FPGA bit stream generation method, device and equipment
Through automated strategy combination and layout and routing optimization, the problem of low bitstream generation efficiency in FPGA prototype verification is solved, efficient bitstream generation and timing optimization are achieved, and the efficiency of FPGA prototype verification is improved.
Patent Information
- Application Number
- CN202411142904.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-01-07
AI Technical Summary
The bitstream generation efficiency is low during the FPGA prototype verification process. It is often caused by wiring failure and excessive resource usage and timing problems, which leads to the Implementation stage that requires waiting for many hours and manually adjusting the strategy is time-consuming, which affects efficiency.
By obtaining the gate-level netlist generated by Vivado's comprehensive Synthesis stage, layout and routing optimization is performed based on policy combinations, and the strategy combination is automatically traversed and modified until the layout and routing is successful, and the timing margin is recorded to judge the bitstream compliance and optimize bitstream generation process.
It improves the efficiency of bitstream generation, reduces the time for manual adjustment of strategies, improves the efficiency of FPGA prototype verification, automates policy selection and allocation, and saves manpower and time.
Smart Images
Figure CN119272683A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of FPGA prototype verification technology, and in particular to an FPGA bit stream generation method, device and equipment. Background Art
[0002] The prototype verification process of Field Programmable Gate Array (FPGA) mainly includes the following steps: converting the application-specific integrated circuit (ASIC) into FPGA code, synthesizing and implementing the FPGA code to generate bitstream, and running and debugging. As the scale of chip design gradually increases, the resources of FPGA devices are limited, which leads to frequent failures in the process of FPGA bitstream generation. Among them, wiring failure is an important reason for the failure of the generated bitstream.
[0003] Usually, the design kit (Vivado) software is used to generate bitstream. In the implementation stage of Vivado, the gate-level netlist generated by synthesis is placed and routed. The result of placement and routing is closely related to the strategy used. By adjusting different strategies, the software can smoothly generate bitstream and optimize timing problems. However, the Implementation stage usually requires waiting for several hours to generate results, and manual adjustment of strategies is required after failure, which makes the efficiency of bitstream generation relatively low, resulting in low efficiency of FPGA prototype verification. Summary of the invention
[0004] The present invention provides a method, device and equipment for generating an FPGA bit stream, which are used to solve the problem of low efficiency of FPGA prototype verification.
[0005] The present invention provides a method for generating an FPGA bit stream, comprising: Obtain a gate-level netlist generated in the synthesis phase of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA; Based on at least one strategy combination and the gate-level netlist, an FPGA bitstream is generated; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0006] According to a method for generating an FPGA bitstream provided by the present invention, the FPGA bitstream is generated based on at least one strategy combination and the gate-level netlist, including: Based on the gate-level netlist, placing and routing the circuit elements on the FPGA; An FPGA bitstream is generated based on the placed and routed circuit elements and at least one strategy combination.
[0007] According to a method for generating an FPGA bitstream provided by the present invention, the circuit element based on layout and routing and at least one strategy combination to generate an FPGA bitstream includes: Step A: traversing each of the strategy combinations based on the circuit elements of the layout and routing; Step B: for each of the strategy combinations, use the target command to execute the project corresponding to the strategy combination and obtain the log file; Step C: judging whether the layout and routing is successful based on the log file; Step D: in the case where the placement and routing fails, modify at least one strategy included in the strategy combination, and repeat steps B to D until the placement and routing succeeds; Step E: When the placement and routing is successful, generate an FPGA bit stream.
[0008] According to a method for generating an FPGA bit stream provided by the present invention, the method further includes: In the case where the placement and routing is successful, recording the worst negative timing margin and the worst hold timing margin; Determining whether the worst negative timing margin and the worst hold timing margin are both greater than a preset value; When the worst negative timing margin and the worst hold timing margin are both greater than the preset value, determining that the generated FPGA bit stream is a bit stream that meets the timing requirements; When at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, the generated FPGA bit stream is determined to be a bit stream that does not meet the timing requirements, the generated FPGA bit stream is saved, and at least one strategy included in the strategy combination is modified and re-run.
[0009] According to a method for generating an FPGA bit stream provided by the present invention, the method further includes: In a case where the placement and routing is successful and at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it is determined not to traverse other strategy combinations in the strategy combinations.
[0010] According to a method for generating an FPGA bit stream provided by the present invention, the method further includes: When the re-run generated FPGA bit stream does not meet the timing requirement, determine to traverse other strategy combinations in the strategy combinations.
[0011] According to a method for generating an FPGA bit stream provided by the present invention, the method further includes: Saving the strategy combination for successful placement and routing, and setting the priority of the strategy combination for successful placement and routing to be the highest; When a new FPGA bit stream needs to be generated, the successful layout and routing strategy combination is executed to generate the new FPGA bit stream.
[0012] The present invention also provides an FPGA bit stream generating device, comprising: An acquisition module is used to acquire a gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA; A generation module is used to generate an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any one of the above-mentioned FPGA bit stream generation methods is implemented.
[0014] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the FPGA bit stream generation method described in any one of the above is implemented.
[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned FPGA bit stream generation methods.
[0016] The FPGA bitstream generation method, device and equipment provided by the present invention obtains the gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes the connection relationship between the circuit elements of the FPGA; based on at least one strategy combination and the gate-level netlist, the FPGA bitstream is generated; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado. Through at least one strategy combination and the gate-level netlist, the FPGA bitstream can be automatically generated, the efficiency of bitstream generation is improved, and thus the efficiency of FPGA prototype verification is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 This is one of the flow charts of the FPGA bit stream generation method provided by the present invention.
[0019] Figure 2 It is a schematic diagram of the layout and wiring process provided by the present invention.
[0020] Figure 3 It is a flow chart of the modification strategy provided by the present invention.
[0021] Figure 4 It is a schematic diagram of successful modification of the strategy provided by the present invention.
[0022] Figure 5 This is the second flow chart of the FPGA bit stream generation method provided by the present invention.
[0023] Figure 6 It is a structural schematic diagram of the FPGA bit stream generating device provided by the present invention.
[0024] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0026] In order to facilitate a clearer understanding of the embodiments of the present application, key terms and related knowledge are first introduced as follows.
[0027] 1. Key terms
[0028] Vivado: Vivado is an adaptive system-on-a-chip (SoC) and FPGA design software. Vivado includes design entry, synthesis, placement and routing, and verification / simulation tools.
[0029] FPGA: Field Programmable Gate Array, field programmable logic gate array.
[0030] ASIC: Application-Specific Integrated Circuit, ASIC is a special chip, a general term for chips specially customized for certain specific needs.
[0031] Synthesis: Synthesis in Vivado is to convert the register transfer level (RTL) code into the basic unit of FPGA.
[0032] Implementation: The implementation in Vivado mainly includes two parts: layout and routing. Layout is to place the synthesized basic units in various locations, and routing is to connect the basic units.
[0033] Python: A programming language.
[0034] Tcl: Commands used in Vivado.
[0035] 2. Related knowledge
[0036] FPGA prototype verification refers to the process of building a working prototype system to verify the correctness and functionality of the design during the hardware design process. FPGA is a programmable gate array that can implement different functions by loading different logic circuits. In chip design, FPGA is widely used to implement prototype verification of the design. The purpose of FPGA prototype verification is to restore the actual usage scenario of the chip as much as possible before the chip is taped out, to fully verify the chip function, and to ensure the reliability and stability of the functional module as much as possible. At the same time, FPGA prototype verification can also shorten the time to market of chip products and reduce chip development costs.
[0037] Using Vivado software to generate the bitstream file required by FPGA mainly involves two steps: Synthesis and Implementation. In the Implementation stage, layout and routing are performed. Layout is to place the basic units generated by synthesis on the FPGA, and routing is to connect the basic units. Therefore, in the Implementation stage, the timing problems caused by layout and routing need to be considered. However, timing violations and layout and routing failures often occur due to excessive resource usage and high fan-out. The most commonly used method to adjust timing violations and layout and routing failures is to modify the strategy used in the Implementation stage.
[0038] The Implementation phase mainly includes three phases: Opt Design, Place Design, and Route Design. Post-Place Phys Opt Design and Post-Route Phys Opt Design are optional. The Opt Design phase can optimize the logic of the design. The Plcae Design phase completes the layout of the design on the FPGA. The Post-Place Phys Opt Design phase estimates the timing based on the location to optimize the logic and layout. The Route Design phase completes the routing on the FPGA. The Post-Route Phys Opt Design phase uses the actual line delay to optimize the logic, placement, and routing. Each phase has different strategies. When the code is updated, the previously used strategy combination may fail, and it is necessary to try again. There are many strategies in each phase, and each selection is random. Manually modifying the strategy will waste a lot of time, making the efficiency of bitstream generation relatively low, resulting in low efficiency of FPGA prototype verification.
[0039] Based on the above problems, the present invention can automatically combine multiple strategies, continuously try and record the results that meet the timing requirements, and can record the successful strategy combination for the next update. At the same time, by automatically modifying the strategy and generating the bitstream file required by the FPGA. The method provided by the present invention can automatically adjust the Implementation strategy in Vivado and efficiently complete the FPGA prototype verification.
[0040] Combine the following Figure 1-Figure 5 The FPGA bit stream generation method of the present invention is described.
[0041] Figure 1 This is one of the flow charts of the FPGA bit stream generation method provided by the present invention, such as Figure 1 As shown, the method includes step 101 and step 102.
[0042] Step 101: Obtain a gate-level netlist generated in the synthesis phase of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA.
[0043] It should be noted that the FPGA bitstream generation method provided by the present invention can be applied to the scenario of FPGA prototype verification, and the executor of the method can be an FPGA bitstream generation device, such as an electronic device, or a control module in the FPGA bitstream generation device for executing the FPGA bitstream generation method.
[0044] Specifically, the premise of Vivado project layout and routing is to perform synthesis and generate a gate-level netlist. After the synthesis is completed, each run is based on the gate-level netlist generated by the synthesis. The kit design Vivado performs the synthesis stage and generates a gate-level netlist, thereby obtaining the gate-level netlist generated by the synthesis stage of Vivado, where the gate-level netlist includes the connection relationship between the circuit elements of the FPGA.
[0045] Step 102: Generate an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the Implementation phase of Vivado.
[0046] Specifically, Vivado provides different strategy combinations for the Implementation phase, and the strategy combination includes at least one strategy, and the strategy is used to optimize the placement and routing of the FPGA in the Implementation phase of Vivado. Based on the at least one strategy combination and the gate-level netlist, an FPGA bitstream can be generated.
[0047] The FPGA bitstream generation method provided by the present invention obtains the gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes the connection relationship between the circuit elements of the FPGA; based on at least one strategy combination and the gate-level netlist, the FPGA bitstream is generated; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado. Through at least one strategy combination and the gate-level netlist, the FPGA bitstream can be automatically generated, the efficiency of bitstream generation is improved, and thus the efficiency of FPGA prototype verification is improved.
[0048] Optionally, a specific implementation of step 102 includes: Based on the gate-level netlist, the circuit elements are laid out and routed on the FPGA; and based on the laid-out circuit elements and at least one strategy combination, an FPGA bitstream is generated.
[0049] Specifically, in the implementation phase of Vivado, according to the connection relationship between the circuit elements of the FPGA included in the gate-level netlist, the circuit elements are laid out and routed on the FPGA, that is, the circuit elements are placed on the FPGA and then connected. Based on the laid out and routed circuit elements and at least one strategy combination, an FPGA bitstream can be generated.
[0050] Optionally, the circuit element based on the placement and routing and at least one strategy combination to generate an FPGA bitstream includes: Step A: Based on the circuit elements of the layout and routing, traverse each of the strategy combinations.
[0051] Step B: For each of the strategy combinations, use the target command to execute the project corresponding to the strategy combination and obtain the log file.
[0052] Specifically, the target command is a Tcl command: set_property stratety {strategy combination name}[get_runs impl_1], where impl_1 represents the project corresponding to the strategy combination. The layout and routing strategy of imp1_1 can be modified. The strategy combination name is provided by Vivado. It is traversed in Python. After each completion, the Vivado log file can be read and analyzed.
[0053] In the process of traversing each strategy combination, for each strategy combination, use the target command to execute the project corresponding to the strategy combination and obtain the log file.
[0054] Step C: Based on the log file, determine whether the placement and routing is successful.
[0055] Step D: in the case where the placement and routing fails, modify at least one strategy included in the strategy combination, and repeat steps B to D until the placement and routing succeeds.
[0056] Specifically, in the case where the placement and routing fails, at least one strategy included in the currently traversed strategy combination may be modified, and after the modification is completed, steps B to D are repeatedly executed until the placement and routing succeeds.
[0057] It should be noted that placement and routing includes the following five stages: Opt Design, Plcae Design, Post-Place Phys Opt Design, Route Design, and Post-Route Phys Opt Design, of which Post-Place Phys Opt Design and Post-Route Phys Opt Design are optional. The strategy is applied to the Opt Design, Plcae Design, Post-Place Phys Opt Design, Route Design, or Post-Route Phys OptDesign stages. After placement and routing is completed, a write bit operation (Write Bitstream) is performed.
[0058] Figure 2 It is a schematic diagram of the layout and wiring process provided by the present invention, such as Figure 2 As shown in the figure, the placement and routing includes five stages: Opt Design, Place Design, Post-Place Phys Opt Design, Route Design, and Post-Route Phys Opt Design. After the placement and routing is completed, the write bit operation is performed.
[0059] In the Opt Design phase, the design logic is optimized. The strategy can be modified using the following tcl command: set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE {strategy combination name} [get_runs impl_1].
[0060] The Place Design phase completes the layout of the design on the FPGA. The strategy can be modified using the following tcl command: set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE {strategy combination name}[get_runs impl_1].
[0061] The Post-Place Phys Opt Design stage is used to optimize logic and layout based on location estimation timing. You can use the following tcl commands to choose whether to use this option and modify the strategy: set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true / false [get_runsimpl_1]; set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE {strategy combination name} [get_runs impl_1].
[0062] The routing on the FPGA is completed in the Route Design phase. The strategy can be modified using the following tcl command: set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE {strategy combination name}[get_runs impl_1].
[0063] The Post-Route Phys Opt Design phase uses actual line delays to optimize logic, placement, and routing. You can use the following tcl commands to select whether to use this option and modify the strategy: set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true / false [get_
[0064] runsimpl_1]; set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS. DIRECTIVE {strategy combination name} [get_runs impl_1].
[0065] Each stage has corresponding strategies for different situations. Based on the currently traversed strategy combination, the strategy is modified to the default option first. By continuously traversing and modifying the strategy, the project can successfully generate a bitstream file that meets the timing.
[0066] Optionally, when the placement and routing fails and occurs in the Opt Design and Place Design stages, modify the strategies corresponding to the Opt Design and / or Place Design stages. Alternatively, when the placement and routing fails and occurs in the Route Design stage, record the number of routing failures, which to a certain extent can reflect the effect of the strategy combination on the project, and modify the strategies corresponding to the routing stage and re-implement them.
[0067] Step E: When the placement and routing is successful, generate an FPGA bit stream.
[0068] Specifically, when the placement and routing is successful, an FPGA bit stream may be generated and saved.
[0069] Optionally, the method further comprises: In the case where the layout and routing is successful, the worst negative timing margin and the worst hold timing margin are recorded; it is determined whether the worst negative timing margin and the worst hold timing margin are both greater than preset values; in the case where the worst negative timing margin and the worst hold timing margin are both greater than the preset values, it is determined that the generated FPGA bit stream is a bit stream that meets the timing requirements; in the case where at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it is determined that the generated FPGA bit stream is a bit stream that does not meet the timing requirements, the generated FPGA bit stream is saved, and at least one strategy included in the strategy combination is modified and re-run.
[0070] Specifically, the preset value can be 0. When the layout and routing is successful, the worst negative timing margin (WNS) and the worst hold timing margin (WHS) generated at the end are recorded. It is determined whether the worst negative timing margin and the worst hold timing margin are both greater than the preset value, that is, whether they are both greater than 0. When the worst negative timing margin and the worst hold timing margin are both greater than the preset value, the process ends, and it is determined that the generated FPGA bitstream is a bitstream that meets the timing requirements. When at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it is determined that the generated FPGA bitstream is a bitstream that does not meet the timing requirements, the generated FPGA bitstream is saved, and at least one strategy included in the strategy combination is modified and re-run, that is, at least one strategy in the currently traversed strategy combination is modified, and the above steps B-D are re-executed.
[0071] Figure 3 It is a flow chart of the modification strategy provided by the present invention, such as Figure 3As shown, it includes steps 301 to 307.
[0072] Step 301: For each strategy combination, use the target command to execute the project corresponding to the strategy combination and obtain the log file.
[0073] Step 302: Based on the log file, determine whether the placement and routing is successful. If the placement and routing fails, go to step 303; if the placement and routing is successful, go to step 304.
[0074] Step 303, modify at least one strategy included in the strategy combination. For example, when the placement and routing fails and occurs in the OptDesign and Place Design stages, modify the strategy corresponding to the Opt Design and / or Place Design stages. Alternatively, when the placement and routing fails and occurs in the Route Design stage, record the number of routing failures, which can reflect the effect of the strategy combination on the project to a certain extent, and modify the strategy corresponding to the Route Design stage and re-implement it.
[0075] Step 304: Record the worst negative timing margin and the worst hold timing margin.
[0076] Step 305: Determine whether the worst negative timing margin and the worst hold timing margin are both greater than a preset value. If both the worst negative timing margin and the worst hold timing margin are greater than the preset value, go to step 306; if at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, go to step 307.
[0077] Step 306: Determine whether the generated FPGA bit stream is a bit stream that meets the timing requirements.
[0078] Step 307: Determine that the generated FPGA bit stream is a bit stream that does not meet the timing requirements, and save the generated FPGA bit stream.
[0079] Optionally, the method further comprises: In a case where the placement and routing is successful and at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it is determined not to traverse other strategy combinations in the strategy combinations.
[0080] Specifically, when the layout and routing is successful and at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it means that the layout and routing is successful but the timing is violated, and it is determined not to traverse other strategy combinations in the strategy combinations, and based on the currently traversed strategy combination or the strategy combination corresponding to the strategy with the least number of failures in the routing stage, at least one strategy included in the currently traversed strategy combination or the strategy with the least number of failures in the routing stage is modified, and the project corresponding to the strategy combination is re-executed to generate a new FPGA bitstream.
[0081] Optionally, the method further comprises: When the re-run generated FPGA bit stream does not meet the timing requirement, determine to traverse other strategy combinations in the strategy combinations.
[0082] Specifically, when the re-run generated FPGA bit stream does not meet the timing requirement, it can be determined to continue traversing other strategy combinations in each strategy combination.
[0083] Optionally, the method further comprises: The successful layout and routing strategy combination is saved, and the priority of the successful layout and routing strategy combination is set to be the highest; when the latest FPGA bit stream needs to be generated, the successful layout and routing strategy combination is executed to generate the latest FPGA bit stream.
[0084] Specifically, for a constantly updated project, the previously successful strategy has a reference significance for the latest project, so after each success, the successful layout and routing strategy combination is saved, and the priority of the successful layout and routing strategy combination is set to be the highest. When the latest bitstream is to be generated, the successful layout and routing strategy combination is executed.
[0085] The method provided by the present invention can traverse different strategy combinations in multiple projects respectively, that is, each project corresponds to a strategy combination, and it is ensured that each strategy combination will only appear once. By modifying [get_runs impl_1] in the tcl command, imp1_1 can be modified to other project names. When all processes are running, a new strategy combination waits for imp to be released, wherein the new strategy combination is a strategy combination of a modified strategy or a measurement combination that has not been traversed, and when imp is idle, the new strategy combination is immediately run.
[0086] Figure 4 is a schematic diagram of a successful strategy modification provided by the present invention, such as Figure 4As shown, select the strategy combination (Performance_WLBlockPlacement), which has the least number of strategy routing failures. This strategy combination includes 4 strategies, namely 3 Explore and 1 WLDrivenblockPlacement; among them, the first Explore corresponds to the Opt Design stage, WLDrivenblockPlacement corresponds to the Plcae Design stage, the second Explore corresponds to the Post-Place Phys Opt Design stage, and the third Explore corresponds to the Route Design stage. Use the tcl command to execute the project corresponding to this strategy combination. In the case of layout and routing failure, modify the strategies of the Opt Design and RouteDesign stages, modify the strategy of the Opt Design stage to ExploreArea, and modify the strategy of the Route Design stage to HigherDelayCost, and execute the project corresponding to this strategy combination. At this time, the layout and routing are successful, and an FPGA bitstream that meets the timing requirements is generated.
[0087] Figure 5 FIG. 2 is a flow chart of the FPGA bit stream generation method provided by the present invention. Figure 5 As shown, the method includes steps 501 to 515.
[0088] Step 501: Obtain a gate-level netlist generated in the synthesis phase of the Vivado design suite, where the gate-level netlist includes connection relationships between circuit elements of the FPGA.
[0089] Step 502: Place and route circuit elements on the FPGA based on the gate-level netlist.
[0090] Step 503: traverse each strategy combination based on the circuit elements of the layout and routing.
[0091] Step 504: For each strategy combination, use the target command to execute the project corresponding to the strategy combination and obtain the log file.
[0092] Step 505: Based on the log file, determine whether the placement and routing is successful. If the placement and routing fails, go to step 506; if the placement and routing is successful, go to step 507.
[0093] Step 506: Modify at least one policy included in the policy combination.
[0094] Step 507: Generate FPGA bitstream.
[0095] Step 508: Record the worst negative timing margin and the worst hold timing margin.
[0096] Step 509: Determine whether the worst negative timing margin and the worst hold timing margin are both greater than a preset value. If both the worst negative timing margin and the worst hold timing margin are greater than the preset value, go to step 510; if at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, go to step 511.
[0097] Step 510: Determine whether the generated FPGA bit stream is a bit stream that meets the timing requirements.
[0098] Step 511: Save the generated FPGA bitstream, modify at least one strategy included in the strategy combination, and re-run.
[0099] Step 512: Determine not to traverse other strategy combinations in each strategy combination.
[0100] Step 513: When the re-generated FPGA bit stream does not meet the timing requirement, determine to traverse other strategy combinations in each strategy combination.
[0101] Step 514: Save the strategy combination for successful placement and routing, and set the priority of the strategy combination for successful placement and routing to be the highest.
[0102] Step 515: When a new FPGA bitstream needs to be generated, execute the successful placement and routing strategy combination to generate a new FPGA bitstream.
[0103] The FPGA bitstream generation method provided by the present invention automatically combines various strategies to obtain multiple strategy combinations. Different strategy combinations will have different effects on the project, and can generate a bitstream file that meets the timing requirements; traverse multiple strategy combinations, and in the case of layout and routing failure, modify at least one strategy included in the strategy combination to automatically complete the layout and routing stage of the project, automatically optimize the project timing, and obtain a bitstream that meets the timing requirements. The method provided by the present invention can automatically complete operations such as strategy selection, allocation, and project operation, and can be performed simultaneously in multiple projects. Multiple projects share a set of traversal schemes, and the strategies included in the strategy combination are automatically allocated to each project. A set of strategies will not be reused. Multiple projects run in parallel, and a bitstream that meets the timing requirements is quickly generated, which saves a lot of manpower and time. Moreover, in the process of continuous updating of the project, the strategy combinations that successfully layout and route are saved. These strategy combinations have reference significance for the continuously updated projects. The priority of the strategy combination that successfully layout and route is increased, which can accelerate the generation of the bitstream file of the new project, improve the efficiency of bitstream generation, and thus improve the efficiency of FPGA prototype verification.
[0104] The FPGA bit stream generating device provided by the present invention is described below. The FPGA bit stream generating device described below and the FPGA bit stream generating method described above can be referenced to each other.
[0105] Figure 6 : is a schematic diagram of the structure of the FPGA bit stream generating device provided by the present invention, such as Figure 6 As shown, the FPGA bit stream generating device 600 includes an acquiring module 601 and a generating module 602; wherein,
[0106] An acquisition module 601 is used to acquire a gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA; The generation module 602 is used to generate an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0107] The FPGA bitstream generation device provided by the present invention obtains the gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes the connection relationship between the circuit elements of the FPGA; based on at least one strategy combination and the gate-level netlist, the FPGA bitstream is generated; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado. Through at least one strategy combination and the gate-level netlist, the FPGA bitstream can be automatically generated, the efficiency of bitstream generation is improved, and thus the efficiency of FPGA prototype verification is improved.
[0108] Optionally, the generating module 602 is specifically configured to: Based on the gate-level netlist, placing and routing the circuit elements on the FPGA; An FPGA bitstream is generated based on the placed and routed circuit elements and at least one strategy combination.
[0109] Optionally, the generating module 602 is further configured to: Step A: traversing each of the strategy combinations based on the circuit elements of the layout and routing; Step B: for each of the strategy combinations, use the target command to execute the project corresponding to the strategy combination and obtain the log file; Step C: judging whether the layout and routing is successful based on the log file; Step D: in the case where the placement and routing fails, modify at least one strategy included in the strategy combination, and repeat steps B to D until the placement and routing succeeds; Step E: When the placement and routing is successful, generate an FPGA bit stream.
[0110] Optionally, the FPGA bit stream generating device 600 further includes: A recording module, used for recording the worst negative timing margin and the worst hold timing margin when the placement and routing is successful; A judging module, used for judging whether the worst negative timing margin and the worst hold timing margin are both greater than a preset value; A first determination module, configured to determine that the generated FPGA bit stream is a bit stream that meets the timing requirement when both the worst negative timing margin and the worst hold timing margin are greater than the preset value; The second determination module is used to determine that the generated FPGA bit stream is a bit stream that does not meet the timing requirements when at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, save the generated FPGA bit stream, and modify at least one strategy included in the strategy combination and re-run it.
[0111] Optionally, the FPGA bit stream generating device 600 further includes: The third determination module is used to determine not to traverse other strategy combinations in the strategy combinations when the placement and routing is successful and at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value.
[0112] Optionally, the FPGA bit stream generating device 600 further includes: The fourth determination module is used to determine to traverse other strategy combinations in the strategy combinations when the re-run generated FPGA bit stream does not meet the timing requirement.
[0113] Optionally, the FPGA bit stream generating device 600 further includes: A saving module, used for saving the strategy combination of successful layout and routing, and setting the priority of the strategy combination of successful layout and routing to be the highest; The execution module is used to execute the successful layout and routing strategy combination to generate the new FPGA bit stream when a new FPGA bit stream needs to be generated.
[0114] Figure 7 is a schematic diagram of the physical structure of an electronic device provided by the present invention, such as Figure 7As shown, the electronic device 700 may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the FPGA bitstream generation method, which includes: obtaining a gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes the connection relationship between the circuit elements of the FPGA; generating an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0115] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.
[0116] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the FPGA bitstream generation method provided by the above-mentioned methods, the method including: obtaining a gate-level netlist generated in the synthesis stage of the kit design Vivado, the gate-level netlist including the connection relationship between the circuit elements of the FPGA; generating an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0117] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the FPGA bitstream generation method provided by the above-mentioned methods, the method comprising: obtaining a gate-level netlist generated in the synthesis stage of the kit design Vivado, the gate-level netlist including the connection relationship between the circuit elements of the FPGA; generating an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
[0118] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for generating an FPGA bitstream, characterized in that: include: Obtain a gate-level netlist generated in the synthesis phase of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA; Based on at least one strategy combination and the gate-level netlist, an FPGA bitstream is generated; wherein each strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the Implementation stage of Vivado.
2. The FPGA bit stream generation method according to claim 1, characterized in that: The generating of the FPGA bitstream based on at least one strategy combination and the gate-level netlist comprises: Based on the gate-level netlist, placing and routing the circuit elements on the FPGA; An FPGA bitstream is generated based on the placed and routed circuit elements and at least one strategy combination.
3. The FPGA bitstream generation method according to claim 2, characterized in that: The circuit elements and at least one strategy combination based on the layout and routing generate an FPGA bitstream, including: Step A: traversing each of the strategy combinations based on the circuit elements of the layout and routing; Step B: for each of the strategy combinations, use the target command to execute the project corresponding to the strategy combination and obtain the log file; Step C: judging whether the layout and routing is successful based on the log file; Step D: in the case where the placement and routing fails, modify at least one strategy included in the strategy combination, and repeat steps B to D until the placement and routing succeeds; Step E: When the placement and routing is successful, generate an FPGA bit stream.
4. The FPGA bit stream generation method according to claim 3, characterized in that: The method further comprises: In the case where the placement and routing is successful, recording the worst negative timing margin and the worst hold timing margin; Determining whether the worst negative timing margin and the worst hold timing margin are both greater than a preset value; When the worst negative timing margin and the worst hold timing margin are both greater than the preset value, determining that the generated FPGA bit stream is a bit stream that meets the timing requirements; When at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, the generated FPGA bit stream is determined to be a bit stream that does not meet the timing requirements, the generated FPGA bit stream is saved, and at least one strategy included in the strategy combination is modified and re-run.
5. The FPGA bit stream generation method according to claim 4, characterized in that: The method further comprises: In a case where the placement and routing is successful and at least one of the worst negative timing margin and the worst hold timing margin is not greater than the preset value, it is determined not to traverse other strategy combinations in the strategy combinations.
6. The FPGA bit stream generation method according to claim 4, characterized in that: The method further comprises: When the re-run generated FPGA bit stream does not meet the timing requirement, determine to traverse other strategy combinations in the strategy combinations.
7. The FPGA bit stream generation method according to any one of claims 1 to 6, characterized in that: The method further comprises: Saving the strategy combination for successful placement and routing, and setting the priority of the strategy combination for successful placement and routing to be the highest; When a new FPGA bit stream needs to be generated, the successful layout and routing strategy combination is executed to generate the new FPGA bit stream.
8. An FPGA bit stream generating device, characterized in that: include: An acquisition module is used to acquire a gate-level netlist generated in the synthesis stage of the kit design Vivado, wherein the gate-level netlist includes connection relationships between circuit elements of the FPGA; A generation module is used to generate an FPGA bitstream based on at least one strategy combination and the gate-level netlist; wherein the strategy combination includes at least one strategy, and the strategy is used to optimize the layout and routing of the FPGA in the implementation stage of Vivado.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the FPGA bit stream generation method according to any one of claims 1 to 7 is implemented.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the FPGA bitstream generation method according to any one of claims 1 to 7 is implemented.