53results about How to "Optimizing place and route" patented technology

The invention relates to a centralized-cache device and design method based on field-programmable gate arrays and relates to the field of field-programmable gate array design, and the centralized-cache device and design method is adaptive to at least two same functional modules. The device comprises a time division multiplexing control unit, a signal serialization unit, a centralizing storage register, a combinational logic unit and a signal parallelization unit. The time division multiplexing control unit is used for dividing the period into two time slots with the same length of time, each time slot corresponds to one functional module sequentially, and each functional module performs input signal processing in the corresponded time slot. The signal serialization unit is used for converting the parallel input signals of each functional module into serial input signals. The centralizing storage register is used for storing the register of each functional module and reading and writing the register of the functional module in the time slot corresponding to the functional module. The combinational logic unit is used for combinational logic of input signal processing of single functional module. The signal parallelization unit is used for restoring serial output signals as parallel output signals after the input signals of each functional module are processed.

The invention discloses a field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and an implementing method thereof. The AES processor comprises an interface storage area buffer module, a control module, an AES encryption and decryption module, a read-only memory lookup table module, a register module and an output module. The implementing method for the processor comprises the following steps: 1, initializing a data table; 2, performing initial setting; 3, receiving data; 4, reading the data; 5, selecting a data processing mode; 6, judging whether the encryption and decryption are finished; and 7, outputting a result. The invention mainly solves the problems that an AES processor is controlled complicatedly and modules have low portability, reliability, safety and processing speed in the prior art; and an improved algorithm and a lookup table-based method are used. The AES processor has all levels of structures which are fixed, is simple in control logic, comprises the modules with high portability, is suitable to be implemented in a singlechip FPGA, and has the characteristics of high speed and high accuracy.

The application discloses a synchronous FIFO, which includes a data storage circuit, a first logic circuit, a second logic circuit and an indication circuit. The data storage circuit includes N first registers, N first multiplexers and N first decision devices; N is a positive integer; the first registers are alternately connected to the first multiplexers. The synchronous FIFO is based on registers to build the storage required for FIFO, mainly including registers, multiplexers, and decision devices. RAM is discarded, no RAM is occupied, no RAM read and write enable and address control are required, and RAM resource waste can be avoided. It occupies less resources in the design with less memory depth requirements, greatly reduces the chip area, saves cost, and is more convenient for layout and wiring.

The invention discloses a routing method based on hierarchical Q-routing planning, which is to obtain high-efficiency data transmission links through global layered parallel planning by sensing network congestion and interconnection link usage. The algorithm of the present invention is a routing algorithm based on a lookup table. The routing algorithm stores the planned direction in the routing table in the learning module of each router node, and the data packet is obtained by accessing the routing table in the learning module of the router node. path information. The present invention constructs a hierarchical design on the basis of split Q-routing, utilizes multi-layer congestion sensor and multi-layer parallel learning to greatly reduce the convergence time of the algorithm, thereby improving the data transmission efficiency of the on-chip network, and also compressing the routing table , reducing hardware resource consumption.

The invention discloses a one-bit full subtracter circuit, which is suitable for subtraction and division operation. The circuit structurally comprises nine NOR gates. Inputs comprise a minuend A, a subtrahend B and a borrow bit Cin from a lower bit; outputs comprise a difference bit S and a borrow bit Cout to a high bit. A process from the input to the difference bit output or the borrow bit output passes through six stages of NOR gates, the circuit structure is symmetrical and the locating and the wiring are facilitated. The one-bit full subtracter circuit can be directly used for subtraction, the borrow bit output of the highest bit directly expresses a sign bit and the indirect operation process of subtraction completed by using an adding circuit after negation and plus one of subtrahend is avoided.