53results about How to "Optimizing place and route" patented technology

The invention provides a method and a device of restraining narrow-band interference. The method specifically comprises the following steps of detecting a frequency which corresponds to the narrow-band interference when a system has the narrow-band interference; detecting whether a higher harmonic frequency of a system clock falls into the operating frequency range of the system when the frequency which corresponds to the narrow-band interference is the higher harmonic frequency of the system clock; when the higher harmonic frequency of the system clock falls into the operating frequency range of the system, adjusting the frequency of the system clock so as to cause the higher harmonic frequency of the system clock to fall out of the operating frequency range of the system. According to the method and the system, the influence of the narrow-band interference of the system on the system performance is solved, and the equipment cost is reduced.

The invention relates to the technical field of a system on a chip and discloses a system on a chip and a resting and arousing method thereof. In the system on the chip, a main voltage area and an auxiliary voltage area are designed, the auxiliary voltage area in which a micro-control unit is arranged can be closed or stepped down, information in the auxiliary voltage area is stored into a memory in the main voltage area by the micro-control unit before the auxiliary voltage area is powered down, the dynamic power consumption and the static power consumption of a digital circuit can be lowered, and the condition that the necessary information can not be lost can also be ensured; and moreover, the system on the chip does not need to depend on the support of a specific process or a specific component, which is very beneficial to arranging and wiring. After the system on the chip is aroused, the auxiliary voltage area is at a resetting state, and the occurrence of confusion of the working of a circuit is avoided; and until the voltage of the auxiliary voltage area is restored to a normal value, the auxiliary voltage area is released and reset, so that the entire circuit is in normal working anew.

The invention discloses a static random-access memory, which comprises a writing control circuit module, a first revert circuit, a second reverse circuit and a reading-out buffer circuit, wherein the writing control circuit module is used for controlling the static random access memory to write in information; the first reverse circuit comprises a PMOS (p-channel metal oxide semiconductor) transistor and a first resistor, is coupled to the writing control circuit module to form a first storage node; the second reverse circuit comprises a second NMOS (n-channel metal oxide semiconductor) transistor and a second resistor and is connected between a voltage source and a complementary voltage source; and the reading-out buffer circuit is coupled to a word-reading line and a bit-reading line and is commonly coupled to the first reverse circuit and the second reverse circuit to form a second storage node. According to the invention, the dual-port SRAM (static random access memory) is realized by using four transistors and two resistors, so that the improvement on the reading and writing speed is facilitated, and the benefits of simple circuit, less occupied space and convenience in capacity extension and layout wiring are realized.

The invention discloses an electric energy metering method which comprises the following steps: detecting whether an electric energy metering chip for electric energy metering loses power; during power failure, switching system power supply of the electric energy metering chip to a backup electricity-taking mode; switching an electric energy metering clock of the electric energy metering chip to a low-frequency clock; and metering the electric energy in a preset time period. According to the low-frequency metering scheme provided in the invention, even if under the mode of circuit phase failure or electricity stealing, calculation of the effective value of the current can still be carried out, and meanwhile, power consumption is reduced; and the method provides apparent power and apparent power pulse output without depending on the support of specific process or devices, facilitates locating and wiring very well, and can guarantee that necessary information on the electric energy metering chip is not lost.

The invention provides a PCIe board card resource allocation method and device, and the method comprises the following steps: dividing the allocation types of PCIe board cards according to the numberof channels of the PCIe board cards, and coding the allocation types and corresponding voltage intervals; detecting the voltage of the PCIe board card in response to the connection of the PCIe board card to the mainboard; comparing the voltage with the voltage interval and judging which code the voltage is located in the corresponding voltage interval; enabling the mainboard to call the distribution type of the PCIe corresponding to the voltage interval to perform distribution. By using the scheme of the invention, the use of IO ports of the mainboard can be greatly reduced, PCB layout and wiring are facilitated, and the method is simple to implement, low in software cost and beneficial for users to realize remote monitoring.

The invention discloses a static random access memory comprising a writing control circuit module, a first inverter circuit, a second inverter circuit and a reading buffer circuit, wherein the writing control circuit module is used for controlling the static random access memory; the first inverter circuit is coupled with the writing control circuit module to form a first storage node; the second inverter circuit is connected between a voltage source and a complementary voltage source; and the reading buffer circuit is coupled to a reading word line and a reading bit line and is coupled together with the first inverter circuit and the second inverter circuit to form a second storage node. The invention isolates the reading bit line from the second storage node by utilizing the reading buffer circuit and controls the state of information written by the static random access memory, thereby solving the problem of reading interference existing in the prior art.

The invention relates to a high-speed shadow memory control structure, which comprises two memories which are mutual shadows. The high-speed shadow memory control structure has the main technical characteristics that the two memories are connected with a shadow memory controller through two groups of data buses, address buses and control signals respectively; the shadow memory controller is also connected with two main control chips through the other two groups of address data buses, address buses and control signals respectively; and a bus switching signal port of the shadow memory controller is connected with any one of the main control chips or other logic switching chip. The independent control functions of the main control chips to the shadow memories are achieved by adopting a fully parallel processing structure, the two main control chips have full read-write rights for the current accessed memory in an entire time range so as to improve the data access speed and read accuracy, and the high-speed shadow memory control structure has the characteristics of flexible control, convenient use and the like.

The invention provides an HPS-based OSD interface switching scheme of an FPGA and belongs to the field of computers. According to the scheme, the FPGA with a hardcore (HPS) is used as a control unit, a peripheral module of the hardcore is set up through the FPGA, RGA signals are output, so that pictures are displayed on a display screen through a DA conversion chip, and switching between the pictures is controlled through a keyboard. Through the scheme, power consumption is reduced, the number of chips is reduced, and locating and wiring of a PCB of a management panel can be performed conveniently.

The invention discloses a multi-source access scheduling method and device for registers of a network interface chip.The method comprises the following steps that register access requests are cached in a classified mode according to sources; quick/slow register access rings are structured based on access speed differences; a double-ring parallel scheduling strategy is adopted, and the cached requests are allocated to the quick/slow register access rings according to weight allocation and access addresses; the quick/slow register access rings handle the access requests in parallel and return register access responses.The device comprises a request classifying unit, a request classified caching unit, a quick access scheduling module, a slow access scheduling module, the quick resister access ring and the slow register access ring.According to the multi-source access scheduling method and device for the registers of the network interface chip, the double-ring parallel scheduling strategy is adopted, different request sources are reasonably scheduled, the differentiated demand for access speeds of different request sources is met, an in-band and out-band combined multi-way configuring and monitoring function is provided, layout and wiring at the back end can be easier, and good expandability is achieved.

The invention provides a differential touch detection circuit and a touch judgment method adopting the differential touch detection circuit. The differential touch detection circuit comprises a firstchannel circuit, a second channel circuit, a differential operational amplifier and an analog-to-digital converter, and the first channel circuit and the second channel circuit have the same connection structure. Wherein the first channel circuit corresponds to a first channel, and the first parasitic capacitor Cx1 is coupled with the first channel circuit through the first touch sensor TK1; the first channel circuit is coupled to a negative input end voltage VIN and a positive output end voltage VOP of the differential operational amplifier. The second channel circuit corresponds to a secondchannel, and a second parasitic capacitor Cx2 is coupled with the second channel circuit through a second touch sensor TK2; the second channel circuit is coupled to the positive electrode input end voltage VIP and the positive electrode output end voltage VON of the differential operational amplifier. Wherein two input ends of the analog-to-digital converter are respectively coupled with the VOP and the VON, and the output Vout of the analog-to-digital converter is the difference between the VOP and the VON.

The utility model discloses a generation method and a device of CKE signals and belongs to the field of communication. The generation method includes: obtaining frequencies of the clock signals of N Masters and frequencies of the clock signals of buses which are connected with the N Masters, the clock signals of the N Masters and the clock signals of the buses are generated based on the same source clock, N is not less than 2 and N is an integer, the nth CKE signal is produced according to the frequency of the nth clock signal of the Master and the frequency of the clock signal of the buses, n belongs to the range of 1, 2, ...N; The nth CKE signal is provided to the nth Master. The generation device of CKE signals comprises obtaining modules, generation modules and providing modules. Because every Master can individually provide a CKE signal, the generation method and the device of CKE signals has the advantages of greatly reducing the numbers of driving circuits of the CKE and being easy for operators to make placement and routing.

The invention discloses a hardware implementation device and method of an activation function, and belongs to the technical field of hardware implementation of function calculation. Aiming at the problem that in the prior art, high performance and hardware resources are difficult to balance when the hardware of a conventional method achieves an activation function, the device comprises an e-exponential calculation module and a CORDIC division module; an input signal calculates an e-exponential e-x or an e-exponential e2x in the e-exponential calculation module through a small index lookup table with 2 as the base and shifting and additive operation. Based on carry-save addition, an adder achieves the calculation function like I1 + I2-I3; based on a CORDIC algorithm, a CORDIC division module calculates a division function result shown in the specification through multiple times of iteration. The circuit structure is simple, no complex control logic exists, circuit layout and wiring areconvenient, the calculation precision is high, sigmoid and tanh activation function calculation in any input range is supported during calculation, and the problem that a traditional hardware implementation method cannot balance performance and hardware resources is solved.

The invention provides a noise processing method and a circuit after a noise processing process. The circuit after the noise processing process comprises at least two disturbed lines and at least one disturbing line. The number of parallel lines among the at least three line does not exceed two. Parallel portions exist between the disturbed lines and the disturbing line. Common parallel portions exist between the disturbed lines. The width of a gap between the common parallel portions is wider than or equal with a sum value of two times the width of a minimum line gap and the width of the line.

The invention provides an optimized BCH (Bose-Chaudhuri-Hocquenghem) decoding method and device in a flash controller. The optimized BCH decoding method comprises the following steps of: reading flash memory information, storing the flash memory information in an FIFO (First Input First Output), and computing an adjoint functor according to the read information; solving a key equation, namely computing an error location polynomial based on an iterative algorithm according to the adjoint functor; verifying a root through Chien Search according to the error location polynomial to determine an error location; and performing anti-error correction on error information of the error location so as to obtain error correction information in a flash memory. In the step of solving the key equation, the conventional riBM algorithm by using characteristics of a binary BCH code is optimized, so that logic is almost reduced to half; and iterative delay is only 1/2 of original algorithm, so that the technical difficulty in ECC (Error Correction Code) logic complexity in a flash memory controller is overcome. According to the optimized BCH decoding method and device, due to high-level symmetry and structuralization of circuits, balancing on logic complexity and decoding delay by adopting a laminated means is facilitated on one hand, wiring layout at the rear end of a VLSI (Very Large Scale Integrated Circuit) is facilitated on the other hand. The optimized riBM algorithm can also be applied to digital television broadcasting, space communication and other application fields.

The invention discloses a system and a method for generating and analyzing a verilog circuit netlist compiler, which can greatly reduce the workload of compiling the compiler, can optimize the analysis process in a targeted manner, improves the analysis efficiency, is simple in generation process, small in workload, clear in logic structure and high in expandability, and facilitates the development of subsequent layout and wiring and the like. The system comprises a Lex translator, a Yacc compiler and a C compiler. The Lex translator is configured to analyze the Lex source program into a lexical analyzer file compiled by C; the Yacc compiler is configured to analyze the grammar description file into a syntactic analyzer file compiled by C; and the C compiler is configured to generate an analytic verilog grammar compiler from the lexical analyzer file compiled by the C and the syntactic analyzer file compiled by the C.