Weak correlation multiport parallel store controller
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A storage controller, multi-port technology, used in instruments, electrical digital data processing, input/output to record carriers, etc. Not very high, low flexibility, etc., to achieve the effect of facilitating layout and wiring, simple structure, and high flexibility
Inactive Publication Date: 2012-08-01
BEIJING INSTITUTE OF TECHNOLOGYGY
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[0003] The disadvantages of the above two types of multi-port memory are: the first type of multi-port memory only supports the reading and writing of fixed-length data, and the flexibility is low; the second type of multi-port memory can only be applied to processors with low frequency Occasions, so it is not applicable to multi-core processors and large-capacity L2 shared storage
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Embodiment 1
[0044] A weakly correlated multi-port parallel storage controller in this embodiment, its structural diagram is as follows figure 1 As shown, it is connected with the memory access unit and the storage body in the peripheral equipment, which includes: a memory port module, an arbitration module, an address generation module, and a port transfer module; the memory access unit in the peripheral equipment includes 4 processors (C1~ C4), the storage bank in the peripheral device includes 4 storage blocks (storage block 0 to storage block 3).
[0045] Among the four storage blocks, the storage word width of each storage block is 8 bits, that is, 1 byte.
[0046] The memory port module includes 4 ports (P1~P4), and the priority sequence is set for the 4 ports in advance, the priorities of the 4 ports are all different, and the priority relationship is P1>P2>P3>P4; The functions include: ① Obtain and latch memory access request information from the processor; the memory access request...
Embodiment 2
[0081] A weakly correlated multi-port parallel memory controller in this embodiment has the same structure as that in Embodiment 1, and its working process is specifically:
[0082] Step 1: Set the initial state of each port of the memory port module to be idle. When the processor has a memory access request, perform operations from steps 2 to 7.
[0083] Step 2: In the first clock cycle, processor C1 sends memory access request information to port P1 in the memory port module, wherein the starting address of the data block is 0x00000000, the length of the data block is 64 bytes, and the memory access mode is read; In the third clock cycle, processor C3 sends memory access request information to port P3 in the memory port module, where the starting address of the data block is 0x00000002, the length of the data block is 128 bytes, and the memory access mode is write.
[0084]Step 3: From the 1st to the 2nd clock cycle, the port P1 in the memory port module latches the memory ...
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Abstract
The invention provides a weak correlation multiport parallel store controller, which is connected with a access memory unit in peripheral equipment and a storage stack including a plurality of storage body and can achieve multiport parallel storage between the visiting and storage unit in the peripheral equipment and the storage stack in the peripheral equipment. The weak correlation multiport parallel store controller comprises a storage port module, an arbitration module, an address generation module and a port switching module. The weak correlation multiport parallel store controller has the following advantages of (1) supporting block reading and writing in random lengths and being high in dexterity; (2) enabling transmission of address and data to multiplex in the same group of signal wires to complete, greatly reducing quantity of the transmission signal wires in a system, being favorable for application of distribution and wiring and reducing complexity and cost of the system; and (3) being simple in structure, less in used transmission signal wires and capable of supporting design and achievement of a large-scale multiport storage, and improving efficiency of parallel access memory of a plurality of processors.
Description
technical field [0001] The invention relates to a weakly correlated multi-port parallel memory controller, which belongs to the field of computer architecture and integrated circuit design, and is suitable for the construction of shared memories of multi-core microprocessors and multi-processor systems. Background technique [0002] There are two types of existing multi-port parallel memory controller implementations: ① For a memory controller including m ports, when it controls n memory blocks (chips), use m×n crossbar switches or on-chip Blocks (chips) are connected together, and different ports access different memory blocks or chips at the same time through a crossbar switch or an on-chip network. This type of structured shared memory is common in the L2-level shared memory of most current multi-core processors; where m and n are Positive integer, m ≥ 2 and n ≥ m; ② use a memory chip with a sufficiently high frequency, so that the data of different storage units can be a...
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