Multi-source access scheduling method and device for registers of network interface chip

A technology of network interface and scheduling method, applied in the field of register multi-source access scheduling, can solve problems such as difficulty in meeting NIC chips

Inactive Publication Date: 2016-06-29
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The implementation of the register access method in the prior art is difficult to meet the above three requirements of the register access processing in the NIC chip

Method used

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  • Multi-source access scheduling method and device for registers of network interface chip
  • Multi-source access scheduling method and device for registers of network interface chip
  • Multi-source access scheduling method and device for registers of network interface chip

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Embodiment Construction

[0044] Such as figure 1 As shown, the implementation steps of the register multi-source access scheduling method for the network interface chip in this embodiment are as follows:

[0045] 1) Cache register access requests by source classification: the request classification unit caches register access requests from multiple request sources to the request classification cache unit according to the type of request source;

[0046] 2) Build a fast / slow register access ring based on the difference in access speed: the fast access common module pre-connects register modules including user-programmable registers, some control and status registers in series to form a fast register access ring; the slow access common module will not contain The register modules of user-programmable registers, some control and status registers are connected in series to form a slow register access ring;

[0047] 3) A dual-ring parallel scheduling strategy is adopted, and cached requests are assigned t...

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Abstract

The invention discloses a multi-source access scheduling method and device for registers of a network interface chip.The method comprises the following steps that register access requests are cached in a classified mode according to sources; quick/slow register access rings are structured based on access speed differences; a double-ring parallel scheduling strategy is adopted, and the cached requests are allocated to the quick/slow register access rings according to weight allocation and access addresses; the quick/slow register access rings handle the access requests in parallel and return register access responses.The device comprises a request classifying unit, a request classified caching unit, a quick access scheduling module, a slow access scheduling module, the quick resister access ring and the slow register access ring.According to the multi-source access scheduling method and device for the registers of the network interface chip, the double-ring parallel scheduling strategy is adopted, different request sources are reasonably scheduled, the differentiated demand for access speeds of different request sources is met, an in-band and out-band combined multi-way configuring and monitoring function is provided, layout and wiring at the back end can be easier, and good expandability is achieved.

Description

technical field [0001] The invention relates to a register access technology in a network interface chip, in particular to a register multi-source access scheduling method and device for a network interface chip. Background technique [0002] Network Interface Chip (NetworkInterfaceChip, NIC) is an interconnect communication host interface chip based on the PCIEG3 standard, supports user-level communication operations, and is used for high-speed access to general servers, general computing nodes and autonomous computing nodes. An important prerequisite for implementing user-level communication operations in the NIC is to virtualize hardware resources and form a programming view for each process to exclusively use the hardware to ensure the atomicity of communication operation request processing when multiple processes are executed concurrently. The NIC communication hardware interface implements a virtual port (VirtualPort, VP) mechanism. Each virtual port consists of a set ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
CPCG06F13/1615G06F13/1673G06F13/1689
Inventor 常俊胜肖立权庞征斌王克非董德尊张建民齐星云徐金波赖明澈罗章黎渊
Owner NAT UNIV OF DEFENSE TECH
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