Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A Routing Method Based on Hierarchical q-routing Planning

A layered and routing technology, applied in transmission systems, electrical components, etc., can solve problems such as difficulty in meeting demands, loss of timeliness, and increased power consumption, and achieve the effects of reducing area resource consumption, facilitating layout and wiring, and reducing time

Active Publication Date: 2022-03-15
HEFEI UNIV OF TECH
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can better solve the problems of data delay, power consumption increase and router temperature rise caused by NoC when transmitting large amounts of data
However, as the scale of the on-chip network continues to increase, network congestion will become more and more serious, and the split Q-routing will take too long to plan paths, so that it loses timeliness and cannot meet the demand.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Routing Method Based on Hierarchical q-routing Planning
  • A Routing Method Based on Hierarchical q-routing Planning
  • A Routing Method Based on Hierarchical q-routing Planning

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0063] A routing method based on hierarchical Q-routing planning in this embodiment is implemented in an on-chip network composed of 64 router nodes, 64 resource nodes and several interconnection channels. Refer to figure 1 and figure 2 The shown learning module configuration mode is configured, and the router node includes an input port, an output port, a congestion sensor, a multiplexer, and an access routing table; it is characterized in that the learning module is set in the router node; refer to Figure 4 , the learning module includes: a learning mode arbiter, a hierarchical control module, a routing table selection module, 3 sub-learning modules, and 3 routing tables. You can increase the network structure and the number of sub-learning modules and routing tables to adapt to more router node networks; refer to Figure 7 , the routing method is carried out as follows:

[0064] Step 1: See image 3 , divide all router nodes into a three-layer network structure accordi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a routing method based on hierarchical Q-routing planning, which is to obtain high-efficiency data transmission links through global layered parallel planning by sensing network congestion and interconnection link usage. The algorithm of the present invention is a routing algorithm based on a lookup table. The routing algorithm stores the planned direction in the routing table in the learning module of each router node, and the data packet is obtained by accessing the routing table in the learning module of the router node. path information. The present invention constructs a hierarchical design on the basis of split Q-routing, utilizes multi-layer congestion sensor and multi-layer parallel learning to greatly reduce the convergence time of the algorithm, thereby improving the data transmission efficiency of the on-chip network, and also compressing the routing table , reducing hardware resource consumption.

Description

technical field [0001] The invention belongs to the communication technology field of integrated circuit on-chip network, in particular to an on-chip network routing method based on hierarchical Q-routing planning. Background technique [0002] With the gradual failure of Moore's Law, the development of semiconductor technology has gradually slowed down, and the operating frequency of single-core processors has encountered bottlenecks and is difficult to increase rapidly. The shortcomings of the System on Chip (SoC) with the traditional bus structure such as poor scalability and low parallelism are becoming more and more obvious. In order to increase the operating frequency of the entire chip, a new method other than the traditional bus is needed, that is, Network on Chip (Network on Chip). , NoC) communication. NoC has good scalability and can process the data of multiple IP cores inside the chip in parallel, effectively solving the problems of power consumption, performan...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04L45/12H04L41/12H04L45/00H04L45/24
CPCH04L45/12H04L41/12H04L45/14H04L45/24
Inventor 李桢旻翁晓峰王镜涵李天瑜马宇晴杜高明宋宇鲲
Owner HEFEI UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products