Routing method based on hierarchical Q-routing planning

Abstract

The invention discloses a routing method based on hierarchical Q-routing planning, which is characterized in that a high-efficiency data transmission link is obtained through global hierarchical parallel planning by sensing the congestion condition of a network and the use condition of an interconnection link. The algorithm provided by the invention is a routing algorithm based on a lookup table, the routing algorithm stores a planned direction in a routing table in a learning module of each router node, and a data packet obtains path information by accessing the routing table in the learning module of the router node where the data packet is located. According to the method, a hierarchical design is constructed on the basis of split Q-routing, and the convergence time of the algorithm is greatly shortened by utilizing a multilayer congestion sensor and multilayer parallel learning, so that the on-chip network data transmission efficiency is improved, the routing table is compressed, and the hardware resource consumption is reduced.

Description

technical field [0001] The invention belongs to the communication technology field of integrated circuit on-chip network, in particular to an on-chip network routing method based on hierarchical Q-routing planning. Background technique [0002] With the gradual failure of Moore's Law, the development of semiconductor technology has gradually slowed down, and the operating frequency of single-core processors has encountered bottlenecks and is difficult to increase rapidly. The shortcomings of the System on Chip (SoC) with the traditional bus structure such as poor scalability and low parallelism are becoming more and more obvious. In order to increase the operating frequency of the entire chip, a new method other than the traditional bus is needed, that is, Network on Chip (Network on Chip). , NoC) communication. NoC has good scalability and can process the data of multiple IP cores inside the chip in parallel, effectively solving the problems of power consumption, performan...

AI Technical Summary

Problems solved by technology

It can better solve the problems of data delay, power consumption increase and router temperature rise caused by NoC when transmitting large amounts of data

However, as the scale of the on-chip network continues to increase, network congestion will become more and more serious, and the split Q-routing will take too long to plan paths, so that it loses timeliness and cannot meet the demand.

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