a synchronous fifo

Abstract

The application discloses a synchronous FIFO, which includes a data storage circuit, a first logic circuit, a second logic circuit and an indication circuit. The data storage circuit includes N first registers, N first multiplexers and N first decision devices; N is a positive integer; the first registers are alternately connected to the first multiplexers. The synchronous FIFO is based on registers to build the storage required for FIFO, mainly including registers, multiplexers, and decision devices. RAM is discarded, no RAM is occupied, no RAM read and write enable and address control are required, and RAM resource waste can be avoided. It occupies less resources in the design with less memory depth requirements, greatly reduces the chip area, saves cost, and is more convenient for layout and wiring.

Description

technical field [0001] The present application relates to the technical field of digital circuits, in particular to a synchronous FIFO. Background technique [0002] In the design of digital circuits such as FPGA (Field-Programmable Gate Array, field programmable gate array), FIFO (First Input First Output, first-in-first-out storage) is a commonly used module. FIFO is divided into synchronous FIFO and asynchronous FIFO. The input and output of the synchronous FIFO are the same clock, and the input and output of the asynchronous FIFO are different clocks. The synchronous FIFO is mainly used to cache data or commands to prevent data or command loss, and is mostly used for rate matching or data synchronization between modules to improve system transmission or processing performance. [0003] Such as figure 1 As shown, the current FIFO is mostly based on RAM Random Access Memory (Random Access Memory) as a storage design, and cooperates with controllers, registers, etc. to c...

AI Technical Summary

Problems solved by technology

However, RAM is a dedicated resource. Generally, each resource of this type has dozens of kilobytes of storage, but the quantity is relatively limited. If a large number of FIFOs need to be used in the design, and the required depth of FIFOs is small, this type of resource will be caused. waste of resources

In addition, in chip design, RAM is also a specific resource. No matter how much storage is required for this type of resource, there is a basic area. On this basis, the more storage is required, the larger the occupied area (flow Chips are more expensive and consume more power)

After the design is completed, RAM resources need to be placed separately, and the back-end layout and routing are relatively more complicated

Images