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System and method for generating and analyzing verilog circuit netlist compiler

A circuit netlist and compiler technology, applied in compiler construction, code compilation, parser generation, etc., can solve the problems of losing advantages, missing the market, spending a lot of time, etc., to reduce workload, reduce workload, and facilitate The effect of writing

Pending Publication Date: 2020-07-10
EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to read netlist files in different formats, corresponding analysis software needs to be written, and writing analysis software takes a lot of time. In the highly competitive chip field, delaying time means losing an advantage, and it is likely to miss the market

Method used

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  • System and method for generating and analyzing verilog circuit netlist compiler
  • System and method for generating and analyzing verilog circuit netlist compiler
  • System and method for generating and analyzing verilog circuit netlist compiler

Examples

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Embodiment Construction

[0019] like figure 2 As shown, the system for generating and analyzing verilog circuit netlist compilers includes: Lex translator, Yacc compiler, and C compiler;

[0020] a Lex translator configured to parse Lex source programs into lexical analyzer files written in C;

[0021] Yacc compiler configured to parse grammar specification files into parser files written in C;

[0022] C compiler configured to generate a parsing verilog grammar compiler from lexer files written in C and parser files written in C.

[0023] The present invention parses the Lex source program into the lexical analyzer file written in C by the Lex translator, the Yacc compiler parses the grammar description file into the lexical analyzer file written in C, and the C compiler uses the lexical analyzer written in C file and a syntax analyzer file written in C to generate and parse the verilog grammar compiler, so for circuit netlists of different formats, it is enough to write the grammar description fi...

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PUM

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Abstract

The invention discloses a system and a method for generating and analyzing a verilog circuit netlist compiler, which can greatly reduce the workload of compiling the compiler, can optimize the analysis process in a targeted manner, improves the analysis efficiency, is simple in generation process, small in workload, clear in logic structure and high in expandability, and facilitates the development of subsequent layout and wiring and the like. The system comprises a Lex translator, a Yacc compiler and a C compiler. The Lex translator is configured to analyze the Lex source program into a lexical analyzer file compiled by C; the Yacc compiler is configured to analyze the grammar description file into a syntactic analyzer file compiled by C; and the C compiler is configured to generate an analytic verilog grammar compiler from the lexical analyzer file compiled by the C and the syntactic analyzer file compiled by the C.

Description

technical field [0001] The invention relates to the technical field of programmable logic devices, in particular to a system for generating and analyzing a verilog circuit netlist compiler, and a method for generating and analyzing a verilog circuit netlist compiler, which is used for analyzing the circuit netlist in FPGA design. Background technique [0002] In the FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) design process, there is a step of synthesis. Generally, the user's circuit (verilog file) will be synthesized into a circuit netlist (netlist), and the subsequent process will be based on the circuit netlist. Perform operations such as layout and routing. Therefore, it is first necessary to read the netlist analysis into the system. For example defined as figure 1 The logic netlist of the 2-bit adder shown. [0003] It can be seen that having a system that can correctly and efficiently analyze the circuit netlist is the first condition for a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/343G06F8/30G06F8/41
CPCG06F8/37G06F8/425
Inventor 李海军涂开辉
Owner EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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