Ultra-high-speed aes processor based on fpga and its realization method

Abstract

The invention discloses a field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and an implementing method thereof. The AES processor comprises an interface storage area buffer module, a control module, an AES encryption and decryption module, a read-only memory lookup table module, a register module and an output module. The implementing method for the processor comprises the following steps: 1, initializing a data table; 2, performing initial setting; 3, receiving data; 4, reading the data; 5, selecting a data processing mode; 6, judging whether the encryption and decryption are finished; and 7, outputting a result. The invention mainly solves the problems that an AES processor is controlled complicatedly and modules have low portability, reliability, safety and processing speed in the prior art; and an improved algorithm and a lookup table-based method are used. The AES processor has all levels of structures which are fixed, is simple in control logic, comprises the modules with high portability, is suitable to be implemented in a singlechip FPGA, and has the characteristics of high speed and high accuracy.

Description

Technical field [0001] The invention belongs to the field of communication technology, and further relates to a field programmable gate array (Field Programmable Gate Array, FPGA)-based ultra-high-speed Advanced Encryption Standard (AES) processor and its implementation method in the field of information security technology. The invention fully utilizes the flexibility of FPGA programming and the reliability of hardware under the condition of ensuring high processing speed and minimum resource occupation, and realizes the safe encryption of data and information. The invention can be widely applied to advanced encryption and decryption in smart cards, mobile banking systems, and ATM cash machines to ensure the safety of data and information. Background technique [0002] With the development of communication technology, the communication environment has become increasingly complex. Compared with traditional software encryption methods, hardware encryption has the advantages of fas...

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Problems solved by technology

[0006] The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, solve the problems of traditional AES processor control logic complexity, long delay time between input and output, and occupy more resources, and propose a method with faster calculation speed and resource utilization FPGA-based ultra-high-speed AES processor with higher rate and simpler structure and its implementation method to improve its practical performance

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