Generation method and device of CKE signal

Abstract

The utility model discloses a generation method and a device of CKE signals and belongs to the field of communication. The generation method includes: obtaining frequencies of the clock signals of N Masters and frequencies of the clock signals of buses which are connected with the N Masters, the clock signals of the N Masters and the clock signals of the buses are generated based on the same source clock, N is not less than 2 and N is an integer, the nth CKE signal is produced according to the frequency of the nth clock signal of the Master and the frequency of the clock signal of the buses, n belongs to the range of 1, 2, ...N; The nth CKE signal is provided to the nth Master. The generation device of CKE signals comprises obtaining modules, generation modules and providing modules. Because every Master can individually provide a CKE signal, the generation method and the device of CKE signals has the advantages of greatly reducing the numbers of driving circuits of the CKE and being easy for operators to make placement and routing.

Description

technical field [0001] The invention relates to the communication field, in particular to a method and device for generating a clock enable signal. Background technique [0002] In ASIC (Application Specific Integrated Circuits, Application Specific Integrated Circuits), often multiple Masters (also known as Cores) (master devices) access multiple Slaves (slave devices) through the bus interconnection structure. ASICs include both synchronous and asynchronous architectural approaches. In the synchronous architecture mode, the clock signals of Master, Slave and the bus are generated from the same source clock using frequency division logic, and the clock frequencies of each clock signal are in the same frequency or multiplied relationship. [0003] Wherein, the Master samples the data of the bus at the rising edge of the clock signal of the Master, so as to realize the data and instruction interaction between the Master and the bus. The bus transmits valid data at the high ...

AI Technical Summary

Problems solved by technology

[0005] Multiple Masters are driven by the same clock enable signal, resulting in a huge number of clock enable drive circuits

Moreover, due to the small size of the ASIC, multiple Masters are driven by the same clock enable signal, which will bring great difficulties to the layout and wiring of the staff.

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