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Processor and processing method for VLIW (very low instruction word)

A technology of super-long instruction word and processing method, which is applied in the direction of machine execution device, etc., can solve the problems of increasing the complexity of instruction fetching, increasing the complexity of instruction issuing, and increasing the length of writing instruction word, so as to facilitate instruction execution and reduce output. Select logic, reduce the effect of the output

Active Publication Date: 2014-11-26
北京中科晶上科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such an architecture increases the process of writing the instruction word length register and increases the complexity of fetching instructions
[0005] Paper: Architecture Design of Variable lengths Instructions Expansion for VLIW proposes a VLIW architecture with a fixed number of parallel instructions. The number of parallel instructions each time is fixed, but the length of a single instruction is variable 16bits or 32bits. Such an architecture needs to add necessary logic to determine the number of bits of the current single instruction when the instruction is issued, which increases the complexity of instruction issuance

Method used

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  • Processor and processing method for VLIW (very low instruction word)
  • Processor and processing method for VLIW (very low instruction word)
  • Processor and processing method for VLIW (very low instruction word)

Examples

Experimental program
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Embodiment 1

[0065] One, the specific introduction of the program memory of the processor of the very long instruction word VLIW of the present embodiment:

[0066] Such as image 3 As shown, each storage address of the program memory of the processor of the very long instruction word VLIW in this embodiment can store the structure of instructions equal to the number of instruction groups, and the instructions are divided into four different groups, then the program memory The number of instructions stored in each address unit is four, that is, instruction 1, instruction 2, instruction 3, and instruction 4 are combined and placed in address 0 of the program memory, instruction 5, instruction 6, instruction 7, instruction 8 These four instructions are combined and put into address 2 of the program memory, and so on, instruction i, instruction i+1, instruction i+2, instruction i+3, and 4 instructions are combined and put into address n of the program memory .

[0067] Two, the specific int...

Embodiment 2

[0078] Such as Figure 5 and Figure 6 As shown, the device structure of the very long instruction word VLIW processor in this embodiment is basically the same as the device structure in Embodiment 1, except that an instruction jump module is added to the instruction fetching and transmitting device, wherein the instruction The jump module is used to output an instruction instruction indicating the jump position of the instruction before the instruction sequence splicing module extracts the instruction, so that the instruction stored in the instruction cache module is invalid, and the instruction sequence splicing module extracts the instruction jump according to the instruction instruction Instructions after turning the position.

[0079] The above-mentioned embodiments make corresponding changes to the maximum storage capacity of each storage unit of the program memory according to the number of groups of instructions, so that each storage unit of the program memory is allo...

Embodiment 1

[0227] The number of parallel instructions this time is 1, and the number of instructions to run in the next cycle is 2:

[0228] Such as Figure 4 As shown, the instruction fetching and emitting device fetches four instructions including instruction 1, instruction 2, instruction 3 and instruction 4 from the instruction address 0, and judges the number of instructions to be executed this time according to the flag bit. The instructions to be executed in parallel this time are 1, that is, the instruction 1 is emitted in the first clock cycle, that is, Inst0-instruction 1; Inst1-NOP; Inst2-NOP; Inst3-NOP; In this embodiment, Inst0 belongs to group A instructions, and Inst0 is input into the instruction register In 0, empty instructions are input in instruction register 1, instruction register 2, and instruction register 3. Input the unlaunched instruction 2, instruction 3 and instruction 4 into the cache module for storage.

[0229] When the instruction is transmitted in the s...

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Abstract

The invention discloses a processor and a processing method for a VLIW (very long instruction word) and mainly aims to provide a processor for a VLIW, which is simple in instruction-fetching and short in operation cycle, and a processing method for the VLIW. The processor for the VLIW includes: instruction selection modules which group and judge instructions entering different instrument processing channel hardware structures are set before instruction registers, and logic circuits before execution devices are reduced; the processing method includes: judging group information of the instructions before entering the instruction registers, storing the instructions into the corresponding instruction registers, and executing the instructions in each instruction register respectively; and accordingly operation cycle of the instructions is shortened. The parallel instructions are stored in the different instruction registers, and accordingly complexity in post instruction execution process is simplified, and frequency of the processor is increased.

Description

technical field [0001] The invention relates to a processor and a processing method of very long instruction word VLIW. Background technique [0002] VLIW: (Very Long Instruction Word, very long instruction word) a very long instruction combination, which connects many instructions together and executes them at the same time, which increases the speed of operation and improves the degree of parallelism. In the VLIW structure, there is a structure with a fixed number of parallel instructions, that is, the number of instructions executed in parallel each time is fixed; there is also a structure with a variable number of parallel instructions, that is, the number of instructions executed in parallel each time is flexible and variable . [0003] Patent: 03818755.8 introduces a VLIW architecture. The storage of instructions in this architecture is stored according to the VLIW with a constant number of instructions. Each storage unit stores the maximum number of parallel instruc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
Inventor 石晶林朱子元于亚轩
Owner 北京中科晶上科技股份有限公司
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