Optimized BCH (Bose-Chaudhuri-Hocquenghem) decoder

A BCH code and decoding technology, applied in the field of error correction control coding, can solve the problems of wasting hardware resources and ignoring the properties of BCH codes, and achieves the effect of reducing the number of iterations and solving technical difficulties.

Inactive Publication Date: 2012-07-11
殷民
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Problems solved by technology

[0005] The inventor noticed that the riBM and RiBM algorithms are general algorithms proposed for RS codes. If they are used on BCH codes without modification, many unique properties of BCH codes will be ignored, resulting in a waste of hardware resources.

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  • Optimized BCH (Bose-Chaudhuri-Hocquenghem) decoder
  • Optimized BCH (Bose-Chaudhuri-Hocquenghem) decoder
  • Optimized BCH (Bose-Chaudhuri-Hocquenghem) decoder

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Embodiment Construction

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] Many parameters are involved in the specific embodiment, and its meaning is described as follows:

[0028] (1) N: the length of the code word in the BCH code, that is, the length of the information plus the redundant parity bit. In the flash memory controller, N=K+MT.

[0029] (2) K: the length of the information in the BCH code. In the flash memory controller, the information is a shortened code, and K is usually 8192=1KB.

[0030] (3) T: The error correction capability of the BCH code.

[0031] (4) Indicates the largest integer less than or equal to T / 2.

[0032] (5) M: BCH code is based on the operation on Galois field GF(2^M), if K=8192, M=14.

[0033] (6) L: the parallelism of the BCH code, since the flash memory is operated in units of bytes, L=8.

[0034] (7)S i (i=0, 1, . . . , 2T-1): the accompaniments for reading infor...

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Abstract

The invention provides an optimized BCH (Bose-Chaudhuri-Hocquenghem) decoding method and device in a flash controller. The optimized BCH decoding method comprises the following steps of: reading flash memory information, storing the flash memory information in an FIFO (First Input First Output), and computing an adjoint functor according to the read information; solving a key equation, namely computing an error location polynomial based on an iterative algorithm according to the adjoint functor; verifying a root through Chien Search according to the error location polynomial to determine an error location; and performing anti-error correction on error information of the error location so as to obtain error correction information in a flash memory. In the step of solving the key equation, the conventional riBM algorithm by using characteristics of a binary BCH code is optimized, so that logic is almost reduced to half; and iterative delay is only 1/2 of original algorithm, so that the technical difficulty in ECC (Error Correction Code) logic complexity in a flash memory controller is overcome. According to the optimized BCH decoding method and device, due to high-level symmetry and structuralization of circuits, balancing on logic complexity and decoding delay by adopting a laminated means is facilitated on one hand, wiring layout at the rear end of a VLSI (Very Large Scale Integrated Circuit) is facilitated on the other hand. The optimized riBM algorithm can also be applied to digital television broadcasting, space communication and other application fields.

Description

[0001] Technical field: the present invention belongs to the technical field of error correction control coding, and mainly relates to the optimization of BCH decoders, which can be used in applications such as flash memory controllers, digital video broadcasting systems, and space communications. Background technique: [0002] Nand flash memory is a non-volatile memory chip that has obvious advantages in power consumption, speed, and heat dissipation, and is widely used in consumer electronics and portable storage. With the advancement of technology and the introduction of new interface standards, the storage speed of flash memory has been greatly improved. The currently released ONFI3.0 standard already supports a storage speed of 400MB / s. It is expected that solid-state drives (SSDs) based on flash memory will also replace mechanical hard drives and become the mainstream development direction of data storage. [0003] According to the number of information bits stored in ea...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
Inventor 殷民
Owner 殷民
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