Digital LDO automatic generation method and device capable of being configured in parameterized mode

Abstract

The invention discloses a method and a device for automatically generating a digital LDO (Low Dropout Regulator) capable of being configured in a parameterized manner, aiming at solving the problems that an existing digital LDO design method needs to repeatedly simulate, verify and modify a schematic diagram layout, the period is long and the cost is high, and based on a given digital LDO architecture, variable design parameters in a digital LDO circuit are subjected to configuration design. Configurable performance parameters correspond to circuit design parameters, and corresponding digital LDO netlist files and layout files can be generated only by inputting specified performance parameters. The design time of the circuit is greatly reduced, and the agile design is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of digital LDO design, and in particular relates to a parameterizable and configurable digital LDO automatic generation method and device. Background Art

[0002] Digital LDO (DLDO) has attracted much attention due to its low voltage operating capability and good process scalability. Compared with traditional analog LDO (ALDO), digital LDO requires a smaller power tube area under the same load current and has fewer stability issues. Although it has the disadvantages of steady-state ripple and low power supply rejection ratio, it is still widely used in high-efficiency power management systems for digital circuits to achieve fine-grained power supply for digital circuits.

[0003] Traditional digital LDO consists of a clock-controlled voltage comparator, a bidirectional shift register, and a PMOS switch array. The output voltage VOUT is compared with the reference voltage VREF through a clock-controlled comparator, and the comparison result is output to the bidirectional shift register, which controls the shift direction of the bidirectional shift register and outputs a digital 0 or 1; thus, one PMOS in the PMOS array is turned on or off each time to adjust the output voltage. The PMOS array consists of PMOS tubes of the same size, which are in the linear region when turned on and in the cutoff region when turned off.

[0004] At present, most LDO designs adopt customized design methods, following the mixed digital-analog design process and designing circuit schematics and layouts according to user needs. When the design requirements change, redesign and simulation verification are required.

[0005] For digital LDO circuits with similar design requirements, the traditional customized design method requires repeated simulation verification and modification of schematic layout, which is long and costly. For example, the current circuit design usually adopts the customized design method: determine the circuit specification requirements -> architecture design, select the appropriate circuit architecture -> schematic design -> simulation -> modify the schematic according to the simulation results -> layout design -> DRC / LVS -> parasitic extraction PEX -> layout post-simulation -> modify the schematic and layout according to the post-simulation results -> export gds file. Summary of the invention

[0006] The purpose of the present invention is to provide a parameter-configurable digital LDO automatic generation device, which realizes parameter-configurable digital LDO under the same architecture, and can realize automatic generation of digital LDO circuits and layouts of the same architecture according to input design parameters, thereby greatly reducing the design time of the circuit and realizing agile design.

[0007] To solve the above problems, the technical solution of the present invention is:

[0008] A parameterizable and configurable digital LDO automatic generation device, comprising:

[0009] A given digital LDO architecture, wherein the digital LDO architecture includes a control logic structure and an analog topology structure;

[0010] A template module is used to template the digital LDO architecture to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template;

[0011] The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of the given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0012] The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog unit; combine the analog unit with the netlist file of the digital control logic to generate the netlist file of the digital LDO; use the layout file of the analog unit and the layout file of the digital control logic to combine the layout according to the splicing rules to obtain the layout file of the digital LDO;

[0013] The control logic structure of the digital LDO architecture includes a counter, a sequence detector and a shift control logic. The input of the counter is connected to a clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to a clock signal, and the output is connected to the shift control logic to control the digital LDO to enter a coarse loop logic or a fine loop logic.

[0014] The template module uses Verilog code to design the counter, sequence detector and shift control logic to generate a control logic Verilog template.

[0015] According to one embodiment of the present invention, the digital control logic automatic generation module performs parameter configuration on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and passes the configured parameters to the control logic Verilog template to obtain the Verilog code of the digital control logic.

[0016] According to an embodiment of the present invention, the digital control logic automatic generation module calls the digital synthesis script template in the templated module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines the digital LDO netlist file template to generate a digital control logic netlist file;

[0017] Call the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0018] According to an embodiment of the present invention, the analog topology structure of the digital LDO architecture includes a clock control comparator, two sets of PMOS switch arrays, a load capacitor and a feedback resistor;

[0019] The negative phase terminal of the clock control comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to the control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to the coarse adjustment loop and the fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded;

[0020] The digital LDO automatic generation module performs parameter configuration on the number of two groups of PMOS switch arrays, the size of load capacitance, the number of feedback resistors and the voltage division ratio based on the analog topology to obtain a corresponding analog unit.

[0021] According to an embodiment of the present invention, the number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO;

[0022] The size of the load capacitance is determined by the clock frequency;

[0023] The number of feedback voltage-dividing resistors and the voltage-dividing ratio are determined by the input voltage, output voltage and reference voltage of the digital LDO.

[0024] According to an embodiment of the present invention, the digital LDO automatic generation module combines the layout file of the analog unit with the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

[0025] A parameterizable and configurable digital LDO automatic generation method, comprising:

[0026] Acquire a given digital LDO architecture, wherein the digital LDO architecture includes a control logic structure and an analog topology structure;

[0027] The digital LDO architecture is templated to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template;

[0028] Based on the given control logic structure of the digital LDO architecture, configure the control logic parameters of the control logic structure, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0029] Based on the given analog topology of the digital LDO architecture, configure the analog parameters in the digital LDO architecture to obtain the corresponding analog unit; combine the analog unit with the netlist file of the digital control logic to generate the netlist file of the digital LDO;

[0030] The layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

[0031] According to an embodiment of the present invention, the automatic generation of a netlist file and a layout file of a digital control logic further comprises:

[0032] Parameter configuration is performed on the control signal bit width of the control logic in the basic architecture of the digital LDO, and the configured parameters are passed to the control logic code template to obtain the control logic code; wherein the configured parameters include the number of bits of the PMOS array;

[0033] Apply the control logic code to the digital synthesis script template to automatically generate a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file;

[0034] Apply the digital control logic gate netlist to the digital backend automatic placement and routing script template to automatically generate the digital control logic layout file.

[0035] According to an embodiment of the present invention, the control logic structure of the digital LDO architecture includes a counter, a sequence detector and a shift control logic, wherein the input of the counter is connected to a clock signal, and the output is connected to the shift control logic; the input of the sequence detector is connected to a clock signal, and the output is connected to the shift control logic, so as to control the digital LDO to enter a coarse loop logic or a fine loop logic;

[0036] The counter, sequence detector and shift control logic are designed using Verilog code to generate a control logic Verilog template;

[0037] Parameter configuration is performed on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and the configured parameters are passed to the control logic Verilog template to obtain the Verilog code of the digital control logic;

[0038] Call the digital synthesis script template to convert the digital logic Verilog code into a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file;

[0039] Call the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0040] According to an embodiment of the present invention, the analog topology structure of the digital LDO architecture includes a clock control comparator, two groups of PMOS switch arrays, a load capacitor and a feedback resistor; the negative phase terminal of the clock control comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to a control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to a coarse adjustment loop and a fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded;

[0041] Based on the analog topology, the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio are parameterized to obtain a corresponding analog unit;

[0042] The number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO; the size of the load capacitor is determined by the clock frequency; the number and voltage division ratio of the feedback voltage divider resistors are determined by the input voltage, output voltage and reference voltage of the digital LDO.

[0043] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0044] The parameterizable digital LDO automatic generation method in one embodiment of the present invention aims at the problem that the existing digital LDO design method needs to repeatedly simulate and verify and modify the schematic layout, which has a long cycle and high cost. Based on a given digital LDO architecture, the changeable design parameters in the digital LDO circuit are configured, and the configurable performance parameters are matched with the circuit design parameters. Only the specified performance parameters need to be input to generate the corresponding digital LDO netlist file and layout file. The circuit design time is greatly reduced, and agile design is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A block diagram of a parameterizable digital LDO automatic generation device in one embodiment of the present invention;

[0046] Figure 2 A basic architecture diagram of a digital LDO in one embodiment of the present invention;

[0047] Figure 3 A flow chart for generating a digital LDO circuit file in one embodiment of the present invention;

[0048] Figure 4 The figure is a flow chart of a method for automatically generating a parameterizable digital LDO in one embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following is a further detailed description of a parameterizable digital LDO automatic generation method and device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0050] This embodiment provides a parameterizable digital LDO automatic generation device. Figure 1 ,include:

[0051] A digital LDO architecture is given, the digital LDO architecture including a control logic structure and an analog topology structure;

[0052] A template module is used to template the digital LDO architecture to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template;

[0053] The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of the given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0054] The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog unit; combine the analog unit with the netlist file of the digital control logic to generate the netlist file of the digital LDO; use the layout file of the analog unit and the layout file of the digital control logic to perform layout combination according to the splicing rules to obtain the layout file of the digital LDO.

[0055] Through the above-mentioned digital LDO automatic generation device, the corresponding digital LDO netlist file and layout file can be generated by simply inputting the specified performance parameters, which can greatly reduce the design time of the circuit and realize agile design.

[0056] For a specific digital LDO architecture, see Figure 2, the digital LDO architecture includes: a clock-controlled comparator, a counter, a sequence detector, a shift control logic (coarse loop logic and fine loop logic), two groups of PMOS switch arrays, two groups of feedforward auxiliary PMOS (both 2 in number), an undershoot detection circuit, and a load capacitor and a feedback resistor. Among them, the control logic structure of the given digital LDO architecture includes a counter, a sequence detector and a shift control logic, the input of the counter is connected to the clock signal, and the output is connected to the shift control logic; the input of the sequence detector is connected to the clock signal, and the output is connected to the shift control logic, which controls the digital LDO to enter the coarse loop logic or the fine loop logic.

[0057] The templated module uses Verilog code to design the counter, sequence detector and shift control logic and generates the control logic Verilog template.

[0058] Please see Figure 3 ,The digital control logic automatic generation module configures the parameters of the control signal bit width of the shift ,control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and passes the configured parameters to the ,control logic Verilog template to obtain the Verilog code of the digital control logic.

[0059] The digital control logic automatic generation module calls the digital synthesis script template in the templated module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines the digital LDO netlist file template to generate a digital control logic netlist file; calls the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0060] The analog topology structure of the digital LDO architecture includes a clock control comparator, two groups of PMOS switch arrays, a load capacitor and a feedback resistor; the negative phase terminal of the clock control comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through a feedback resistor, and the output terminal is connected to a control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to a coarse adjustment loop and a fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded.

[0061] The digital LDO automatic generation module is based on the analog topology structure, and configures the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio to obtain the corresponding analog unit. The number of two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO; the size of the load capacitor is determined by the clock frequency; the number of feedback voltage division resistors and the voltage division ratio are determined by the input voltage, output voltage and reference voltage of the digital LDO.

[0062] The analog topology of the above digital LDO architecture can also include two groups of feedforward auxiliary PMOS and undershoot detection circuits, wherein the gates of the two groups of feedforward auxiliary PMOS are connected to the output of the clock control comparator, the source is connected to the input voltage, and the drain is connected to the output voltage. The input of the undershoot detection circuit is connected to the output voltage of the digital LDO, and its output is connected to the shift control logic. The analog units and analog layouts of the two groups of feedforward auxiliary PMOS and undershoot detection circuits are input into the digital LDO automatic generation module, and the netlist files of the analog units and digital control logic are combined to generate the netlist file of the digital LDO; the layout files of the analog units and the layout files of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

[0063] The digital LDO automatic generation module combines the layout file of the analog unit with the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

[0064] Based on the same concept, this embodiment provides a parameterizable digital LDO automatic generation method, see Figure 4 , the method comprises the following steps:

[0065] S1: Obtain a given digital LDO architecture, where the digital LDO architecture includes a control logic structure and an analog topology structure;

[0066] S2: Template the digital LDO architecture to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template;

[0067] S3: Based on the control logic structure of the given digital LDO architecture, configure the control logic parameters of the control logic structure, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0068] S4: Based on the given analog topology of the digital LDO architecture, configure analog parameters in the digital LDO architecture to obtain corresponding analog units; combine the analog units with the netlist file of the digital control logic to generate a netlist file of the digital LDO;

[0069] S5: combining the layout file of the analog unit and the layout file of the digital control logic according to a splicing rule to obtain a layout file of the digital LDO.

[0070] Through the above-mentioned digital LDO automatic generation method, the corresponding digital LDO netlist file and layout file can be generated by simply inputting the specified performance parameters, which can greatly reduce the design time of the circuit and realize agile design.

[0071] In step S2, the control logic code template is a template including the digital control logic of the digital LDO, such as the control of the coarse and fine adjustment logic in the digital LDO. Most of the content of the template can be reused, and only minor changes need to be made to the external variables passed in to obtain the control logic code for a specific circuit. Similarly, most of the content of the digital LDO netlist file template can be reused, and only minor changes need to be made to the external variables passed in to obtain the netlist file for a specific circuit. The digital synthesis script template contains the synthesis script code, and can be automatically modified according to the variables passed in from the outside to complete the conversion from the digital logic code to the gate-level netlist. The digital back-end layout and routing script template contains the layout and routing code, which is also automatically modified according to the external variables to complete the process from the gate-level netlist to the layout.

[0072] The above template can be used to adapt digital LDO circuits with different specifications, which is the basis for realizing agile design of digital LDO.

[0073] In step S3, this part focuses on the automatic generation of relevant files of digital control logic circuit. For details, please refer to Figure 2 , configure the control signal bit width of the control logic in the basic architecture of digital LDO, such as the number of bits of the PMOS array. In the coarse adjustment and fine adjustment control logic, the bit width of the control signal is determined by the number of bits of the PMOS array. Pass the configured parameters to the control logic code template to obtain the control logic code. Apply the control logic code to the digital synthesis script template to complete the conversion from digital logic code to gate-level netlist, and automatically generate the digital control logic gate netlist. On the one hand, the digital control logic gate netlist is combined with the digital LDO netlist file template to generate a digital control logic netlist file. On the other hand, the digital control logic gate netlist is applied to the digital back-end automatic layout and routing script template to complete the conversion from gate-level netlist to layout, and automatically generate the digital control logic layout file.

[0074] In step S4, the analog parameters in the digital LDO architecture are configured to obtain the corresponding analog units; the analog units are combined with the netlist file of the digital control logic to generate the netlist file of the digital LDO. In a digital LDO architecture, in addition to the devices related to the control logic, there are also some analog units, such as clock control comparators, PMOS switch arrays, etc. When designing a circuit for a given digital LDO architecture, it is necessary to configure the parameters of these analog units. The analog units after parameter configuration can be used for circuit design to obtain the layout of the analog units. Among them, the analog units are used to combine with the netlist file of the digital control logic to generate the netlist file of the digital LDO.

[0075] In step S5, the layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO. The layout file of the analog unit obtained in step S4 and the layout file of the digital control logic obtained in step S3 are combined according to the splicing rules of pin alignment to obtain the layout file of the digital LDO.

[0076] In this way, after obtaining the netlist file and layout file of the digital LDO, the circuit design of the given digital LDO architecture is completed. Through the above method, a parameter-configurable digital LDO is realized under the same architecture, and the digital LDO circuit and layout of the same architecture can be automatically generated according to the input design parameters, which greatly reduces the circuit design time and realizes agile design.

[0077] The following is an application example to introduce the parameterizable configurable digital LDO automatic generation method in this embodiment.

[0078] Please see Figure 2 , the figure shows a digital LDO architecture, which includes: a clock-controlled comparator, a counter, a sequence detector, a shift control logic (coarse loop logic and fine loop logic), two sets of PMOS switch arrays, two sets of feedforward auxiliary PMOS (both 2 in number), an undershoot detection circuit, and load capacitors and feedback resistors; wherein the counter, sequence detector and shift control logic are designed using digital Verilog code.

[0079] The configurable performance parameters of the digital LDO architecture circuit are: input voltage VIN and output voltage VOUT, maximum load current, input clock frequency, and reference voltage.

[0080] The configurable circuit design parameters of the digital LDO architecture circuit are mainly: the number N and M of the two groups of PMOS switch arrays, which corresponds to the control signal bit width output by the shift control logic; the voltage division ratio of the load capacitance and the feedback resistor.

[0081] The automatic generation of the digital control logic of the digital LDO architecture includes the following steps:

[0082] 1. Automatic generation of Verilog: The counter, sequence detector and shift control logic in the digital LDO of this architecture are designed using Verilog code. The control signal width of the shift control logic, the counting threshold of the counter and the sequence that the sequence detector can detect are configurable parameters. The bit width of the control signal is determined by the number N and M of the PMOS array. The Verilog of the shift control logic can be obtained by passing the two parameters to the Verilog template. Then the number of counts of the counter and the sequence detected by the sequence detector can be determined. According to the input parameters, the Verilog code of the digital control logic can be automatically generated using the template.

[0083] 2. Automatic generation of digital control logic circuits and layouts: Using the digital backend process, you can directly generate the cdl and gds files of the digital control logic, pass the parameters N and M to the digital synthesis script template and the digital backend automatic layout and routing script template, and then use the corresponding tools to complete the self-generation.

[0084] The automatic generation of this digital LDO includes the following steps:

[0085] 1. The parameters of the analog part are configurable: The parameters of the analog part (including the clock control comparator, two groups of PMOS switch arrays, two groups of feedforward auxiliary PMOS (the number is 2 each), the undershoot detection circuit, and the load capacitor and feedback resistor) can be changed, including the number N and M of the coarse and fine ring PMOS arrays, the size of the PMOS array, the size of the load capacitor, the number of feedback divider resistors and the divider ratio.

[0086] 2. Automatic generation of digital LDO netlist file: After determining the parameters of the analog part, use the corresponding analog unit to combine with the cdl of the digital control logic to generate the netlist file of the complete digital LDO.

[0087] 3. Automatic generation of digital LDO layout files: Use the corresponding analog unit layout files and the automatically generated digital layout files to combine the layouts according to the splicing rules.

[0088] Among them, the relationship between the configurable parameters of the digital LDO is as follows:

[0089] 1. The number of coarse and fine ring PMOS arrays N and M. The size of the PMOS array is determined by the input performance parameters VIN, VOUT and the maximum load current;

[0090] 2. The size of the load capacitance is determined by the input clock frequency;

[0091] 3. The number of feedback voltage divider resistors and the voltage divider ratio are determined by the input VIN, VOUT and reference voltage.

[0092] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A parameterizable digital LDO automatic generation device, characterized in that: include: A given digital LDO architecture, wherein the digital LDO architecture includes a control logic structure and an analog topology structure; A template module is used to template the digital LDO architecture to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template; The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of the given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic; The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog unit; combine the analog unit with the netlist file of the digital control logic to generate the netlist file of the digital LDO; use the layout file of the analog unit and the layout file of the digital control logic to combine the layout according to the splicing rules to obtain the layout file of the digital LDO; The control logic structure of the digital LDO architecture includes a counter, a sequence detector and a shift control logic. The input of the counter is connected to a clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to a clock signal, and the output is connected to the shift control logic to control the digital LDO to enter a coarse loop logic or a fine loop logic. The template module uses Verilog code to design the counter, sequence detector and shift control logic to generate a control logic Verilog template.

2. The parameterizable digital LDO automatic generation device according to claim 1, characterized in that: The digital control logic automatic generation module performs parameter configuration on the control signal bit width of the shift control logic, the counting threshold of the counter and the sequence detectable by the sequence detector, and transfers the configured parameters to the control logic Verilog template to obtain the Verilog code of the digital control logic.

3. The parameterizable digital LDO automatic generation device according to claim 2, characterized in that: The digital control logic automatic generation module calls the digital synthesis script template in the templated module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines the digital LDO netlist file template to generate a digital control logic netlist file; Call the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

4. The parameterizable digital LDO automatic generation device according to claim 1, characterized in that: The analog topology of the digital LDO architecture includes a clock control comparator, two sets of PMOS switch arrays, load capacitors and feedback resistors; The negative phase terminal of the clock control comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to the control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to the coarse adjustment loop and the fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded; The digital LDO automatic generation module performs parameter configuration on the number of two groups of PMOS switch arrays, the size of load capacitance, the number of feedback resistors and the voltage division ratio based on the analog topology to obtain a corresponding analog unit.

5. The parameterizable digital LDO automatic generation device according to claim 4, characterized in that: The number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO; The size of the load capacitance is determined by the clock frequency; The number of feedback voltage-dividing resistors and the voltage-dividing ratio are determined by the input voltage, output voltage and reference voltage of the digital LDO.

6. The parameterizable digital LDO automatic generation method according to claim 1, characterized in that: The digital LDO automatic generation module combines the layout file of the analog unit with the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

7. A parameterizable digital LDO automatic generation method, characterized in that: include: Acquire a given digital LDO architecture, wherein the digital LDO architecture includes a control logic structure and an analog topology structure; The digital LDO architecture is templated to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template; Based on the given control logic structure of the digital LDO architecture, configure the control logic parameters of the control logic structure, and pass the parameters to the control logic code template, digital synthesis script template and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic; Based on the given analog topology of the digital LDO architecture, configure the analog parameters in the digital LDO architecture to obtain the corresponding analog unit; combine the analog unit with the netlist file of the digital control logic to generate the netlist file of the digital LDO; The layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

8. The parameterizable digital LDO automatic generation method according to claim 7, characterized in that: The automatic generation of the netlist file and layout file of the digital control logic further includes: Parameter configuration is performed on the control signal bit width of the control logic in the basic architecture of the digital LDO, and the configured parameters are passed to the control logic code template to obtain the control logic code; wherein the configured parameters include the number of bits of the PMOS array; Apply the control logic code to the digital synthesis script template to automatically generate a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file; Apply the digital control logic gate netlist to the digital backend automatic placement and routing script template to automatically generate the digital control logic layout file.

9. The parameterizable digital LDO automatic generation method according to claim 7, characterized in that: The control logic structure of the digital LDO architecture includes a counter, a sequence detector and a shift control logic. The input of the counter is connected to a clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to a clock signal, and the output is connected to the shift control logic to control the digital LDO to enter a coarse loop logic or a fine loop logic. The counter, sequence detector and shift control logic are designed using Verilog code to generate a control logic Verilog template; Parameter configuration is performed on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and the configured parameters are passed to the control logic Verilog template to obtain the Verilog code of the digital control logic; Call the digital synthesis script template to convert the digital logic Verilog code into a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file; Call the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

10. The parameterizable digital LDO automatic generation method according to claim 7, characterized in that: The analog topology structure of the digital LDO architecture includes a clock control comparator, two groups of PMOS switch arrays, a load capacitor and a feedback resistor; the negative phase terminal of the clock control comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to a control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to a coarse adjustment loop and a fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded; Based on the analog topology, the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio are parameterized to obtain a corresponding analog unit; The number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO; the size of the load capacitor is determined by the clock frequency; the number and voltage division ratio of the feedback voltage divider resistors are determined by the input voltage, output voltage and reference voltage of the digital LDO.

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