Chip, arrangement method of driving clock unit circuit on chip, and electronic device

Abstract

The invention provides a chip, an arrangement method of a driving clock unit circuit on the chip, electronic equipment and the chip, and the chip comprises the driving clock unit circuit which is arranged on a first area of the chip. Wherein the driving clock unit circuit includes: an input port and an output port disposed at both ends of a first region; an active transistor disposed in a driving force core region located in an intermediate region of the first region; wherein the number and the arrangement mode of the effective transistors are determined according to the driving capability of the driving clock unit circuit; and the decoupling capacitor is used for filling a redundant region, in which the effective transistor does not exist, in the driving force core region.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a chip, a method for arranging a driving clock unit circuit on a chip, and an electronic device. Background Art

[0002] As chips scale, the chip clock structure becomes increasingly important to the timing closure of the entire chip. The H-clock tree effectively controls the impact of cross-corner interference, structurally ensuring that clock skew within each corner is controlled within a reasonable range. High-drive clock units are used to reduce top-level clock delay, helping to mitigate the impact of on-chip variations (OCVs), thereby ensuring rapid timing convergence for the entire chip. Currently, the performance and drive capability of high-drive clock units are relatively low, which in turn limits the timing closure of the entire chip. Summary of the Invention

[0003] Embodiments of the present application provide a chip, a method for arranging a driving clock unit circuit on a chip, and an electronic device.

[0004] In a first aspect, an embodiment of the present application provides a chip, comprising a driving clock unit circuit, which is arranged on a first area of ​​the chip, wherein the driving clock unit circuit comprises: an input port and an output port arranged at both ends of the first area; an effective transistor, which is arranged in a driving force core area located in the middle area of ​​the first area; wherein the number and arrangement of the effective transistors are determined according to the driving capability of the driving clock unit circuit; and a decoupling capacitor, which fills an excess area in the driving force core area where the effective transistor does not exist.

[0005] In a second aspect, an embodiment of the present application provides a method for arranging a driving clock unit circuit on a chip, comprising: determining the driving capability of the driving clock unit circuit; determining an initial arrangement of the driving clock unit circuit on the chip based on the driving capability; wherein, in the initial arrangement, the size of the driving clock unit circuit, and the position, size, shape, port metal layer of the input and output ports, and the number and arrangement of effective transistors are all determined; filling different fillers in redundant areas where there are no effective transistors in the driving force core area where the effective transistors in the initial arrangement are located to obtain different intermediate arrangements; and taking the intermediate arrangement with the largest driving capability as the target arrangement of the driving clock unit circuit on the chip.

[0006] In a third aspect, an embodiment of the present application provides an electronic device, comprising: any one of the above-mentioned chips.

[0007] The chip provided in the embodiment of the present application is filled with decoupling capacitors in the redundant areas where the effective transistors do not exist in the driving force core area and in the adjacent areas of the effective transistors, thereby improving the performance of the driving clock unit circuit, reducing the power consumption of the driving clock unit circuit, and enhancing the driving capability of the driving clock unit circuit.

[0008] The method for arranging the driving clock unit circuit on a chip provided in an embodiment of the present application optimizes the driving clock unit circuit in which a decoupling capacitor is filled in an adjacent area of ​​the effective transistor in a redundant area where the effective transistor does not exist in the driving force core area, thereby improving the performance of the driving clock unit circuit, reducing the power consumption of the driving clock unit circuit, and enhancing the driving capability of the driving clock unit circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A flowchart of a method for arranging a driving clock unit circuit on a chip according to one embodiment of the present application;

[0010] Figure 2 A schematic diagram of an intermediate arrangement in an embodiment of the present application;

[0011] Figure 3 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0012] Figure 4 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0013] Figure 5 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0014] Figure 6 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0015] Figure 7 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0016] Figure 8 is a schematic diagram of another intermediate arrangement in an embodiment of the present application;

[0017] Figure 9 This is a schematic diagram of another intermediate arrangement in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solution of the present application, the driving clock unit and its optimization method, electronic device, and computer-readable medium provided by the present application are described in detail below with reference to the accompanying drawings.

[0019] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the scope of this application to those skilled in the art.

[0020] In the absence of conflict, the various embodiments of the present application and the various features therein may be combined with each other.

[0021] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0022] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof is not excluded.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0024] Figure 1 A flowchart of a method for arranging a driving clock unit circuit on a chip provided in one embodiment of the present application.

[0025] First, refer to Figure 1 One embodiment of the present application provides a method for arranging a driving clock unit circuit on a chip, comprising:

[0026] Step 100: Determine the driving capability of the driving clock unit circuit.

[0027] In some exemplary embodiments, the driving timing unit circuit may be a driving clock unit circuit in a kit form.

[0028] In some exemplary embodiments, the sizes of the different driving clock unit circuits in the kit, as well as the positions, sizes, shapes, and port metal layers of their input and output ports, are all identical. Therefore, a target placement on the chip for the driving clock unit circuit with the greatest drive capability can be determined first. Then, based on this target placement on the chip for driving clock unit circuits with other drive capabilities, the target placement on the chip for driving clock unit circuits with other drive capabilities can be determined.

[0029] Step 101, determining the initial layout of the driving clock unit circuit on the chip based on the driving capability; wherein, in the initial layout, the size of the driving clock unit circuit, as well as the position, size, shape, port metal layer of the input and output ports, and the number and arrangement of effective transistors are all determined.

[0030] Step 102 : Filling different fillers in redundant areas where no active transistors exist in the driving force core area where the active transistors are located in the initial arrangement to obtain different intermediate arrangements.

[0031] In some exemplary embodiments, the active transistor may be an active metal oxide semiconductor (MOS) transistor.

[0032] In some exemplary embodiments, filling different fillers in redundant areas where no effective transistors exist in the driving force core area where the effective transistors in the initial arrangement are located to obtain different intermediate arrangements includes: filling at least one of the following fillers in redundant areas where no effective transistors exist in the driving force core area where the effective transistors in the initial arrangement are located to obtain different intermediate arrangements: a filler cell, a dummy cell, and a decoupling capacitor (decap).

[0033] In the above and following descriptions of the present disclosure, the "first area" is the area occupied by the driving clock unit circuit on the chip, the "driving force core area" is the middle part of the first area, in which effective transistors are arranged, and the "redundant area" is the area in the driving force core area where no effective transistors are arranged.

[0034] In some exemplary embodiments, a filler may be filled in a region adjacent to an effective transistor in the redundant region.

[0035] In some exemplary embodiments, a region adjacent to the active transistor in the redundant region may be filled with at least one of the following fillers: a filler cell, a dummy cell, and a decap.

[0036] In some exemplary embodiments, the redundant region may be filled with a filler in adjacent regions and non-adjacent regions of the active transistor.

[0037] In some exemplary embodiments, the adjacent region refers to a region adjacent to an active transistor.

[0038] In some exemplary embodiments, the non-adjacent region refers to a region that is not adjacent to an active transistor.

[0039] In some exemplary embodiments, the redundant region may be filled with at least one of the following fillers: a filler cell, a dummy cell, and a decap.

[0040] In some exemplary embodiments, at least one of the type and arrangement of the fillers filled in the redundant areas in different intermediate arrangements is different. Figure 2 As shown, the adjacent area is filled with filler cells and decap. Figure 3 As shown, the adjacent area is filled with dummy cells and decap. Figure 4 As shown, the adjacent area is filled with filler cell, dummy cell, and decap. Figure 5 As shown, the adjacent area is filled with decap. Figure 6 As shown, filler cells and decap are filled in adjacent areas and non-adjacent areas. Figure 7 As shown, dummy cells and decaps are filled in adjacent and non-adjacent areas. Figure 8 As shown, filler cells, dummy cells, and decap cells are filled in adjacent and non-adjacent areas. Figure 9 As shown, the adjacent areas and the non-adjacent areas are filled with decap.

[0041] Step 103 : Using the middle arrangement with the largest driving capability as the target arrangement of the driving clock unit circuit on the chip.

[0042] In some exemplary embodiments, a decoupling capacitor is filled in a redundant region in a middle arrangement having the largest driving capability and located in a region adjacent to an active transistor.

[0043] In some exemplary embodiments, a redundant region in the middle arrangement having the largest driving capability is filled with a decoupling capacitor in an adjacent region and a non-adjacent region of an active transistor.

[0044] The method for arranging the driving clock unit circuit on a chip provided in an embodiment of the present application optimizes the driving clock unit circuit in which a decoupling capacitor is filled in an adjacent area of ​​the effective transistor in a redundant area where the effective transistor does not exist in the driving force core area, thereby improving the performance of the driving clock unit circuit, reducing the power consumption of the driving clock unit circuit, and enhancing the driving capability of the driving clock unit circuit.

[0045] Secondly, refer to Figure 5 and Figure 9 Another embodiment of the present application provides a chip, including: a driving clock unit circuit, which is arranged on a first area of ​​the chip.

[0046] The driving clock unit circuit includes: an input port and an output port arranged at both ends of the first area; an effective transistor, which is arranged in a driving force core area located in the middle area of ​​the first area; wherein the number and arrangement of the effective transistors are determined according to the driving capability of the driving clock unit circuit; and a decoupling capacitor, which fills the redundant area in the driving force core area where no effective transistors exist.

[0047] In some exemplary embodiments, Figure 5 As shown, the decoupling capacitor is filled in a redundant region where no active transistor exists in the driving force core region and is located in a region adjacent to the active transistor.

[0048] In some exemplary embodiments, Figure 9 As shown, the decoupling capacitor is filled in the redundant area where no active transistor exists in the driving force core area and is located in the adjacent area and non-adjacent area of ​​the active transistor.

[0049] The driving clock unit provided in the embodiment of the present application is filled with decoupling capacitors in the redundant area where there are no effective transistors in the driving force core area and in the adjacent area of ​​the effective transistor, thereby improving the performance of the driving clock unit circuit, reducing the power consumption of the driving clock unit circuit, and enhancing the driving capability of the driving clock unit circuit.

[0050] In a third aspect, another embodiment of the present application provides an electronic device, comprising: any one of the above-mentioned chips.

[0051] In some exemplary embodiments, the electronic device further includes: one or more I / O interfaces 1003 connected between the processor 1001 and the memory 1002 , and configured to implement information interaction between the processor 1001 and the memory 1002 .

[0052] Among them, the processor 1001 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 1002 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 1003 is connected between the processor 1001 and the memory 1002, and can realize information interaction between the processor 1001 and the memory 1002, including but not limited to a data bus (Bus), etc.

[0053] In some embodiments, the processor 1001 , the memory 1002 , and the I / O interface 1003 are connected to each other via a bus 1004 , and further connected to other components of the computing device.

[0054] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0055] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A chip, comprising a driving clock unit circuit, wherein the driving clock unit circuit is arranged on a first area of ​​the chip, wherein the driving clock unit circuit comprises: An input port and an output port disposed at both ends of the first region; An effective transistor, wherein the effective transistor is arranged in a driving force core region located in a middle region of the first region; wherein the number and arrangement of the effective transistors are determined according to the driving capability of the driving clock unit circuit; A decoupling capacitor is used to fill a redundant area in the driving force core area where the effective transistor does not exist.

2. The chip according to claim 1, wherein: The decoupling capacitor is filled in a redundant area in the driving force core area where the effective transistor does not exist and is located in an adjacent area of ​​the effective transistor.

3. The chip according to claim 1, wherein: The decoupling circuit is filled in a redundant region in which the effective transistor does not exist in the driving force core region and in a region adjacent to and non-adjacent to the effective transistor.

4. A method for arranging a driving clock unit circuit on a chip, comprising: Determine the driving capability of the driving clock unit circuit; Determine the initial layout of the driving clock unit circuit on the chip based on the driving capability; wherein, in the initial layout, the size of the driving clock unit circuit, the position, size, shape, port metal layer of the input and output ports, and the number and arrangement of effective transistors are all determined; Filling different fillers in a redundant area where the effective transistor in the driving force core area where the effective transistor in the initial arrangement is located and where the effective transistor does not exist, so as to obtain a different intermediate arrangement; The middle arrangement with the largest driving capability is taken as the target arrangement of the driving clock unit circuit on the chip.

5. The method for arranging a driving clock unit circuit on a chip according to claim 4, wherein: A decoupling capacitor is filled in a redundant region in the middle arrangement having the largest driving capability and located in a region adjacent to the effective transistor.

6. The method for arranging a driving clock unit circuit on a chip according to claim 4, wherein: The redundant area in the middle arrangement with the largest driving capability is filled with decoupling capacitors in the adjacent area and the non-adjacent area of ​​the effective transistor.

7. The method for arranging a driving clock unit circuit on a chip according to claim 4, wherein: The step of filling a redundant region where the effective transistor is located in the driving force core region where the effective transistor is located in the initial arrangement with different fillers to obtain a different intermediate arrangement comprises: At least one of the following fillers is filled in a redundant area where the effective transistor in the driving force core area is located and where the effective transistor does not exist, so as to obtain a different intermediate arrangement: Filled cells, empty cells, decoupling capacitors.

8. An electronic device comprising the chip according to any one of claims 1 to 3.

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