Integrated circuit hybrid unit layout method and device, equipment and medium
By modeling the problem of the to-layout area of the integrated circuit into a weighted maximum satisfactory problem and adopting a window-based adjustment method, the multi-unit spacing constraint problem is solved, and efficient and compliant integrated circuit layout is achieved, and design compliance is improved. and reliability reduce costs.
Patent Information
- Application Number
- CN202411337720.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-07
AI Technical Summary
The existing integrated circuit hybrid unit layout method has limitations when dealing with multi-cell spacing constraints, ignoring the complex multi-cell spacing problem, resulting in the design being unable to meet the requirements of high performance and high reliability, and traditional methods can only solve it in the legalization stage. The two-unit edge spacing constraint cannot be fully considered, which increases the risk of violations.
Model the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfactory problem, and adjust it through a window-based method after the legalization stage to reduce multi-unit spacing violations, ensure that all spacing constraints are met, and achieve efficient and compliant layout.
By converting multi-unit spacing constraints into weighted maximum satisfactory issues and adopting a window-based iterative method, the compliance of the design is significantly improved, the risk of violations is reduced, the quality and reliability of the layout is improved, and the design cycle is shortened. Reduced costs.
Smart Images
Figure CN119272714A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of very large scale integrated circuit physical design automation technology, and in particular to an integrated circuit hybrid unit layout method and device, equipment, and medium. Background Art
[0002] Due to the aggressive device scaling and manufacturing constraints in advanced technology nodes of integrated circuit processes, integrated circuit physical design automation needs to consider more complex design rule constraints, especially cell spacing constraints, which require that the minimum spacing requirements must be met between any two cell edge types to avoid three-cell spacing violations caused by insufficient spacing. Therefore, mixed cell height layout with multiple cell spacing constraints is crucial in integrated circuit design, which directly affects the feasibility, performance, and quality and reliability of the design and the final product.
[0003] At present, among the existing solutions, some take the cell edge spacing constraints into consideration and only solve the two-cell edge spacing constraints in the legalization stage, ignoring the multi-cell spacing constraint problem, such as references [1-2]; some others, due to the complexity of the multi-cell spacing constraints, convert the multi-cell spacing constraints into key two-cell spacing constraints in order to handle the problem in the detailed layout stage. Although this can simplify the problem complexity and improve the solution speed, it compromises the quality of the solution and increases the risk of violation, such as reference [3].
[0004] Based on this, a new integrated circuit hybrid cell layout method is needed.
[0005] References:
[0006] [1]H.Li,W.Chow,G.Chen,B.Yu,and EFYYoung.Pin-accessiblelegalization for mixed-cell-height circuits.IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems,41(1):143-154,2022.
[0007] [2] Z. Zhu, J. Chen, W. Zhu, and Y. Chang. Mixed-cell-height legalization considering technology and region constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(12):5128-5141, 2020.
[0008] [3] Y.-H.Cheng, D.-W.Huang, W.-K.Mak, and T.-C.Wang.A practical detailedplacement algorithm under multi-cell spacing constraints.In 2018IEEE / ACMInternational Conference on Computer-Aided Design(ICCAD),page1-8,2018. Summary of the invention
[0009] In view of this, the embodiments of the present specification provide an integrated circuit mixed cell layout method and apparatus, equipment, and medium, which reduce multi-cell spacing violations based on satisfiability problems after the legalization stage, and eliminate all remaining violations through windows, which can effectively solve multi-cell spacing violation problems at a relatively small displacement cost, ensure that all spacing constraints are met, and thus achieve efficient and compliant integrated circuit layout.
[0010] The embodiments of this specification provide the following technical solutions:
[0011] The embodiment of the present specification provides a method for layout of a hybrid cell of an integrated circuit, including:
[0012] Based on the multi-cell spacing constraint condition, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area;
[0013] For the remaining violations that are not resolved during the solving process, a window-based approach is used for adjustment.
[0014] The embodiment of this specification also provides an integrated circuit hybrid cell layout device, including:
[0015] Problem modeling and solving module: based on multi-cell spacing constraints, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area;
[0016] Adjustment Module: For the remaining violations that are not resolved during the solving process, a window-based approach is used for adjustment.
[0017] The embodiment of the present specification also provides an electronic device, including:
[0018] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so as to enable the at least one processor to execute: any one of the integrated circuit hybrid cell layout methods described above.
[0019] The embodiments of the present specification also provide a computer storage medium, wherein the computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the integrated circuit hybrid unit layout method described in any one of the above is performed.
[0020] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:
[0021] This application solves the multi-cell spacing violation problem at the minimum displacement cost by converting the multi-cell spacing constraint problem into a weighted maximum satisfiability problem and adopting a window-based iterative method to handle the remaining violations, thereby ensuring that the design meets the minimum spacing requirements while reducing the risk of violations and improving the compliance of the layout. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 (a) is a hybrid cell height layout diagram considering multi-cell spacing constraints in this application;
[0024] Figure 1 (b) is a diagram of a multi-unit spacing violation pattern in this application;
[0025] Figure 2 It is a flow chart of the integrated circuit hybrid cell layout method in this application. DETAILED DESCRIPTION
[0026] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0027] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0028] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0029] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0030] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.
[0031] With the continuous advancement of integrated circuit technology, device size continues to shrink, especially in very large scale integrated circuit (VLSI) design, design rules become increasingly complex, for example, the cell spacing constraint requires that any two cell edge types must meet the minimum spacing requirement, such as Figure 1 A mixed-cell height layout with multiple cell spacing constraints is shown, resulting in a triple cell spacing violation if both cell spacing requirements are not met.
[0032] However, traditional layout methods have limitations when dealing with multi-cell spacing constraints. In the legalization stage, they can often only solve the spacing constraints of two cell edges, while ignoring the more complex multi-cell spacing problem. As a result, a large number of adjustments are required in the subsequent detailed layout stage, and even a larger-scale layout reconstruction may be required. This not only prolongs the design cycle and increases costs, but also fails to meet the requirements of precision and reliability for VLSI design.
[0033] There are also some methods that convert multi-cell spacing constraints into critical two-cell spacing constraints. Although this simplifies the problem and alleviates the computational burden of the detailed layout stage to a certain extent, it compromises the quality of the solution and increases the risk that the design does not comply with process rules, thus affecting the performance and reliability of the final chip.
[0034] In view of this, the inventors discovered through research and improvement exploration that the existing integrated circuit mixed cell layout method does not fully consider the multi-cell spacing constraint problem, especially ignores the complex interactions between three or more cells, and is unable to capture all multi-cell spacing violations. The solutions found are often not optimal, resulting in the final design being unable to meet the requirements of high performance and high reliability.
[0035] Based on this, the embodiment of this specification proposes a method for layout of hybrid cells of integrated circuits: the overall idea is: by converting the layout problem of the integrated circuit into a weighted maximum satisfiability problem, ensuring that all design rule constraints are met, after the initial solution, for the remaining violation problems, a window-based method is used for local adjustment, and an iterative process is used to ensure that all spacing constraints are met, which significantly improves the compliance of the overall design, so that the design can meet the complex process requirements while effectively shortening the design cycle and reducing costs.
[0036] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.
[0037] like Figure 2 As shown, the embodiment of this specification provides a method for layout of an integrated circuit hybrid cell, comprising the following steps:
[0038] Step S1: Based on multi-cell spacing constraints, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area.
[0039] Specifically, in integrated circuit design, a certain minimum spacing needs to be maintained between cells of different types and sizes to avoid short circuits, ensure signal integrity, and meet manufacturing process requirements. Multi-cell spacing constraints involve the relative position relationship between three or more cells, which is more complicated than the traditional two-cell spacing constraints.
[0040] In practice, formulating this problem as a weighted maximum satisfiability problem can significantly reduce the number of violations in the layout and improve the compliance of the design. The time complexity of this satisfiability problem is O(b2 n ), where n is the number of different variables in the formula and b is the maximum number of occurrences of any variable in the input.
[0041] Step S2: For the remaining violation problems that are not solved in the solution process, a window-based method is used to adjust them.
[0042] In combination with the above embodiments, most violations are solved by converting it into a maximum satisfiability problem. However, violations still exist at the edges of different rectangular regions. Next, a window-based method is used to solve the remaining violations.
[0043] In some embodiments, modeling the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfiability problem includes:
[0044] definition For unit c i The kth candidate state of , l(r,p) is the pth position of the rth row;
[0045] For each unit, set hard clauses, including constraints that must be met unconditionally in the area to be laid out, as follows:
[0046] Each unit c i Only one variable must be selected At most one variable can exist at the same location.
[0047] For each unit, a soft clause is also set, including the constraints that can be compromised in the area to be laid out, as follows:
[0048] For the offending triple and The soft clause is expressed as Where β is a user-specified parameter;
[0049] and / or, to reduce Coordinates and legalized coordinates The displacement between the two, the soft clause is expressed as The weight The definition is as follows:
[0050] Here, γ is a user-specified parameter.
[0051] In some embodiments, modeling the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfiability problem further includes:
[0052] For each unit, two candidate states are generated, the candidate states including the original orientation and the horizontally flipped orientation;
[0053] Traverse the cells and take the corresponding cells as the current cells one by one to perform the following processing:
[0054] Determine whether the current unit satisfies a preset exchange condition for exchanging with an adjacent unit, and if so, generate candidate states corresponding to the original orientation and the horizontal flip orientation at the position of the adjacent unit;
[0055] Traverse the next unit until each unit is processed;
[0056] The preset exchange condition includes: if the current unit and the adjacent unit have the same vertical coordinate and height, and are located in the same area.
[0057] Specifically, in the process of modeling the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfiability problem, for each cell, we generate two candidate states, corresponding to the original orientation and the horizontal flip orientation at the original position, which increases the flexibility of the layout and allows more options for finding the best layout solution while satisfying the design rules.
[0058] Traverse all cells. If a cell and an adjacent cell have the same ordinate and height and are located in the same area, it indicates that the two cells are interchangeable in layout.
[0059] When the exchange conditions with adjacent units are met, you can choose to exchange the positions of the two units. After the exchange, not only does the original unit obtain a new position, but the unit at the new position (the original adjacent unit) also needs to reconsider its original orientation and horizontal flip orientation to generate candidate states under the new position state.
[0060] By increasing candidate states and inter-cell swapping, possible violations can be found and resolved in complex layout problems, thereby optimizing overall circuit performance and manufacturing feasibility.
[0061] In some embodiments, the integrated circuit hybrid cell layout method further includes: dividing the area to be laid out into a plurality of rectangular sub-areas, and the width and height of each of the rectangular sub-areas are defined as follows:
[0062] Among them, n region Indicates the number of areas specified by the user; W indicates the width of the layout area; H indicates the height of the layout area.
[0063] Specifically, we divide the layout area into multiple rectangular areas and treat each sub-area as an independent problem, which significantly reduces the amount of data required to be processed in a single calculation, thereby reducing the time complexity of the problem.
[0064] Furthermore, in the subsequent layout adjustment stage, if a violation is detected in a rectangular sub-region, adjustments can be made only to that specific region, avoiding large-scale changes to the entire layout, thereby improving the efficiency and flexibility of the design process.
[0065] In some embodiments, modeling the problem as a satisfiability problem for solving includes:
[0066] Modeling each of the rectangular sub-region problems as a weighted maximum satisfiability problem;
[0067] Solve the weighted maximum satisfiability problem using a parallel solver.
[0068] Specifically, after formulating the violation reduction problem as a maximum satisfiability problem in each rectangular region, the Open-WBO parallel solver can be used to process these sub-problems simultaneously. Open-WBO can process the maximum satisfiability problem of multiple rectangular sub-regions simultaneously, thereby quickly finding ways to reduce the number of violations, significantly reducing the solution time and speeding up the entire layout optimization process.
[0069] In some embodiments, the remaining violation problems that are not resolved during the solution process are adjusted using a window-based method, including:
[0070] All unresolved violation issues are stored in a queue format, wherein one tuple in the queue represents one violation issue;
[0071] When the queue is not empty, perform the following processing to obtain a compliant layout result:
[0072] Taking out the violation tuple at the front end of the queue from the queue, and generating a window with the violation unit in the violation tuple as the center;
[0073] Based on the window, a position lookup table is created, and each position in the position lookup table is marked, wherein a position not occupied by any unit is marked as a preset first value; a position occupied by a unit is marked as an index of the unit occupied;
[0074] Determining the unit to be moved or exchanged according to the position lookup table;
[0075] After adjusting the units to be moved or exchanged, the position lookup table and queue status are updated.
[0076] Specifically, unresolved violation tuples are stored in the format of a queue. If the queue is not empty, a violation tuple is popped from the queue. First, a window centered on the violation unit is generated. Based on the window, a data structure called a position lookup table is designed. In the position lookup table, the blank space is marked as -1, and the position occupied by the unit is marked as the index of the unit. Then, according to the position lookup table, the unit can be moved or exchanged to solve the violation problem.
[0077] Based on the same inventive concept, the present application also provides an integrated circuit hybrid cell layout device, comprising:
[0078] Problem modeling and solving module: based on multi-cell spacing constraints, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area;
[0079] Adjustment Module: For the remaining violations that are not resolved during the solving process, a window-based approach is used for adjustment.
[0080] Preferably, the integrated circuit hybrid cell layout device further comprises: a layout area division module;
[0081] The layout area division module is used to divide the layout area into multiple rectangular sub-areas, and the width and height of each rectangular sub-area are defined as follows:
[0082] Among them, n region Indicates the number of areas specified by the user; W indicates the width of the layout area; H indicates the height of the layout area.
[0083] Based on the same inventive concept, the present application also provides an electronic device based on an integrated circuit mixed cell layout method, or an electronic device based on an integrated circuit layout filling cell insertion method, the electronic device comprising: a processor, a memory and a computer program; wherein
[0084] The memory is used to store the computer program, and the memory may also be a flash memory. The computer program is, for example, an application program, a functional module, etc. for implementing the above method.
[0085] The processor is used to execute the computer program stored in the memory to implement each step performed by the device in the above method. For details, please refer to the relevant description in the above method embodiment.
[0086] Optionally, the memory can be independent or integrated with the processor.
[0087] When the memory is a device independent of the processor, the device may further include:
[0088] A bus is used to connect the memory and the processor.
[0089] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, they execute: the integrated circuit hybrid unit layout method as described in any embodiment of the present application.
[0090] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.
[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A method for layout of a hybrid cell of an integrated circuit, characterized in that: include: Based on the multi-cell spacing constraint condition, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area; For the remaining violations that are not resolved during the solving process, a window-based approach is used for adjustment.
2. The integrated circuit hybrid cell layout method according to claim 1, characterized in that: The method of modeling the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfiability problem includes: definition For unit c i The kth candidate state of , l(r,p) is the pth position of the rth row; For each unit, set hard clauses, including constraints that must be met unconditionally in the area to be laid out, as follows: Each unit c i You must select only one variable At most one variable can exist at the same location. For each unit, a soft clause is also set, including the constraints that can be compromised in the area to be laid out, as follows: For the offending triple and The soft clause is expressed as Where β is a user-specified parameter; and / or, to reduce Coordinates and legalized coordinates The displacement between the two, the soft clause is expressed as The weight The definition is as follows: Here, γ is a user-specified parameter.
3. The integrated circuit hybrid cell layout method according to claim 2, characterized in that: The step of modeling the problem of the area to be laid out of the integrated circuit as a weighted maximum satisfiability problem further includes: For each unit, two candidate states are generated, the candidate states including the original orientation and the horizontally flipped orientation; Traverse the cells and take the corresponding cells as the current cells one by one to perform the following processing: Determine whether the current unit satisfies a preset exchange condition for exchanging with an adjacent unit, and if so, generate candidate states corresponding to the original orientation and the horizontal flip orientation at the position of the adjacent unit; Traverse the next unit until each unit is processed; The preset exchange condition includes: if the current unit and the adjacent unit have the same vertical coordinate and height, and are located in the same area.
4. The integrated circuit hybrid cell layout method according to claim 1, characterized in that: The integrated circuit hybrid cell layout method further includes: dividing the area to be laid out into a plurality of rectangular sub-areas, wherein the width and height of each of the rectangular sub-areas are defined as follows: Among them, n region Indicates the number of areas specified by the user; W indicates the width of the layout area; H indicates the height of the layout area.
5. The integrated circuit hybrid cell layout method according to claim 4, characterized in that: The problem is modeled as a satisfiability problem and solved by: Modeling each of the rectangular sub-region problems as a weighted maximum satisfiability problem; Solve the weighted maximum satisfiability problem using a parallel solver.
6. The integrated circuit hybrid cell layout method according to claim 1, characterized in that: For the remaining violation problems that are not resolved during the solution process, a window-based method is used for adjustment, including: All unresolved violation issues are stored in a queue format, wherein one tuple in the queue represents one violation issue; When the queue is not empty, perform the following processing to obtain a compliant layout result: Taking out the violation tuple at the front end of the queue from the queue, and generating a window with the violation unit in the violation tuple as the center; Based on the window, a position lookup table is created, and each position in the position lookup table is marked, wherein a position not occupied by any unit is marked as a preset first value; a position occupied by a unit is marked as an index of the unit occupied; Determining the unit to be moved or exchanged according to the position lookup table; After adjusting the units to be moved or exchanged, the position lookup table and queue status are updated.
7. An integrated circuit hybrid cell layout device, characterized in that: include: Problem modeling and solving module: based on multi-cell spacing constraints, the problem of the area to be laid out of the integrated circuit is modeled as a weighted maximum satisfiability problem to reduce the number of violations, wherein the area to be laid out is a rectangular area; Adjustment Module: For the remaining violations that are not resolved during the solving process, a window-based approach is used for adjustment.
8. The integrated circuit hybrid cell layout device according to claim 7, characterized in that: The integrated circuit hybrid cell layout device further comprises: a layout area division module; The layout area division module is used to divide the layout area into multiple rectangular sub-areas, and the width and height of each rectangular sub-area are defined as follows: Among them, n region Indicates the number of areas specified by the user; W indicates the width of the layout area; H indicates the height of the layout area.
9. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit hybrid unit layout method as described in any one of claims 1-6.
10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the integrated circuit hybrid unit layout method according to any one of claims 1 to 6 is performed.