Chip detection method and chip grabbing equipment

Abstract

The invention discloses a chip detection method and chip grabbing equipment, and the method comprises the steps: providing a to-be-cut wafer, and enabling a chip region of the to-be-cut wafer to be provided with a plurality of connection structures and a plurality of test board structures; providing grabbing equipment, wherein the grabbing equipment comprises a suction nozzle structure and detection equipment; the suction nozzle structure adsorbs the chip structure, and the detection device obtains the detection resistance value of each connection structure; and comparing the reference resistance value of each connection structure with the corresponding detection resistance value, and judging whether the chip area has layered failure or not. Whether the edge of the chip area has the defect of layering failure or not is judged by comparing the resistance change before and after the wafer to be cut is cut, and whether the chip is influenced by layering and cracks or not can be judged visually and accurately; besides, the suction nozzle structure is combined with the detection equipment, and detection can be automatically completed while the suction nozzle structure adsorbs the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a chip detection method and a chip grabbing device. Background Art

[0002] Semiconductor products at large-size nodes (65 nanometers and above) use low dielectric constant materials to reduce the impact of parasitic capacitance and parasitic resistance. Compared with ordinary silicon oxide materials, this material is more fragile and is prone to die edge delamination (DED) due to stress during packaging and cutting.

[0003] Since the delamination occurs on the side of the chip and the cracks are tiny, it is difficult to effectively detect them using conventional manual or optical inspection methods. Using SEM / FIB and other methods is costly and inefficient, making it difficult to apply on a large scale.

[0004] Therefore, a fast, reliable and low-cost edge delamination inspection method is needed to ensure the quality and reliability of automotive-grade semiconductor chips. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a chip detection method and a chip grabbing device to ensure the quality and reliability of automotive-grade semiconductor chips in an efficient, accurate, automated and low-cost manner.

[0006] In order to solve the above problems, the technical solution of the present invention provides a chip detection method, comprising: providing a wafer to be cut, the wafer to be cut includes a plurality of chip areas and a plurality of cutting road areas, the cutting road areas are located between the chip areas, the chip areas include an effective area and an ineffective area, the effective area includes a first area and a second area surrounding the first area; forming a plurality of connection structures on the second area; forming a plurality of test board structures on the ineffective area, each of the connection structures is electrically connected to the adjacent test board structures; cutting the wafer to be cut along the cutting road areas to form a plurality of chip structures; After cutting, a grasping device is used to grasp the chip structure; the grasping device includes: a suction nozzle structure, the suction nozzle structure has a vacuum adsorption cavity; a plurality of receiving plate structures located on the adsorption surface of the suction nozzle structure; and a detection device electrically connected to the plurality of receiving plate structures. When the grasping device grasps the chip structure, the suction nozzle structure adsorbs the surface of the chip structure, and the plurality of receiving plate structures are respectively in contact with the corresponding test board structures, and the detection device obtains the detection resistance value of each of the connection structures. The reference resistance value of each of the connection structures is compared with the corresponding detection resistance value to determine whether there is a delamination failure in the chip area.

[0007] Optionally, the chip area also includes: a protection ring structure located on the second area, the protection ring structure surrounds the first area, the protection ring structure includes a plurality of first parts and a plurality of second parts, each of the second parts is located between the ineffective area and the first area; each of the connection structures is parallel to the corresponding first part, and the protection ring structure is located between the plurality of the connection structures and the first area.

[0008] Optionally, the shape of the chip area includes a rectangle; and the ineffective area includes four vertex corners of the chip area.

[0009] Optionally, the shape of the inactive area includes a triangle; and the connecting structure further extends to the inactive area.

[0010] Optionally, the connection structure includes: a plurality of stacked structures parallel to the corresponding first parts, and the plurality of stacked structures are electrically connected to each other; the stacked structure includes: a plurality of metal layers vertically stacked and parallel to the corresponding first parts, and connecting plugs located between adjacent metal layers; the metal layer located on the top layer is electrically connected to the test board structure.

[0011] Optionally, after forming the connection structure and before forming the test board structure, the method further includes: forming a dielectric structure on the chip area, wherein the connection structure and the guard ring structure are located in the dielectric structure, and the test board structure is located on the dielectric structure.

[0012] Optionally, after forming the test board structure, the method further includes: forming a passivation layer on the chip area, wherein the passivation layer covers the connection structure and the guard ring structure, and the passivation layer exposes a portion of the test board structure.

[0013] Optionally, the material of the test board structure includes metal, and the metal includes aluminum.

[0014] Optionally, the method of comparing the reference resistance of each of the connection structures with the corresponding detection resistance to determine whether there is a delamination failure in the chip area includes: obtaining the difference between the reference resistance of each of the connection structures and the corresponding detection resistance; if the difference between the reference resistance and the detection resistance is within a preset range, determining that there is no delamination failure defect in the chip area; if the difference between the reference resistance and the detection resistance exceeds the preset range, determining that there is a delamination failure defect in the chip area.

[0015] Optionally, the method for obtaining the detection resistance value of each of the connecting structures includes: after the suction nozzle structure adsorbs the chip structure, arbitrarily selecting two adjacent receiving plate structures to form an electrical path with the detection device, and the detection device obtains the detection resistance value of a single connecting structure until the detection of the detection resistance values ​​of all the connecting structures is completed.

[0016] Optionally, the nozzle structure also has a plurality of first interfaces, and the plurality of first interfaces are electrically connected to the corresponding receiving plate structures; the detection device has a plurality of second interfaces, and the second interfaces are electrically connected to the corresponding first interfaces, so as to realize electrical connection between the plurality of receiving plate structures and the detection device.

[0017] Correspondingly, the technical solution of the present invention also provides a chip grasping device, including: a suction nozzle structure, the suction nozzle structure has a vacuum adsorption cavity; a plurality of receiving plate structures located on the adsorption surface of the suction nozzle structure; and a detection device electrically connected to the plurality of receiving plate structures.

[0018] Optionally, the nozzle structure also has a plurality of first interfaces, and the plurality of first interfaces are electrically connected to the corresponding receiving plate structures; the detection device has a plurality of second interfaces, and the second interfaces are electrically connected to the corresponding first interfaces, so as to realize electrical connection between the plurality of receiving plate structures and the detection device.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the chip detection method of the technical solution of the present invention, by comparing the resistance value changes before and after cutting the wafer to be cut, it is judged whether there is a delamination failure defect at the edge of the chip area, and whether the chip is affected by delamination and cracks can be judged intuitively and accurately; in addition, by combining the suction nozzle structure with the detection equipment, the detection can be automatically completed while the suction nozzle structure adsorbs the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost.

[0021] In the chip grabbing structure of the technical solution of the present invention, by combining the suction nozzle structure with the detection equipment, the detection can be automatically completed while the suction nozzle structure adsorbs the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 8 It is a schematic diagram of the structure of each step of the chip detection method in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As described in the background technology, a fast, reliable, and low-cost edge layer inspection method is needed to ensure the quality and reliability of automotive-grade semiconductor chips.

[0024] Specifically, due to thermal stress of the package, cracks and delamination are likely to occur in the triangular area at the four corners of the chip. During design, the triangular area at the four corners of the chip is usually defined as the ineffective area of ​​the chip, resulting in a waste of chip area.

[0025] Currently, the industry lacks reliable detection methods for cracks and delamination failures. Due to accuracy reasons, general optical inspection or manual inspection has a serious false positive rate or omission rate, which makes it difficult to meet the quality and reliability requirements of automotive semiconductor products.

[0026] On this basis, the present invention provides a chip detection method and a chip grabbing device, which can judge whether there is a delamination failure defect at the edge of the chip area by comparing the resistance value changes before and after cutting the wafer to be cut, and can intuitively and accurately judge whether the chip is affected by delamination and cracks; in addition, by combining a suction nozzle structure with the detection device, the suction nozzle structure can automatically complete the detection while adsorbing the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost.

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figures 1 to 8 It is a schematic diagram of the structure of each step of the chip detection method in an embodiment of the present invention.

[0029] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 An enlarged structural schematic diagram of the middle chip area 101 provides a wafer 100 to be cut, wherein the wafer 100 to be cut includes a plurality of chip areas 101 and a plurality of cutting road areas 102, wherein the cutting road areas 102 are located between the chip areas 101, and the chip area 101 includes an effective area A and an ineffective area B, wherein the effective area A includes a first area I and a second area II surrounding the first area I.

[0030] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 Schematic diagram of the enlarged structure of the connection structure 104, a plurality of connection structures 104 are formed on the second area II; a plurality of test board structures 107 are formed on the non-effective area B, and each of the connection structures 104 is electrically connected to the adjacent test board structures 107.

[0031] In this embodiment, the chip area further includes:

[0032] The test structure also includes: a protection ring structure 103 located on the second area II, the protection ring structure 103 surrounds the first area I, the protection ring structure 103 includes a plurality of first parts and a plurality of second parts (not marked), each of the second parts is located between the inactive area B and the first area I; each of the connection structures 104 is parallel to the corresponding first part, and the protection ring structure 103 is located between the plurality of the connection structures 104 and the first area I.

[0033] In this embodiment, the chip area 101 has a rectangular shape; the inactive area B includes four corners of the chip area 101 .

[0034] In this embodiment, the shape of the inactive area B includes a triangle.

[0035] In this embodiment, the guard ring structure 103 is used to protect the device structure on the first region I from being affected by cutting or other reliability effects.

[0036] In this embodiment, the guard ring structure 103 includes a multi-layer metal stacking structure.

[0037] In this embodiment, the connection structure 104 and the guard ring structure 103 are formed based on the same process steps.

[0038] In this embodiment, the connection structure 104 also extends to the inactive area B so as to be electrically connected to the test board structure later.

[0039] In this embodiment, the connection structure 104 includes: a plurality of stacked structures parallel to the first part of the protection ring structure 103, and the plurality of stacked structures are electrically connected to each other; the stacked structure includes: a plurality of vertically stacked metal layers 106 parallel to the first part of the protection ring structure 103, and a connection plug 105 located between adjacent metal layers 106.

[0040] In this embodiment, the thickness of the metal layer 106 located at the top layer is greater than the thickness of the metal layer 106 located at the bottom layer.

[0041] In this embodiment, a plurality of stacked structures are electrically connected to each other through the metal layer 106 at the bottom layer and the metal layer 106 at the top layer.

[0042] In this embodiment, after forming the connection structure and before forming the test board structure, the method further includes: forming a dielectric structure (not shown) on the chip area 101 , wherein the connection structure 104 and the guard ring structure 103 are located in the dielectric structure.

[0043] In this embodiment, the test board structure 107 is located on the dielectric structure.

[0044] In this embodiment, the test board structure 107 is located at four corner areas of the chip area 101 .

[0045] In this embodiment, the metal layer 106 at the topmost layer is electrically connected to the test board structure 107. One test board structure 107 is electrically connected to the connection structures 104 on both sides, that is, all four test board structures 107 are electrically connected through the connection structures 104.

[0046] In this embodiment, the material of the test board structure 107 includes metal, and the metal includes aluminum.

[0047] In this embodiment, after forming the test board structure 107, it also includes: forming a passivation layer (not shown) on the chip area 101, the passivation layer covers the connection structure 104 and the protection ring structure 103, and the passivation layer exposes a portion of the test board structure 107 to facilitate connecting a metal probe during subsequent testing.

[0048] Please refer to Figure 5 , Figure 5 and Figure 1 The wafer 100 to be cut is cut along the cutting road area 102 to form a plurality of chip structures.

[0049] In this embodiment, after obtaining a plurality of the chip structures, in a subsequent manufacturing process, each of the chip structures needs to be captured by a capture device and placed in a test bench for detection.

[0050] Please refer to Figure 6 and Figure 7 , Figure 6 is a side view of the nozzle structure 200, Figure 7 It is a bottom view of the suction surface 200b of the suction nozzle structure 200. After the wafer 100 to be cut is cut, the chip structure is grabbed by a grabbing device.

[0051] In this embodiment, the gripping device includes: a nozzle structure 200 having a vacuum adsorption cavity 200a; a plurality of receiving plate structures 201 located on the adsorption surface 200b of the nozzle structure 200; and a detection device 202 electrically connected to the plurality of receiving plate structures 201.

[0052] In this embodiment, the nozzle structure 200 is used to adsorb each chip structure into a test bench for testing.

[0053] In this embodiment, the nozzle structure 200 also has a plurality of first interfaces 203, and the plurality of first interfaces 203 are electrically connected to the corresponding receiving plate structures 201; the detection device 202 has a plurality of second interfaces 204, and the second interfaces 204 are electrically connected to the corresponding first interfaces 203, so as to realize electrical connection between the plurality of receiving plate structures 201 and the detection device 202.

[0054] In this embodiment, the detection device 202 is a D / A detection device.

[0055] Please refer to Figure 8 When the grasping device grasps the chip structure, the suction nozzle structure 200 adsorbs the surface of the chip structure, and several receiving plate structures 201 are respectively in contact with the corresponding test board structures 107 , and the detection device 202 obtains the detection resistance value of each of the connecting structures 104 .

[0056] In this embodiment, the method for obtaining the detection resistance value of each of the connecting structures 104 includes: after the nozzle structure 200 adsorbs the chip structure, arbitrarily selecting two adjacent receiving plate structures 201 and the detection device 202 to form an electrical path, and the detection device 202 obtains the detection resistance value of a single connecting structure 104 until the detection resistance value detection of all the connecting structures 104 is completed.

[0057] Please continue to refer to Figure 8 , comparing the reference resistance of each of the connection structures 104 with the corresponding detection resistance to determine whether the chip region 101 has delamination failure.

[0058] In this embodiment, the reference resistance of each of the connection structures 104 is compared with the corresponding detection resistance to determine whether the chip area 101 has a delamination failure, which includes: obtaining the difference between the reference resistance of each of the connection structures 104 and the corresponding detection resistance; if the difference between the reference resistance and the detection resistance is within a preset range, it is determined that the chip area 101 does not have a delamination failure defect; if the difference between the reference resistance and the detection resistance exceeds the preset range, it is determined that the chip area 101 has a delamination failure defect.

[0059] In this embodiment, by comparing the resistance value changes before and after cutting the wafer 100 to be cut, it is determined whether there is a delamination failure defect at the edge of the chip area 101, so it is possible to intuitively and accurately determine whether the chip is affected by delamination and cracks; in addition, by combining the suction nozzle structure 200 with the detection equipment 202, the suction nozzle structure 200 can automatically complete the detection while adsorbing the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost.

[0060] In this embodiment, the method for obtaining the reference resistance value of each of the connection structures 104 includes: theoretically calculating the reference resistance value of each of the connection structures 104 according to the structure of each of the connection structures 104 .

[0061] In other embodiments, the resistance values ​​of the connection structures in several chip structures that have not produced delamination failure defects in the past can be obtained after the substrate is subsequently cut, and this can be equivalent to the reference resistance values ​​of each connection structure to be detected in this embodiment.

[0062] Correspondingly, the embodiment of the present invention also provides a chip grabbing device, please continue to refer to Figure 6 and Figure 7 , including: a suction nozzle structure 200, wherein the suction nozzle structure 200 has a vacuum adsorption cavity 200a; a plurality of receiving plate structures 201 located on the adsorption surface 200b of the suction nozzle structure 200; and a detection device 202 electrically connected to the plurality of receiving plate structures 201.

[0063] In this embodiment, by combining the nozzle structure 200 with the detection device 202, the detection can be automatically completed while the nozzle structure 200 absorbs the chip structure, so that the detection process has the advantages of high efficiency, accuracy, automation and low cost.

[0064] In this embodiment, the nozzle structure 200 also has a plurality of first interfaces 203, and the plurality of first interfaces 203 are electrically connected to the corresponding receiving plate structures 201; the detection device 202 has a plurality of second interfaces 204, and the second interfaces 204 are electrically connected to the corresponding first interfaces 203, so as to realize electrical connection between the plurality of receiving plate structures 201 and the detection device 202.

[0065] In this embodiment, the detection device 202 is a D / A detection device.

[0066] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip detection method, characterized in that: include: Providing a wafer to be cut, the wafer to be cut comprises a plurality of chip areas and a plurality of cutting road areas, the cutting road areas are located between the chip areas, the chip areas comprise effective areas and ineffective areas, the effective areas comprise a first area and a second area surrounding the first area; forming a plurality of connection structures on the second region; forming a plurality of test board structures on the inactive area, wherein each of the connection structures is electrically connected to an adjacent test board structure; Cutting the wafer to be cut along the cutting road area to form a plurality of chip structures; After cutting the wafer to be cut, using a grabbing device to grab the chip structure; The gripping device comprises: a suction nozzle structure having a vacuum adsorption cavity; a plurality of receiving plate structures located on the adsorption surface of the suction nozzle structure; and a detection device electrically connected to the plurality of receiving plate structures; When the grabbing device grabs the chip structure, the suction nozzle structure absorbs the surface of the chip structure, and a number of the receiving plate structures are respectively in contact with the corresponding test plate structures, and the detection device obtains the detection resistance value of each of the connection structures; The reference resistance value of each of the connection structures is compared with the corresponding detection resistance value to determine whether the chip region has delamination failure.

2. The chip detection method according to claim 1, characterized in that: The chip area also includes: a protection ring structure located on the second area, the protection ring structure surrounds the first area, the protection ring structure includes a plurality of first parts and a plurality of second parts, each of the second parts is located between the ineffective area and the first area; each of the connection structures is parallel to the corresponding first part, and the protection ring structure is located between the plurality of the connection structures and the first area.

3. The chip detection method according to claim 1, characterized in that: The shape of the chip area includes a rectangle; the inactive area includes four corners of the chip area.

4. The chip detection method according to claim 3, characterized in that: The shape of the inactive area includes a triangle; and the connection structure further extends to the inactive area.

5. The chip detection method according to claim 2, characterized in that: The connection structure includes: a plurality of stacked structures parallel to the corresponding first parts, and the plurality of stacked structures are electrically connected to each other; the stacked structure includes: a plurality of vertically stacked metal layers parallel to the corresponding first parts, and connecting plugs located between adjacent metal layers; the metal layer located on the top layer is electrically connected to the test board structure.

6. The chip detection method according to claim 2, characterized in that: After forming the connection structure and before forming the test board structure, the method further includes: forming a dielectric structure on the chip area, wherein the connection structure and the guard ring structure are located in the dielectric structure, and the test board structure is located on the dielectric structure.

7. The chip detection method according to claim 1, characterized in that: After forming the test board structure, the method further includes: forming a passivation layer on the chip area, wherein the passivation layer covers the connection structure and the guard ring structure, and the passivation layer exposes a portion of the test board structure.

8. The chip detection method according to claim 1, characterized in that: The material of the test board structure includes metal, and the metal includes aluminum.

9. The chip detection method according to claim 1, characterized in that: The method of comparing the reference resistance of each of the connection structures with the corresponding detection resistance to determine whether the chip area has a delamination failure includes: obtaining the difference between the reference resistance of each of the connection structures and the corresponding detection resistance; if the difference between the reference resistance and the detection resistance is within a preset range, determining that the chip area does not have a delamination failure defect; if the difference between the reference resistance and the detection resistance exceeds the preset range, determining that the chip area has a delamination failure defect.

10. The chip detection method according to claim 1, characterized in that: The method for obtaining the detection resistance value of each of the connection structures includes: after the nozzle structure adsorbs the chip structure, arbitrarily selecting two adjacent receiving plate structures to form an electrical path with the detection device, and the detection device obtains the detection resistance value of a single connection structure until the detection of the detection resistance values ​​of all the connection structures is completed.

11. The chip detection method according to claim 1, characterized in that: The suction nozzle structure also has a plurality of first interfaces, which are electrically connected to the corresponding receiving plate structures; the detection device has a plurality of second interfaces, which are electrically connected to the corresponding first interfaces to realize electrical connection between the plurality of receiving plate structures and the detection device.

12. A chip grabbing device, characterized in that: include: A suction nozzle structure, wherein the suction nozzle structure has a vacuum adsorption cavity; A plurality of receiving plate structures located on the suction surface of the suction nozzle structure; A detection device electrically connected to the plurality of docking plate structures.

13. The chip grabbing device according to claim 12, characterized in that: The suction nozzle structure also has a plurality of first interfaces, which are electrically connected to the corresponding receiving plate structures; the detection device has a plurality of second interfaces, which are electrically connected to the corresponding first interfaces to realize electrical connection between the plurality of receiving plate structures and the detection device.

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