Switching converter, zero cross detection circuit and method thereof, chip and display device

Abstract

The invention discloses a switching converter and a zero-cross detection circuit and method thereof, a chip and a display device, and the zero-cross detection circuit comprises a comparator which is used for comparing the voltage of a switching node with the output voltage of the switching converter to obtain a first comparison signal; the turn-on time control circuit is used for generating a turn-on time control signal according to the first comparison signal; and the adjustable delay circuit is used for adjusting the conduction duration of the synchronous switching tube in each switching period according to the conduction time control signal, so that the light load efficiency of the switching converter is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a switching converter and a zero-crossing detection circuit and method, a chip, and a display device thereof. Background Art

[0002] A switching converter is a power supply that uses modern power electronics technology to control the on-time ratio of the switch tube and maintain a stable output voltage. Synchronous DC-DC converters are widely used because of their low conduction loss. However, due to the bidirectional conduction characteristics of MOS tubes, when the DC-DC converter is in light load mode, current backflow is prone to occur, resulting in energy loss, which significantly reduces its efficiency in light load mode. Therefore, the existing technology will add an inductor current zero-crossing detection circuit (ZCD) inside the DC-DC converter to prevent inductor current backflow, thereby improving the efficiency of the DC-DC converter in light load mode.

[0003] Figure 1 FIG. 1 shows a schematic diagram of the structure of a switching converter in the prior art. Figure 1 The switching converter 100 includes a power element L and a main switch tube MN connected in series between an input voltage Vin and a ground terminal, a synchronous switch tube MP and a capacitor Cout connected in series between a common node SW of the inductor L and the main switch tube MN and a ground terminal, a load RL connected in parallel with the capacitor Cout, and a common node of the synchronous switch tube MP and the capacitor Cout provides an output voltage Vout. The switching converter 100 also includes driving units 110 and 120, a PWM logic control circuit 130, and a comparator 140 used as a zero-crossing detection circuit. The PWM logic control circuit 130 is used to provide control signals to the driving units 110 and 120 respectively, so that the driving units 110 and 120 respectively drive the main switch tube MN and the synchronous switch tube MP to turn on and off. The comparator 140 is used to detect the voltage change at both ends of the synchronous switch tube MP and output the comparison result to the PWM logic control circuit 130. When the voltage Vsw of the switch node SW is less than the output voltage Vout, the inductor current IL flows back, and the zero-crossing detection signal ZCD sent by the comparator 140 turns off the synchronous switch tube MP. Because the comparator 140 itself has an offset and a delay, and the signal transmission also has a delay, therefore, in order to ensure that the synchronous switch tube MP is turned off at the zero-crossing point of the inductor current IL, the prior art will add a certain amount of offset to the comparator 140, but this solution is only applicable to the case where the input voltage Vin and the output voltage Vout of the switching converter 100 are fixed. When the output voltage Vout changes, the slope of the inductor current IL changes, which will cause the synchronous switch tube MP to be turned off too early or too late.

[0004] See also Figure 2a, which is a schematic diagram of the change of the inductor current IL when the synchronous switch MP is turned off too late. At this time, the inductor current IL will have a current reverse phase, during which the capacitor Cout reversely discharges, resulting in energy loss. Figure 2b , which is a schematic diagram of the change of the inductor current IL when the synchronous switch tube MP is turned off too early. At this time, the inductor current IL will flow to the load RL through the body diode of the synchronous switch tube MP. In this stage, the conduction voltage drop of the body diode will cause energy loss. Therefore, if the synchronous switch tube MP is turned off too early or too late, the efficiency of the switching converter 100 will be reduced.

[0005] Therefore, a new switching converter and its zero-crossing detection circuit are yet to be proposed to solve the above problems. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a switching converter and a zero-crossing detection circuit and method, a chip, and a display device thereof, so as to improve the light-load efficiency of the switching converter.

[0007] According to a first aspect of the present invention, a zero-crossing detection circuit of a switching converter is provided, wherein the switching converter comprises a main switch tube and a synchronous switch tube, wherein a common node of the main switch tube and the synchronous switch tube is a switch node, and the zero-crossing detection circuit comprises a comparator for comparing a voltage of the switch node with an output voltage of the switching converter to obtain a first comparison signal according to a comparison result; an on-time control circuit for generating an on-time control signal according to the first comparison signal; and an adjustable delay circuit for adjusting the on-time length of the synchronous switch tube in each switching cycle according to the on-time control signal.

[0008] Optionally, the adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor, and the adjustable delay circuit is used to control the shutdown of the synchronous switch tube when the voltage of the delay capacitor is charged to a set threshold value, so as to control the on-time of the synchronous switch tube in each switching cycle, wherein the adjustable delay circuit is also used to adjust the capacitance value of the delay capacitor according to the on-time control signal, so as to adaptively adjust the on-time of the synchronous switch tube in each switching cycle.

[0009] Optionally, the on-time control circuit is used to perform addition and subtraction counting operations according to the level state of the first comparison signal in each switching cycle to generate the on-time control signal.

[0010] Optionally, the on-time control circuit includes a D flip-flop, used to sample and hold the first comparison signal in each switching cycle to obtain a trigger signal corresponding to the level state of the first comparison signal; and an add-subtract counter, used to perform addition and subtraction operations according to the value of the trigger signal in each switching cycle to adjust the value of the on-time control signal.

[0011] Optionally, the on-time control circuit also includes a SAR logic circuit, which is used to provide a logic digital signal to the add-subtract counter when the zero-crossing detection circuit cannot complete the calibration of the turn-off moment of the synchronous switch tube through the add-subtract counter within a set time, so that the add-subtract counter directly outputs the logic digital signal as the on-time control signal.

[0012] Optionally, the on-time control circuit also includes a counting control module, which is used to count the number of times that the trigger signal is continuously at the same level in multiple consecutive switching cycles to obtain a count value, and obtain a counting enable signal based on the count value, and the counting enable signal is used to control the working state of the add-subtract counter and the SAR logic circuit, wherein when the counting enable signal is in a first level state, the add-subtract counter is in a pass-through mode, and the SAR logic circuit works, and when the counting enable signal is in a second level state, the add-subtract counter is in an add-subtract counting mode, and the SAR logic circuit does not work.

[0013] Optionally, the comparator is a dynamic comparator, and the comparator compares the voltage of the switch node and the output voltage of the switching converter at the turn-off moment of the synchronous switch tube to obtain the first comparison signal according to the comparison result.

[0014] Optionally, the counting control module uses a first counting value and a second counting value to count the number of times that the trigger signal is continuously at the first level and the second level respectively, and when one of the counting values ​​is increased by 1, the other counting value is reset, and when the first counting value or the second counting value is greater than or equal to a preset value, the counting enable signal is flipped from the second level to the first level; the SAR logic circuit converts the trigger signal in a plurality of consecutive switching cycles into a logic digital signal through a successive approximation algorithm, and outputs a reset signal to the counting control module after the conversion is completed, and it also outputs a corresponding logic digital signal to the up-down counter in each switching cycle of the plurality of switching cycles; the counting control module is also used to reset the counting value after receiving the reset signal.

[0015] Optionally, the adjustable delay circuit also includes a first switch tube and a second switch tube, which are connected in sequence between the first current source and the charging path of the delay capacitor, and the first switch tube and the second switch tube turn on the charging path when the synchronous switch tube is turned on to output a first voltage signal at a first node between the first switch tube and the second switch tube; a voltage comparison module, connected to the first node, for comparing the first voltage signal with the set threshold to obtain a second comparison signal based on the comparison result; an output module, for generating a zero-crossing detection signal based on the second comparison signal and the driving signal of the main switch tube, wherein, when the voltage of the delay capacitor is charged to the set threshold, the zero-crossing detection signal controls the synchronous switch tube to turn off.

[0016] Optionally, the adjustable delay circuit also includes a third switch tube, connected between the power supply voltage and the first node, the third switch tube is turned on when the first voltage signal rises to the set threshold value to maintain the voltage of the first node at the power supply voltage; a fourth switch tube, connected between the two ends of the delay capacitor, the fourth switch tube is used to be turned on when the first voltage signal rises to the set threshold value to reset the voltage of the delay capacitor; a fifth switch tube, connected between the first node and the ground terminal, the fifth switch tube is used to be turned on when the main switch tube is turned on to reset the voltage of the first node.

[0017] Optionally, the adjustable delay circuit also includes a control signal generating module, which is used to perform an OR operation on the second comparison signal and the drive signal of the main switch tube to obtain a first control signal, and invert the first control signal to obtain a second control signal, the first control signal is provided to the control end of the fourth switch tube, and the second control signal is provided to the control ends of the second switch tube and the third switch tube; the output module is used to perform an AND operation on the inverted signal of the second comparison signal and the inverted signal of the drive signal of the main switch tube to obtain the zero-crossing detection signal.

[0018] Optionally, the charging current provided by the first current source to the delay capacitor is related to a voltage difference between a preset output voltage and an input voltage.

[0019] Optionally, the first current source receives a regulation signal related to a preset output voltage, and generates the charging current according to the regulation signal; the voltage comparison module includes a second current source and a first transistor, which are connected between the power supply voltage and the ground terminal in sequence, the control terminal of the first transistor receives the first voltage signal, the second current source provides a bias current, and the intermediate node between the second current source and the first transistor provides the second comparison signal, and the set threshold is equal to the threshold voltage of the first transistor; the delay capacitor includes a first capacitor and a switch capacitor array connected in parallel, the switch capacitor array includes a plurality of capacitor branches with the same number of bits as the on-time control signal, the first to the last capacitor branches are controlled by the lowest bit to the highest bit of the on-time control signal in sequence, and are selectively connected in parallel with the first capacitor.

[0020] According to a second aspect of the present invention, a zero-crossing detection method for a switching converter is provided, wherein the switching converter comprises a main switch tube and a synchronous switch tube, wherein a common node of the main switch tube and the synchronous switch tube is a switch node, and the zero-crossing detection method comprises comparing a voltage of the switch node with an output voltage of the switching converter to obtain a first comparison signal according to a comparison result; generating an on-time control signal according to the first comparison signal; and controlling the synchronous switch tube to turn off according to the on-time control signal.

[0021] Optionally, controlling the shutdown of the synchronous switch tube according to the on-time control signal includes adjusting the capacitance value of the delay capacitor according to the on-time control signal, charging the delay capacitor with a charging current during the on-phase of the synchronous switch tube, and controlling the shutdown of the synchronous switch tube when the voltage of the delay capacitor is charged to a set threshold.

[0022] Optionally, generating the on-time control signal according to the first comparison signal includes sampling and holding the first comparison signal to obtain a trigger signal corresponding to the level state of the first comparison signal; counting the number of times the trigger signal is continuously at the same level in a plurality of consecutive switching cycles to obtain a count value, and outputting a count enable signal according to the count value; when the count enable signal is at a second level, performing addition and subtraction operations according to the value of the trigger signal to obtain the on-time control signal, and when the count enable signal flips from the second level to the first level, converting the trigger signal in a plurality of consecutive switching cycles into a logic digital signal through a successive approximation algorithm, resetting the count value after the conversion is completed, and outputting the corresponding logic digital signal as the on-time control signal in each switching cycle of the plurality of switching cycles.

[0023] Optionally, the charging current is related to a voltage difference between a preset output voltage and an input voltage.

[0024] According to a third aspect of the present invention, there is provided a switching converter, comprising a main switch tube and a synchronous switch tube, wherein the intermediate node between the main switch tube and the synchronous switch tube is a switch node; an inductor connected to the switch node; a first drive unit, configured to generate a first drive signal according to a first switch control signal to drive the main switch tube to be turned on and off; a second drive unit, configured to generate a second drive signal according to a second switch control signal to drive the synchronous switch tube to be turned on and off; a PWM logic control circuit, configured to provide the first switch control signal and the second switch control signal to the first drive unit and the second drive unit respectively; and a zero-crossing detection circuit as described above, configured to provide the zero-crossing detection signal to the second drive unit.

[0025] According to a fourth aspect of the present invention, there is provided a chip comprising the switching converter as described above.

[0026] According to a fifth aspect of the present invention, there is provided a display device, comprising a display panel for displaying an image; a driving circuit for controlling a display state of the display panel; and a switching converter as described above.

[0027] The present invention provides a switching converter and a zero-crossing detection circuit and method, a chip, and a display device thereof. The comparator compares the voltage of the switching node with the output voltage of the switching converter to obtain a first comparison signal according to the comparison result; the on-time control circuit generates an on-time control signal according to the first comparison signal; and the adjustable delay circuit is used to adjust the on-time length of the synchronous switch tube in each switching cycle according to the on-time control signal, thereby improving the light-load efficiency of the switching converter.

[0028] In a preferred embodiment, by setting a counting control module and a SAR logic circuit in the conduction time control circuit, when a sudden change occurs in the load current, the switching converter can be quickly switched between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM), so that the switching converter can quickly enter a stable state.

[0029] In a preferred embodiment, the adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor. The adjustable delay circuit controls the synchronous switch tube to turn off when the voltage of the delay capacitor is charged to a set threshold value. By setting the charging current provided by the first current source to be related to the voltage difference between the preset output voltage and the input voltage, the zero-crossing detection circuit can maintain the same accuracy under different preset output voltages, thereby achieving precise shutdown of the synchronous switch tube at the zero-crossing point of the inductor current, thereby further improving the light-load efficiency of the switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 A schematic structural diagram of a switching converter according to the prior art is shown;

[0032] Figure 2a-2b A schematic diagram showing the change in the inductor current of the switching converter when the synchronous switch is turned off too early or too late;

[0033] Figure 3 A schematic structural diagram of a switching converter according to an embodiment of the present invention is shown;

[0034] Figure 4 A circuit diagram of a conduction time control circuit according to an embodiment of the present invention is shown;

[0035] Figure 5 A schematic diagram showing the operation of a SAR logic circuit according to an embodiment of the present invention is shown;

[0036] Figure 6 A circuit diagram of an adjustable delay circuit according to an embodiment of the present invention is shown;

[0037] Figure 7 A timing diagram of an adjustable delay circuit according to an embodiment of the present invention is shown;

[0038] Figure 8 A schematic diagram showing the operation of a zero-crossing detection circuit according to an embodiment of the present invention is shown;

[0039] Fig. 9 A flow chart of a zero-crossing detection method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0041] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0042] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0043] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0044] Figure 3 A schematic structural diagram of a switching converter according to an embodiment of the present invention is shown.

[0045] See also Figure 3 The switching converter 200 provided in the embodiment of the present invention includes a power element L and a synchronous switch tube MP connected in series between the input end and the output end of the switching converter 200, a main switch tube MN connected in series between the switch node SW and the ground end, a capacitor Cout connected between the output end and the ground end of the switching converter 200, and a load RL connected in parallel with the capacitor Cout. Among them, the power element L is an inductor, the main switch tube MN is, for example, an NMOS tube, and the synchronous switch tube MP is, for example, a PMOS tube. The switch node SW is an intermediate node between the power element L and the main switch tube MN. The output end of the switching converter 200, that is, the common node of the synchronous switch tube MP and the capacitor Cout, provides an output voltage Vout, and the input end of the switching converter 200 receives an input voltage Vin.

[0046] The switching converter 200 further includes driving units 210 and 220, a PWM logic control circuit 230, and a zero-crossing detection circuit. The PWM logic control circuit 230 is used to provide switch control signals Lg_ctrl and Hg_ctrl to the driving units 210 and 220, respectively. The switch control signals Lg_ctrl and Hg_ctrl are, for example, PWM signals. The driving unit 210 is used to generate a drive signal Lg_drv according to the switch control signal Lg_ctrl to drive the main switch tube MN to turn on and off. The drive signal Lg_drv, for example, drives the main switch tube MN to turn on when the high level is high, and drives the main switch tube MN to turn off when the low level is low. The driving unit 220 is used to generate a drive signal Hg_drv according to the switch control signal Hg_ctrl and the zero-crossing detection signal ZCD to drive the synchronous switch tube MP to turn on and off. The drive signal Hg_drv, for example, drives the synchronous switch tube MP to turn on when the high level is high, and drives the synchronous switch tube MP to turn off when the low level is low. The driving unit 220 drives the synchronous switch tube MP to turn off when the zero-crossing detection signal ZCD indicates that the inductor current IL reaches the zero-crossing point. The zero-crossing detection circuit is used to output the zero-crossing detection signal ZCD according to the magnitude relationship of the voltages at both ends of the synchronous switch tube MP. The zero-crossing detection circuit includes a comparator 240, a conduction time control circuit 250, and an adjustable delay circuit 260.

[0047] Optionally, when the zero-crossing detection signal ZCD is flipped from the second level to the first level, it indicates that the inductor current IL reaches the zero-crossing point. The first level can be a low level or a high level. When the first level is a high level, the second level is a low level. When the first level is a low level, the second level is a high level. In the subsequent embodiments, the first level is a high level and the second level is a low level as an example.

[0048] The comparator 240 is used to compare the voltage Vsw of the switch node SW with the output voltage Vout, so as to obtain a comparison signal Q according to the comparison result. The comparator 240 is, for example, a dynamic comparator. Optionally, the comparator 240 only works once in a switching cycle (i.e., the interval between two turn-off moments of the synchronous switch tube MP), that is, it only compares the voltage Vsw with the output voltage Vout at the turn-off moment of the synchronous switch tube MP.

[0049] Optionally, the positive and negative input terminals of the comparator 240 are respectively connected to the first terminal (ie, the switch node SW) and the second terminal (ie, the output terminal of the switching converter 200) of the synchronous switch MP, and the output terminal provides a comparison signal Q. Therefore, when Vsw>Vout, Q=1.

[0050] Optionally, the comparator 240 compares the voltage Vsw with the output voltage Vout in the high voltage domain of Vout-5V to Vout, and converts the comparison result through an internal level converter to obtain a comparison signal Q in the low voltage domain.

[0051] The on-time control circuit 250 is connected to the output terminal of the comparator 240 and is used to generate an on-time control signal T according to the comparison signal Q. <n:0>and provides it to the adjustable delay circuit 260 to control the conduction time of the synchronous switch MP.

[0052] The adjustable delay circuit 260 is used to control the on-time signal T <n:0>Adjust the conduction time of the synchronous switch MP in each switching cycle. The adjustable delay circuit 260 includes a delay capacitor 263 and a current source 261 for charging the delay capacitor 263. The adjustable delay circuit 260 is used to control the synchronous switch MP to turn off when the voltage of the delay capacitor 263 is charged to a set threshold value, so as to control the conduction time of the synchronous switch MP in each switching cycle. In addition, the adjustable delay circuit 260 is also used to control the conduction time of the synchronous switch MP according to the conduction time control signal T <n:0>The capacitance value of the delay capacitor 263 is adjusted to adaptively adjust the conduction time of the synchronous switch tube MP in each switching cycle. The charging current I provided by the current source 261 changes with the voltage difference between the preset output voltage Vout1 and the input voltage Vin. The capacitance value of the delay capacitor 263 needs to be adjusted before the main switch tube MN is turned off.

[0053] The on-time control circuit 250 is also used to perform an up-down counting operation according to the level state of the comparison signal Q in each switching cycle to generate an on-time control signal T <n:0>.

[0054] Figure 4 A circuit diagram of a conduction time control circuit according to an embodiment of the present invention is shown.

[0055] See also Figure 4 The on-time control circuit 250 includes a D flip-flop 252 and an up-down counter 255 .

[0056] The D flip-flop 252 is used to sample and hold the comparison signal Q in each switching cycle to obtain a trigger signal Q1 corresponding to the level state of the comparison signal Q. The D flip-flop 252 has an input terminal D, a clock terminal Clk, a reset terminal Reset, and an output terminal Q. The input terminal D receives the comparison signal Q, the clock terminal Clk receives the clock signal clk_q, the reset terminal Reset receives the enable signal en_auto, and the output terminal Q provides a trigger signal Q1. The enable signal en_auto is an enable signal of the zero-crossing detection circuit.

[0057] The up / down counter 255 is used to perform up / down operations according to the value of the trigger signal Q1 in each switching cycle to adjust the on-time control signal T <n:0>For example, if the value of the current switching cycle trigger signal Q1 is 1, the up-down counter 255 controls the on-time control signal T of the previous switching cycle. <n:0>Perform an add 1 operation to obtain the on-time control signal T of the current switching cycle <n:0>If the value of the trigger signal Q1 in the current switching cycle is 0, the up-down counter 255 controls the on-time control signal T of the previous switching cycle. <n:0>Subtract 1 to obtain the on-time control signal T of the current switching cycle. <n:0>Optionally, the on-time control signal T <n:0>It is composed of n+1 (n>0) bits of binary digital signal. Without considering the influence of other factors, the conduction time control signal T <n:0>The larger the value of is, the longer the conduction time of the synchronous switch MP is. The up-down counter 255 also receives an enable signal en_auto.

[0058] The on-time control circuit 250 further includes a delay circuit 251 , a counting control module 253 and a SAR logic circuit 254 .

[0059] The delay circuit 251 is used to control the working sequence of the D flip-flop 252, the counting control module 253, the SAR logic circuit 254 and the up-down counter 255 in each switching cycle. Specifically, the delay circuit 251 delays the clock signal clk differently to obtain the clock signal clk_q, the clock signal clk_check, the clock signal clk_SAR and the clock signal clk_count, and provides the clock signal clk_q, the clock signal clk_check, the clock signal clk_SAR and the clock signal clk_count to the D flip-flop 252, the counting control module 253, the SAR logic circuit 254 and the up-down counter 255, respectively.

[0060] The SAR logic circuit 254 is used to provide a logic digital signal B to the up-down counter 255 when the zero-crossing detection circuit cannot complete the calibration of the turn-off time of the synchronous switch tube MP through the up-down counter 255 within the set time (that is, the synchronous switch tube MP cannot be turned off at the zero-crossing point of the inductor current IL within the set period). <n:0>, so that the up-down counter 255 directly converts the logic digital signal B <n:0>The output is the on-time control signal T <n:0>.

[0061] The counting control module 253 is used to count the number of times the trigger signal Q1 is continuously at the same level in multiple consecutive switching cycles (i.e., count the number of times the trigger signal Q1 is continuously 0 or 1) to obtain a count value, and obtain a counting enable signal en_SAR according to the count value. The counting enable signal en_SAR is used to control the working state of the add-subtract counter 255 and the SAR logic circuit 254. When the counting enable signal en_SAR is in the second level state, the add-subtract counter 255 works in the add-subtract counting mode, and the SAR logic circuit does not work; when the counting enable signal en_SAR is in the first level state, the add-subtract counter 255 works in the pass-through mode, and the SAR logic circuit 254 works normally. When the add-subtract counter 255 works in the add-subtract counting mode, it performs addition and subtraction operations according to the value of the trigger signal Q1 in each switching cycle to adjust the on-time control signal T <n:0>When the add-subtract counter 255 works in the direct mode, the add-subtract counter 255 directly converts the logic digital signal B <n:0>The output is the on-time control signal T <n:0>.

[0062] Optionally, the count control module 253 uses the first count value and the second count value to count the number of times the trigger signal Q1 is continuously at the first level and the second level respectively. Specifically, in the current switching cycle, if the trigger signal Q1 is at the first level, the first count value is increased by 1, and the second count value is reset to 0. If the trigger signal Q1 is at the second level, the first count value is reset to 0, and the second count value is increased by 1. For example, when the first count value and the second count value are both less than the preset value Y, the count enable signal en_SAR is at the second level. When the first count value or the second count value is greater than or equal to the preset value Y (Y>1), it indicates that the zero-crossing detection circuit cannot complete the calibration of the turn-off moment of the synchronous switch tube MP through the add-subtract counter 255 within Y cycles. At this time, the count enable signal en_SAR is at the first level. Among them, the first level is, for example, a high level (i.e., 1), and the second level is, for example, a low level (i.e., 0). After the counting enable signal en_SAR is flipped from the second level to the first level, the counting control module 253 allows the counting enable signal en_SAR to continue to maintain the first level until it receives the reset signal reset_chk.

[0063] The counting control module 253 is further configured to reset the counting value to 0 when receiving a reset signal reset_chk, that is, to reset both the first counting value and the second counting value to 0.

[0064] After the SAR logic circuit 254 is started, the logic digital signal B <n:0>Reset, and then convert the trigger signal Q1 in the next n+1 consecutive switching cycles into a logical digital signal B through the successive approximation algorithm <n:0>, and outputs a reset signal reset_chk to the counting control module 253 after the conversion is completed. The SAR logic circuit 254 also outputs a corresponding logic digital signal B in each switching cycle of the consecutive n+1 switching cycles. <n:0>To up-down counter 255.

[0065] Figure 5 FIG. 4 is a schematic diagram showing the operation of a SAR logic circuit according to an embodiment of the present invention.

[0066] Combine the following Figure 5 The working principle of the SAR logic circuit 254 is described. The SAR logic circuit 254 is started when the count enable signal en_SAR is flipped from the second level to the first level. After starting, the logic digital signal B <n:0>reset and the logic digital signal B <n:0>The highest bit n is set to 1, and the highest bit n is set to 1 and the remaining bits are set to 0. <n:0>Output to the up-down counter 255; if the next switching cycle trigger signal Q1 is 1, the logic digital signal B is determined <n:0>The highest bit of is 1. If the trigger signal Q1 is 0 in the next switching cycle, the logic digital signal B is determined. <n:0>The highest bit of the logic digital signal B is 0. <n:0>The second highest bit is set to 1, and the highest bit is x (x represents the value of the highest bit previously determined), the second highest bit is 1, and the remaining bits are 0. <n:0>Output to the up-down counter 255; repeat the above process, after n+1 cycles, the logic digital signal B <n:0>All bits of are determined, the successive approximation operation is completed, and the SAR logic circuit 254 outputs a reset signal reset_chk.

[0067] Optionally, the effective edge of the clock signal clk is synchronized with the turn-off time of the synchronous switch MP; the effective edge of the clock signal clk_q has a certain delay relative to the effective edge of the clock signal clk, so as to ensure that the D flip-flop 252 samples the comparison signal Q only after the comparator 240 outputs the comparison signal Q in each switching cycle; the effective edge of the clock signal clk_check has a certain delay relative to the effective edge of the clock signal clk_q, so as to ensure that the counting control module 253 counts the trigger signal Q1 only after the trigger signal Q1 is stable; the effective edge of the clock signal clk_SAR has a certain delay relative to the effective edge of the clock signal clk_check, so as to ensure that the SAR logic circuit 254 performs a successive approximation operation only after the counting enable signal en_SAR is output. The clock signal clk_count has a certain delay relative to the clock signal clk_SAR, so as to ensure that the up-down counter 255 starts working only after the SAR logic circuit 254 or the counting control module 253 completes the work of the current switching cycle.

[0068] Figure 6 A circuit diagram of an adjustable delay circuit according to an embodiment of the present invention is shown.

[0069] See also Figure 6 The adjustable delay circuit 260 further includes a voltage comparison module 262, an output module 264, a control signal generation module 265 and switch tubes M1-M5.

[0070] The current source 261 is used to receive the adjustment signal Vo_sel <m:0>, and adjust Vo_sel according to <m:0>Generates a charging current I. Among them, the adjustment signal Vo_sel <m:0>The preset output voltage Vout1 is related to the preset output voltage Vout1, which can be obtained by register selection, for example, and the preset output voltage Vout1 represents the output voltage expected by the switching converter 200. The charging current I is related to the voltage difference between the preset output voltage Vout1 and the input voltage Vin. The expression of the calibration accuracy of the charging current I is: , in, represents the calibration accuracy of the charging current I, k represents the slope of the inductor current when the synchronous switch tube MP is turned on, L represents the inductance value of the inductor L, Vout1 represents the preset output voltage, Vin represents the input voltage of the switching converter 200, Indicates the calibration step of the conduction time of the synchronous switch MP.

[0071] The relationship between the charging time t, the capacitance C of the delay capacitor 263, the voltage V of the delay capacitor 263 and the charging current I is: .

[0072] The switch tubes M4 and M2 are sequentially connected between the current source 261 and the charging path of the delay capacitor 263. The switch tubes M4 and M2 are used to turn on the charging path at the turn-on time of the synchronous switch tube MP, so as to output the first voltage signal Va at the first node between the switch tubes M4 and M2. The control end of the switch tube M4 receives the driving signal Lg_drv, and the control end of the switch tube M2 receives the control signal Vp.

[0073] The voltage comparison module 262 is connected to the first node, and is used to compare the first voltage signal Va with a set threshold value to obtain a comparison signal Vb according to the comparison result.

[0074] The output module 264 is used to generate a zero-crossing detection signal ZCD according to the comparison signal Vb and the drive signal Lg_drv. Specifically, the output module 264 is used to perform an AND operation on the inverted signal of the comparison signal Vb and the inverted signal of the drive signal Lg_drv to obtain the zero-crossing detection signal ZCD. When the voltage of the delay capacitor 263 is charged to a set threshold, the zero-crossing detection signal ZCD controls the synchronous switch tube MP to turn off.

[0075] The switch tube M5 is connected between the power supply voltage AVDD and the first node, and the control terminal of the switch tube M5 receives the control signal Vp. The switch tube M5 is used to be turned on when the first voltage signal Va rises to a set threshold to maintain the potential of the first node at the power supply voltage AVDD.

[0076] The switch tube M3 is connected between two ends of the delay capacitor 263, and the control end of the switch tube M3 receives the control signal Vpb. The switch tube M3 is used to be turned on when the first voltage signal Va rises to a set threshold value to reset the voltage of the delay capacitor 263.

[0077] The control signal generating module 265 is used to generate a control signal Vpb and a control signal Vp that is inverted from the control signal Vpb according to the comparison signal Vb and the drive signal Lg_drv. Specifically, the control signal generating module 265 is used to perform a non-OR operation on the comparison signal Vb and the drive signal Lg_drv to obtain the control signal Vpb, and invert the control signal Vpb to obtain the control signal Vp. Among them, the control signal Vpb is at a high level only when the comparison signal Vb is flipped to a low level and the drive signal Lg_drv has not flipped from a low level to a high level, that is, it is at a high level only during the dead time between the turn-off moment of the synchronous switch tube MP and the turn-on moment of the main switch tube MN.

[0078] The switch tube M1 is connected between the first voltage signal Va and the ground end. The control end of the switch tube M1 receives the driving signal Lg_drv. The switch tube M1 is used to be turned on when the main switch tube MN is turned on to reset the voltage of the first node.

[0079] Specifically, the voltage comparison module 262 includes a current source 262a and a transistor M6 which are sequentially connected between the power supply voltage AVDD and the ground terminal, wherein the control terminal of the transistor M6 receives the first voltage signal Va, the output terminal of the current source 262a provides a bias current Ibias, and the intermediate node between the transistor M6 and the current source 262a provides a comparison signal Vb. The set threshold is the threshold voltage Vth6 of the transistor M6. The working principle of the voltage comparison module 262 is that when the first voltage signal Va does not reach the set threshold Vth6, the transistor M6 is turned off, and the current source 262a pulls the comparison signal Vb up to the power supply voltage AVDD, and when the first voltage signal Va reaches the set threshold Vth6, the transistor M6 is turned on to pull the comparison signal Vb down to the ground voltage.

[0080] The delay capacitor 263 includes a capacitor C connected in parallel FIX and switched capacitor array 263a, where capacitor C FIX The capacitance value of the switch capacitor array 263a is fixed, and the capacitance value of the switch capacitor array 263a follows the conduction time control signal T <n:0>The switch capacitor array 263a includes n+1 capacitor branches, and the first capacitor branch to the n+1th capacitor branch are respectively controlled by the conduction time control signal T <n:0>The lowest to highest bit control, selectively with capacitor C FIX Each capacitor branch includes a switch and a capacitor connected in series, and the capacitance values ​​of the capacitors from the first capacitor branch to the n+1th capacitor branch are 2 0 C0,2 1 C0……2 n C0. The voltage at the first terminal of the delay capacitor 263 is the voltage of the delay capacitor 263. The calibration step length of the conduction time of the synchronous switch tube MP The calibration accuracy of the charging current I is related to the set threshold Vth6, the unit capacitance value C0 and the charging current I. It can also be expressed as:

[0081] Where, L represents the inductance value of the inductor, g fsw represents a coefficient positively correlated with the switching frequency of the main switch tube MN, C0 represents the unit capacitance value of the switch capacitor array 263a, and V represents the set threshold value Vth6.

[0082] The output module 264 includes a NOT gate 264a, a NOT gate 264b and an AND gate 264c. The input end of the NOT gate 264a receives the comparison signal Vb. The input end of the NOT gate 264b receives the drive signal Lg_drv. The first input end of the AND gate 264c is connected to the output end of the NOT gate 264b, the second input end of the AND gate 264c is connected to the output end of the NOT gate 264a, and the output end of the AND gate 264c provides a zero crossing detection signal ZCD.

[0083] The control signal generating module 265 includes a NOT gate 265a, a NOR gate 265b and a NOT gate 265c. The input end of the NOT gate 265a is connected to the output end of the NOT gate 264a. The first input end of the NOR gate 265b is connected to the output end of the NOT gate 265a, the second input end receives the driving signal Lg_drv, and the output end provides the control signal Vpb. The input end of the NOT gate 265c receives the control signal Vpb, and the output end provides the control signal Vp.

[0084] Figure 7 A timing diagram of an adjustable delay circuit according to an embodiment of the present invention is shown.

[0085] Combine the following Figure 7 The working principle of the adjustable delay circuit 260 is described. When the dead time is ignored, Figure 7 Taking the switching cycle T in the figure as an example, when the driving signal Lg_drv is turned to a high level, the main switch tube MN is turned on, the zero-crossing detection signal ZCD is at a low level, and the first voltage signal Va is pulled down to the ground voltage by the switch tube M1. When the driving signal Lg_drv is turned to a low level, that is, after the main switch tube MN is turned off, the zero-crossing detection signal ZCD remains at a low level, and the synchronous switch tube MP starts to turn on. The charging current I provided by the output end of the current source 261 charges the delay capacitor 263 through the switch tubes M4 and M2. The voltage value of the first voltage signal Va starts to rise. When the first voltage After the voltage value of the signal Va rises to the threshold voltage Vth6 of the transistor M6, the transistor M6 is turned on and the comparison signal Vb is pulled down to the ground voltage, so that the zero-crossing detection signal ZCD is flipped to a high level, and the synchronous switch tube MP is turned off. At the same time, the control signal Vpb is flipped to a high level, and the control signal Vp is flipped to a low level, so that the switch tube M5 is turned on to pull the first voltage signal Va to the power supply voltage AVDD, and the switch tube M3 is turned on to discharge the delay capacitor 263 to the ground voltage until the drive signal Lg_drv is flipped to a high level, and a new switching cycle is restarted.

[0086] Figure 8 FIG. 4 is a schematic diagram showing the operation of a zero-crossing detection circuit according to an embodiment of the present invention.

[0087] Combine the following Figure 8 The working principle of the zero-crossing detection circuit of the embodiment of the present invention is described as follows: at the moment when the synchronous switch tube MP is turned off, the comparator 240 compares the voltage across the synchronous switch tube MP, i.e., the voltage Vsw, and the output voltage Vout to obtain a comparison signal Q. When the comparison signal Q is 1, the on-time control circuit 250 adds 1 to the first count value and resets the second count value to 0. When the comparison signal Q is 0, the first count value is reset to 0 and the second count value is added to 1. At the same time, the counting enable signal en_SAR is output according to the first count value and the second count value, and it is determined whether the counting enable signal en_SAR is 0. If the counting enable signal en_SAR=0, the on-time control signal T is incremented by the up-down counter 255 when the comparison signal Q is 1. <n:0>Perform an addition operation, and when the comparison signal Q is 0, the conduction time control signal T <n:0>If the count enable signal en_SAR=1, the SAR logic circuit 254 is started, and the SAR logic circuit 254 performs a successive approximation operation on the comparison signal Q1 in the next n+1 switching cycles. The SAR logic circuit 254 also outputs a corresponding logic digital signal B in each switching cycle. <n:0>As the on-time control signal T <n:0>, and the adjustable delay circuit 260 turns off the synchronous switch tube MP after a preset time delay after the main switch tube MN is turned off to enter the next switching cycle.

[0088] Optionally, the switch tubes M1 - M3 and the transistor M6 are NMOS tubes (N-channel Metal-Oxide-Semiconductor), and the switch tubes M4 and M5 are PMOS tubes (P-channel Metal-Oxide-Semiconductor).

[0089] The switching converter and its zero-crossing detection circuit provided by the embodiment of the present invention, the comparator compares the voltage of the switching node with the output voltage of the switching converter to obtain a first comparison signal according to the comparison result; the on-time control circuit generates an on-time control signal according to the first comparison signal; the adjustable delay circuit is used to adjust the on-time length of the synchronous switch tube in each switching cycle according to the on-time control signal, thereby improving the light-load efficiency of the switching converter.

[0090] Furthermore, by setting a counting control module and a SAR logic circuit in the on-time control circuit, the switching converter can be quickly switched between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) when the load current suddenly changes, so that the switching converter can quickly enter a stable state.

[0091] Furthermore, the adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor. The adjustable delay circuit controls the synchronous switch tube to turn off when the voltage of the delay capacitor is charged to a set threshold value. By setting the charging current provided by the first current source to be related to the voltage difference between the preset output voltage and the input voltage, the zero-crossing detection circuit can maintain the same accuracy under different preset output voltages, thereby achieving precise shutdown of the synchronous switch tube at the zero-crossing point of the inductor current, thereby further improving the light-load efficiency of the switching converter.

[0092] It is understandable that the present invention further provides a chip including the switching converter 200 described above.

[0093] It is understandable that the present invention also provides a display device, including a display panel for displaying images, a driving circuit for controlling the display state of the display panel, and the switching converter 200 as described above. The switching converter 200, for example, provides a stable power supply for the display device.

[0094] The present invention also provides a zero-crossing detection method for a switching converter, specifically referring to FIG. Fig. 9 , the zero-crossing detection method comprises the following steps: S1: comparing the voltage of the switch node with the output voltage of the switching converter to obtain a first comparison signal according to the comparison result; S2: Generate an on-time control signal according to the first comparison signal; S3: Controlling the synchronous switch tube to turn off according to the on-time control signal.

[0095] Furthermore, step S3 also includes: The capacitance value of the delay capacitor is adjusted according to the conduction time control signal; the delay capacitor is charged by a charging current during the conduction phase of the synchronous switch tube, and the synchronous switch tube is controlled to be turned off when the voltage of the delay capacitor is charged to a set threshold.

[0096] The charging current is related to the voltage difference between the preset output voltage and the input voltage.

[0097] Step S2 also includes: Sampling and holding the first comparison signal to obtain a trigger signal; Counting the number of times the trigger signal is continuously at the same level in a plurality of consecutive switching cycles to obtain a count value, and outputting a count enable signal according to the count value; When the counting enable signal is at the second level, performing addition and subtraction operations according to the value of the trigger signal to obtain a conduction time control signal, and When the counting enable signal is flipped from the second level to the first level, the logic digital signal is reset, and the trigger signal in a plurality of consecutive switching cycles is converted into a logic digital signal through a successive approximation algorithm, and the counting value is reset after the conversion is completed, and the corresponding logic digital signal is output as a conduction time control signal in each switching cycle of the plurality of switching cycles.

[0098] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A zero-crossing detection circuit for a switching converter, the switching converter comprising a main switch tube and a synchronous switch tube, a common node of the main switch tube and the synchronous switch tube being a switch node, the zero-crossing detection circuit comprising: a comparator, configured to compare the voltage of the switch node with the output voltage of the switch converter, so as to obtain a first comparison signal according to the comparison result; a conduction time control circuit, configured to generate a conduction time control signal according to the first comparison signal; The adjustable delay circuit is used to adjust the conduction time of the synchronous switch tube in each switching cycle according to the conduction time control signal.

2. The zero-crossing detection circuit according to claim 1, wherein: The adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor. The adjustable delay circuit is used to control the synchronous switch tube to turn off when the voltage of the delay capacitor is charged to a set threshold value, so as to control the conduction time of the synchronous switch tube in each switching cycle. The adjustable delay circuit is further used to adjust the capacitance value of the delay capacitor according to the on-time control signal, so as to adaptively adjust the on-time of the synchronous switch tube in each switching cycle.

3. The zero-crossing detection circuit according to claim 2, wherein: The on-time control circuit is used to perform addition and subtraction counting operations according to the level state of the first comparison signal in each switching cycle to generate the on-time control signal.

4. The zero-crossing detection circuit according to claim 3, wherein: The on-time control circuit comprises: A D flip-flop, used for sampling and holding the first comparison signal in each switching cycle to obtain a trigger signal corresponding to a level state of the first comparison signal; The up-down counter is used to perform an up-down operation according to the value of the trigger signal in each switching cycle to adjust the value of the on-time control signal.

5. The zero-crossing detection circuit according to claim 4, wherein: The on-time control circuit further includes: The SAR logic circuit is used to provide a logic digital signal to the add-subtract counter when the zero-crossing detection circuit cannot complete the calibration of the turn-off moment of the synchronous switch tube through the add-subtract counter within a set time, so that the add-subtract counter directly outputs the logic digital signal as the turn-on time control signal.

6. The zero-crossing detection circuit according to claim 5, wherein: The on-time control circuit further includes: a counting control module, used for counting the number of times the trigger signal is continuously at the same level in a plurality of consecutive switching cycles to obtain a count value, and obtaining a counting enable signal according to the count value, wherein the counting enable signal is used to control the working state of the up-down counter and the SAR logic circuit, When the counting enable signal is in the first level state, the up-down counter is in the pass-through mode, and the SAR logic circuit works. When the counting enable signal is in the second level state, the up-down counter is in the up-down counting mode, and the SAR logic circuit does not work.

7. The zero-crossing detection circuit according to claim 1, wherein: The comparator is a dynamic comparator, which compares the voltage of the switch node with the output voltage of the switch converter at the turn-off moment of the synchronous switch tube to obtain the first comparison signal according to the comparison result.

8. The zero-crossing detection circuit according to claim 6, wherein: The counting control module uses the first counting value and the second counting value to count the number of times that the trigger signal is continuously at the first level and the second level respectively, and when one of the counting values ​​is increased by 1, the other counting value is reset, and when the first counting value or the second counting value is greater than or equal to a preset value, the counting enable signal is flipped from the second level to the first level; The SAR logic circuit converts the trigger signal in a plurality of consecutive switching cycles into a logic digital signal through a successive approximation algorithm, and outputs a reset signal to the counting control module after the conversion is completed, and further outputs a corresponding logic digital signal to the up-down counter in each switching cycle of the plurality of switching cycles; The counting control module is further configured to reset the counting value after receiving the reset signal.

9. The zero-crossing detection circuit according to claim 1, wherein: The adjustable delay circuit also includes: A first switch tube and a second switch tube are connected in sequence between the first current source and the charging path of the delay capacitor, and the first switch tube and the second switch tube turn on the charging path when the synchronous switch tube is turned on, so as to output a first voltage signal at a first node between the first switch tube and the second switch tube; a voltage comparison module, connected to the first node, and configured to compare the first voltage signal with the set threshold value to obtain a second comparison signal according to the comparison result; an output module, configured to generate a zero-crossing detection signal according to the second comparison signal and the driving signal of the main switch tube, When the voltage of the delay capacitor is charged to a set threshold, the zero-crossing detection signal controls the synchronous switch tube to be turned off.

10. The zero-crossing detection circuit according to claim 9, wherein: The adjustable delay circuit also includes: a third switch tube, connected between the power supply voltage and the first node, the third switch tube being turned on when the first voltage signal rises to the set threshold value, so as to maintain the voltage of the first node at the power supply voltage; a fourth switch tube, connected between two ends of the delay capacitor, the fourth switch tube being configured to be turned on when the first voltage signal rises to the set threshold value, so as to reset the voltage of the delay capacitor; A fifth switch tube is connected between the first node and a ground terminal, and is used for being turned on when the main switch tube is turned on to reset the voltage of the first node.

11. The zero-crossing detection circuit according to claim 10, wherein: The adjustable delay circuit also includes: a control signal generating module, configured to perform a non-OR operation on the second comparison signal and the driving signal of the main switch tube to obtain a first control signal, and invert the first control signal to obtain a second control signal, wherein the first control signal is provided to the control end of the fourth switch tube, and the second control signal is provided to the control ends of the second switch tube and the third switch tube; The output module is used for performing an AND operation on the inverted signal of the second comparison signal and the inverted signal of the driving signal of the main switch tube to obtain the zero-crossing detection signal.

12. The zero-crossing detection circuit according to claim 11, wherein: The charging current provided by the first current source to the delay capacitor is related to a voltage difference between a preset output voltage and an input voltage.

13. The zero-crossing detection circuit according to claim 12, wherein: The first current source receives a regulation signal related to a preset output voltage, and generates the charging current according to the regulation signal; The voltage comparison module comprises: A second current source and a first transistor are connected between a power supply voltage and a ground terminal in sequence, a control terminal of the first transistor receives the first voltage signal, the second current source provides a bias current, an intermediate node between the second current source and the first transistor provides the second comparison signal, and the set threshold is equal to a threshold voltage of the first transistor; The delay capacitor comprises: A first capacitor and a switch capacitor array connected in parallel, the switch capacitor array includes a plurality of capacitor branches with the same number of bits as the on-time control signal, the first to the last capacitor branches are controlled in sequence by the lowest bit to the highest bit of the on-time control signal, and are selectively connected in parallel with the first capacitor.

14. A zero-crossing detection method for a switching converter, the switching converter comprising a main switch tube and a synchronous switch tube, a common node of the main switch tube and the synchronous switch tube being a switch node, the zero-crossing detection method comprising: Comparing the voltage of the switch node with the output voltage of the switch converter to obtain a first comparison signal according to the comparison result; generating an on-time control signal according to the first comparison signal; The synchronous switch tube is controlled to be turned off according to the conduction time control signal.

15. The zero-crossing detection method according to claim 14, wherein: Controlling the synchronous switch tube to turn off according to the conduction time control signal comprises: The capacitance value of the delay capacitor is adjusted according to the on-time control signal, the delay capacitor is charged by a charging current during the on-phase of the synchronous switch tube, and the synchronous switch tube is controlled to be turned off when the voltage of the delay capacitor is charged to a set threshold.

16. The zero-crossing detection method according to claim 14, wherein: Generating a conduction time control signal according to the first comparison signal comprises: Sampling and holding the first comparison signal to obtain a trigger signal corresponding to a level state of the first comparison signal; Counting the number of times the trigger signal is continuously at the same level in a plurality of consecutive switching cycles to obtain a count value, and outputting a count enable signal according to the count value; When the counting enable signal is at the second level, performing addition and subtraction operations according to the value of the trigger signal to obtain a conduction time control signal, and When the counting enable signal is flipped from the second level to the first level, the trigger signal in a plurality of consecutive switching cycles is converted into a logic digital signal through a successive approximation algorithm, and the counting value is reset after the conversion is completed, and the corresponding logic digital signal is output as a conduction time control signal in each switching cycle of the plurality of switching cycles.

17. The zero-crossing detection method according to claim 15, wherein: The charging current is related to a voltage difference between a preset output voltage and an input voltage.

18. A switching converter comprising: A main switch tube and a synchronous switch tube, wherein the intermediate node between the main switch tube and the synchronous switch tube is a switch node; an inductor connected to the switch node; A first driving unit, used to generate a first driving signal according to a first switch control signal to drive the main switch tube to be turned on and off; A second driving unit, used to generate a second driving signal according to a second switch control signal to drive the synchronous switch tube to be turned on and off; a PWM logic control circuit, configured to provide the first switch control signal and the second switch control signal to the first drive unit and the second drive unit respectively; as well as The zero-crossing detection circuit according to any one of claims 1 to 13, configured to provide the zero-crossing detection signal to the second driving unit.

19. A chip comprising the switching converter according to claim 18.

20. A display device, comprising: A display panel, used for displaying images; A driving circuit, used for controlling the display state of the display panel; as well as A switching converter as claimed in any one of claims 1 to 13.

Images