Cascaded Doherty power amplifier

Abstract

A main amplifier and an auxiliary amplifier respectively comprise a pre-stage driving amplifier and a final-stage amplifier, the pre-stage driving amplifier and the final-stage amplifier are connected through an input matching circuit, and the final-stage amplifier is connected with an output matching circuit. The main path output matching circuit is connected with the auxiliary path matching amplifier through a delay line, the pre-stage driving amplifier comprises a first transistor, the final-stage amplifier comprises a second transistor, the first transistor and the second transistor are integrated on a wafer, and grid electrodes and drain electrodes of the first transistor and the second transistor are arranged in a staggered mode. The grid electrode of the first transistor and the drain electrode of the second transistor are arranged on the same side of the wafer, the drain electrode of the first transistor and the grid electrode of the second transistor are arranged on the other side of the wafer, the first transistor and the second transistor are in an isolated state, and the first transistor and the second transistor have the same technological parameters. And the phase also has high consistency, and the cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of Doherty power amplifiers, and in particular relates to a cascaded Doherty power amplifier. Background Art

[0002] The RF power amplifier is a key component at the end of the transmitter in the communication base station system. The efficiency of the power amplifier plays a great role in system power consumption and heat dissipation. Especially in the 5G system, the Massive MIMO architecture has put forward higher requirements on system power consumption and device size, so improving the efficiency of the power amplifier has become an increasingly important indicator in the design.

[0003] Doherty amplifier is a common method to improve the efficiency of power amplifier. In order to further improve the overall efficiency of cascade power amplifier, the single final Doherty can be changed to cascade Doherty. Figure 1 As shown in FIG. 1 , the principle of cascade Doherty is to first cascade a single driver amplifier and a single final amplifier to form a high-gain single-channel power amplifier, and then synthesize the two high-gain single-channel amplifiers using a Doherty circuit. In this way, since the gain of a single final amplifier is relatively high, the output power of a single driver amplifier will be reduced. At the same time, since the other driver amplifier works in a high-efficiency Class C state, the power consumed by the entire driver amplifier is greatly reduced. This improves the overall efficiency of the cascade power amplifier.

[0004] However, such a cascaded Doherty amplifier has the following disadvantages: 1. The process parameters of the driving power amplifier and the final power amplifier are often different, such as threshold voltage, transconductance, and gate-drain parasitic parameters per unit size. This causes fluctuations in the performance of the cascade circuit, which is more obvious in the Doherty combiner, thus affecting the consistency of the product.

[0005] 2. The difference in threshold voltages between the driving power amplifier and the final power amplifier requires separate power supply circuits to achieve different power supply voltages, which greatly increases the complexity of the circuit. Summary of the invention

[0006] In view of the above-mentioned technical problems, the purpose of the present invention is to provide a cascaded Doherty power amplifier, in which the driving transistor and the final-stage transistor are integrated on a chip, the gate and the drain of the driving transistor and the final-stage transistor are alternately placed, and the driving transistor and the final-stage transistor are in an isolated state. The driving transistor and the final-stage transistor have the same process parameters and the phases are highly consistent, which reduces the cost and improves the overall efficiency of the cascade power amplifier.

[0007] In order to solve these problems in the prior art, the technical solution provided by the present invention is: A cascaded Doherty power amplifier comprises a main amplifier and at least one auxiliary amplifier, wherein the main amplifier and the auxiliary amplifier respectively comprise a pre-stage driver amplifier and a final amplifier, wherein the pre-stage driver amplifier comprises a driving input matching circuit, wherein the pre-stage driver amplifier and the final amplifier are connected via an input matching circuit, wherein the final amplifier is connected to an output matching circuit, wherein the main output matching circuit is connected to the auxiliary matching amplifier via a delay line, wherein the pre-stage driver amplifier comprises a first transistor, wherein the final amplifier comprises a second transistor, wherein the first transistor and the second transistor are integrated on a wafer, wherein the gate and the drain of the first transistor and the second transistor are alternately arranged, wherein the gate of the first transistor and the drain of the second transistor are on the same side of the wafer, wherein the drain of the first transistor and the gate of the second transistor are on the other side of the wafer, wherein the first transistor and the second transistor are in an isolated state, and wherein the first transistor and the second transistor have the same process parameters.

[0008] In a preferred technical solution, an isolation ground hole is provided between the first transistor and the second transistor on the chip.

[0009] In a preferred technical solution, the first transistor adopts a multi-unit structure, and the gate is connected to a damping resistor.

[0010] In a preferred technical solution, the gate power supplies of the first transistor and the second transistor are respectively connected to the same pin after passing through an input matching circuit and a driving input matching circuit.

[0011] In the preferred technical solution, the gate of the first transistor of the main path and the gate of the first transistor of the auxiliary path are respectively connected to the main path drive input matching circuit and the auxiliary path drive input matching circuit, the main path drive input matching circuit and the auxiliary path drive input matching circuit are connected to the input power divider, and the connection point between the auxiliary path output matching circuit and the output delay line serves as the final signal output end.

[0012] In a preferred technical solution, the electrical length of the delay line is adjusted according to the electrical length of the output impedance of the second transistor of the main path and the electrical length of the main path output matching circuit, and the electrical length of the delay line, the output impedance equivalent electrical length of the second transistor of the main path and the electrical length of the main path output matching circuit add up to an integer multiple of 90 degrees.

[0013] In a preferred technical solution, the sum of the equivalent electrical length of the output impedance of the second transistor of the auxiliary path and the electrical length of the auxiliary path output matching circuit is an integer multiple of 180 degrees.

[0014] In the preferred technical solution, the main input matching circuit is implemented by a first integrated passive device, the main output matching circuit and the delay line are implemented by a second integrated passive device, the auxiliary input matching circuit is implemented by a third integrated passive device, the auxiliary output matching circuit is implemented by a fourth integrated passive device, the input power divider, the main drive input matching circuit and the auxiliary drive input matching circuit are implemented by a fifth integrated passive device, all the integrated passive devices and the main chip and the auxiliary chip integrating the first transistor and the second transistor are placed on the packaging base, and the fifth integrated passive device is located in the middle of the first integrated passive device and the third integrated passive device, and is located in the middle of the main chip and the auxiliary chip.

[0015] In the preferred technical solution, the gate of the second transistor of the main path is connected to the first integrated passive device through the first bonding wire group, the drain of the first transistor of the main path is connected to the first integrated passive device through the second bonding wire group, the drain of the second transistor of the main path is connected to the second integrated passive device through the third bonding wire group, the gate of the first transistor of the main path is connected to the fifth integrated passive device through the fourth bonding wire group, the gate of the second transistor of the auxiliary path is connected to the third integrated passive device through the seventh bonding wire group, the drain of the first transistor of the auxiliary path is connected to the third integrated passive device through the eighth bonding wire group, the drain of the second transistor of the auxiliary path is connected to the fourth integrated passive device through the sixth bonding wire group, the gate of the first transistor of the auxiliary path is connected to the fifth integrated passive device through the fifth bonding wire group, the first integrated passive device is connected to the fifth integrated passive device through the tenth bonding wire group, and the third integrated passive device is connected to the fifth integrated passive device through the ninth bonding wire group. The wire group is connected to the fifth integrated passive device, the second integrated passive device is connected to the fourth integrated passive device through the thirteenth bonding wire group, the input signal pin is connected to the fifth integrated passive device through the eleventh bonding wire group, the output signal pin is connected to the second integrated passive device through the twelfth bonding wire group, the main path gate power supply pin is connected to the first integrated passive device through the fourteenth bonding wire group, the auxiliary path gate power supply pin is connected to the third integrated passive device through the sixteenth bonding wire group, the main path second transistor drain power supply pin is connected to the second integrated passive device through the fifteenth bonding wire group, the main path first transistor drain power supply pin is connected to the first integrated passive device through the eighteenth bonding wire group, the auxiliary path second transistor drain power supply pin is connected to the fourth integrated passive device through the seventeenth bonding wire group, and the auxiliary path first transistor drain power supply pin is connected to the third integrated passive device through the nineteenth bonding wire group.

[0016] Compared with the solutions in the prior art, the advantages of the present invention are: 1. The efficiency of the cascade Doherty can be greatly improved compared to the traditional Class AB plus Doherty final stage. Since the two cascade stages are integrated on the same chip, they have the same process parameters, such as threshold voltage, transconductance, and unit size gate drain parasitic parameters. As a result, the turn-on voltage of the two is completely consistent, and the phase is also highly consistent, so that the inconsistency problem of the cascade Doherty performance is properly solved.

[0017] 2. The consistency of gate voltage allows two levels of gate voltage to be powered by the same pin. Compared with the traditional solution, the number of gate voltage power supplies is reduced by half. This greatly improves the ease of use of cascaded Doherty, simplifies circuit layout, and saves costs.

[0018] 3. Since the two stages of the cascade are integrated on the same chip, the driver chip with less heat dissipation can also share the energy dissipation of the final stage output, which reduces the overall thermal resistance of the device to a certain extent.

[0019] 4. The layout method of placing the gate of the driver and the drain of the final stage on the same side and the drain of the driver and the gate of the final stage on the same side is adopted. This makes it unnecessary to cross the wires when the two-stage Doherty cascade is connected. This improves stability and greatly simplifies the circuit design.

[0020] 5. The problem that could only be solved by MMIC before is now solved by discrete transistors plus matching, further reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below in conjunction with the accompanying drawings and embodiments: Figure 1 A circuit architecture diagram of an existing cascade Doherty amplifier; Figure 2 A circuit diagram of a cascaded Doherty power amplifier according to a preferred embodiment of the present invention; Figure 3 is a schematic diagram of an integrated active transistor D1 of the present invention; Figure 4 is a schematic diagram of an integrated active transistor D2 of the present invention; Figure 5 It is a schematic diagram of an integrated active transistor wafer W1 of the present invention; Figure 6 A schematic diagram of a packaging structure of a cascaded Doherty power amplifier according to a preferred embodiment of the present invention. Implementation

[0022] The above scheme is further described below in conjunction with specific examples. It should be understood that these examples are used to illustrate the present invention and are not limited to the scope of the present invention. The implementation conditions adopted in the examples can be further adjusted according to the conditions of the specific manufacturer, and the unspecified implementation conditions are usually the conditions in conventional experiments.

[0023] Example

[0024] like Figure 2 As shown, a cascade Doherty power amplifier includes a main amplifier and at least one auxiliary amplifier, the main amplifier and the auxiliary amplifier respectively include a pre-stage driver amplifier and a final amplifier, the pre-stage driver amplifier includes a driving input matching circuit, the pre-stage driver amplifier and the final amplifier are connected through the input matching circuit, the final amplifier is connected to the output matching circuit, the main output matching circuit is connected to the auxiliary matching amplifier through a delay line, the pre-stage driver amplifier includes a first transistor, the final amplifier includes a second transistor, the first transistor and the second transistor are integrated on a chip, the gate and drain of the first transistor and the second transistor are alternately placed, the gate of the first transistor and the drain of the second transistor are on the same side of the chip, the drain of the first transistor and the gate of the second transistor are on the other side of the chip, the first transistor and the second transistor are in an isolated state, and the first transistor and the second transistor have the same process parameters.

[0025] The first transistor and the second transistor are integrated on a chip, and the whole can be called an integrated active transistor, including: a main integrated active transistor D1 and an auxiliary integrated active transistor D2.

[0026] Specifically, Figure 2 As shown, a cascade Doherty amplifier includes: a main integrated active transistor D1, an auxiliary integrated active transistor D2, a main input matching circuit IMM, a main output matching circuit OMM, an output delay line OL, an auxiliary input matching circuit IMP, an auxiliary output matching circuit OMP, a main drive input matching circuit DIMM, an auxiliary drive input matching circuit DIMP and an input power divider PD.

[0027] The integrated active transistor D1 integrates a first transistor T1 and a second transistor T2, and the power of the first transistor T1 is greater than or equal to the power of the second transistor T2. Generally, the first transistor is used as a final amplifier and the second transistor is used as a driving amplifier. The first transistor T1 and the second transistor T2 have the same process parameters, such as threshold voltage, transconductance, and unit size gate-drain parasitic parameters.

[0028] A preferred embodiment, such as Figure 3As shown, the unit structure of the first transistor T1 is similar to the unit structure of the second transistor T2. When the first transistor T1 adopts a multi-unit structure, a damping resistor R1 can be added to the gate to prevent loop oscillation formed by the multi-unit loop.

[0029] The integrated active transistor D2 integrates a fourth transistor T4 and a third transistor T3. The power of the fourth transistor T4 is greater than or equal to the power of the third transistor T3. The fourth transistor T4 and the third transistor T3 have the same process parameters, such as threshold voltage, transconductance, and unit size gate-drain parasitic parameters.

[0030] A preferred embodiment, such as Figure 4 As shown, the unit structure of the fourth transistor T4 is similar to the unit structure of the third transistor T3. When the fourth transistor T4 adopts a multi-unit structure, a damping resistor R2 can be added to the gate to prevent loop oscillation formed by the multi-unit loop.

[0031] The second transistor T1 and the first transistor T2 on the integrated active transistor D1 are in an isolated state with an isolation ground hole S1 disposed therebetween. The isolation ground hole S1 can ensure sufficient isolation between the second transistor T1 and the first transistor T2.

[0032] The fourth transistor T4 and the third transistor T3 on the integrated active transistor D2 are in an isolated state with an isolation ground hole S2 disposed therebetween. The isolation ground hole S2 can ensure sufficient isolation between the fourth transistor T4 and the third transistor T3.

[0033] The gate and drain of the second transistor T1 and the first transistor T2 on the integrated active transistor D1 are placed alternately, and the gate Gm of the second transistor T1 and the drain Dd1 of the first transistor T2 are on the same side. The drain Dm of the second transistor T1 and the gate Gd1 of the first transistor T2 are on the same side. The gate and drain of the second transistor T4 and the first transistor T3 on the integrated active transistor D2 are placed alternately, and the gate Gp of the second transistor T4 and the drain Dd2 of the first transistor T3 are on the same side. The drain Dp of the second transistor T4 and the gate Gd2 of the first transistor T3 are on the same side. The cascade connection of the first transistor and the second transistor on the same side can be realized.

[0034] Figure 5 The schematic diagram of the integrated active transistor D2 after processing on the same wafer W1. The wafer W1 is processed through multiple semiconductor processes. During this process, the second transistor T4 and the first transistor T3 in each independent active transistor D2 are almost in the same area of ​​the wafer, so they have the same process parameters, such as threshold voltage, transconductance, unit size gate drain parasitic parameters, etc.

[0035] The gate Gm of the second main transistor T1 and the drain Dd1 of the first main transistor T2 are connected to the main input matching circuit IMM. The function of the main input matching circuit IMM is to achieve inter-stage matching between the gate Gm of the second main transistor T1 and the drain Dd1 of the first main transistor T2, so that the first main transistor T2 can output sufficient power to drive the second main transistor T1.

[0036] The gate Gp of the auxiliary second transistor T4 and the drain Dd2 of the auxiliary first transistor T3 are connected to the auxiliary input matching circuit IMP. The auxiliary input matching circuit IMP has the function of matching the gate Gp of the auxiliary second transistor T4 and the drain Dd1 of the auxiliary first transistor T3 between stages, so that the auxiliary first transistor T3 can output sufficient power to drive the auxiliary second transistor T4.

[0037] The gate power supplies of the second transistor T1 of the main circuit and the first transistor T2 of the main circuit are connected to the same pin Vgs1 after passing through the main circuit gate-drain matching circuit IMM and the main circuit drive gate-drain matching circuit DIMM respectively. The gate power supplies of the second transistor T4 and the first transistor T3 of the auxiliary circuit are connected to the same pin Vgs2 after passing through the auxiliary circuit gate-drain matching circuit IMP and the auxiliary circuit drive gate-drain matching circuit DIMP respectively.

[0038] The gate Gd1 of the first transistor T2 of the main circuit is connected to the input matching circuit DIMM and the port 2 of the input power divider PD. The gate Gd2 of the first transistor T3 of the auxiliary circuit is connected to the port 4 of the input power divider PD after driving the input matching circuit DIMP through the auxiliary circuit. The port 1 of the input power divider PD is the isolation port. The port 3 of the input power divider PD is the signal input port Pin.

[0039] The drain Dm of the second transistor T1 of the main path is connected to one end of the main path output matching circuit OMM, and the other end of the main path output matching circuit OMM is connected to a delay line OL. The electrical length of the delay line OL is adjusted according to the output impedance of the second transistor T1 of the main path and the electrical length of the main path output matching circuit OMM. The principle of adjustment is to make the sum of the electrical length of the delay line OL, the electrical length equivalent to the output impedance of the second transistor T1 of the main path, and the electrical length of the main path output matching circuit OMM be an integer multiple of approximately 90 degrees.

[0040] The drain Dp of the auxiliary second transistor T4 is connected to the auxiliary output matching circuit OMP. The other end of the auxiliary output matching circuit OMP is connected to one end of the output delay line DL, and the connection point serves as the final signal drain Pout. The equivalent electrical length of the output impedance of the auxiliary second transistor T4 and the electrical length of the auxiliary output matching circuit OMP add up to an integral multiple of approximately 180 degrees.

[0041] In another embodiment, an example of the physical layout and implementation of the cascaded Doherty circuit of the present invention in a package is shown. Figure 6 As shown, the main input matching circuit IMM is implemented by the integrated passive device IPD1, the main output matching circuit OMM and the delay line OL are implemented by the integrated passive device IPD2, the auxiliary input matching circuit IMP is implemented by the integrated passive device IPD3, and the auxiliary output matching circuit OMP is implemented by the integrated passive device IPD4. The input power divider PD, the main drive input matching circuit DIMM and the auxiliary drive input matching circuit DIMP are all implemented on an integrated passive device IPD5. The integrated passive device IPD5 is located in the middle of the integrated passive device IPD1 and the integrated passive device IPD3, and is also located in the middle of the main integrated active transistor D1 and the auxiliary integrated active transistor D2. All integrated passive devices and integrated active transistors are placed on the package base F. The gate Gm of the second transistor T1 of the main path is connected to the integrated passive device IPD1 through the bonding wire group B1. The drain Dd1 of the small crystal T2 of the main path is connected to the integrated passive device IPD1 through the bonding wire group B2. The drain Dm of the second transistor T1 of the main circuit is connected to the integrated passive device IPD2 through the bonding wire group B3. The gate Gd1 of the small crystal T2 of the main circuit is connected to the integrated passive device IPD5 through the bonding wire group B4. The gate Gp of the second transistor T4 of the auxiliary circuit is connected to the integrated passive device IPD3 through the bonding wire group B7. The drain Dd2 of the small crystal T3 of the auxiliary circuit is connected to the integrated passive device IPD3 through the bonding wire group B8. The drain Dp of the second transistor T4 of the auxiliary circuit is connected to the integrated passive device IPD4 through the bonding wire group B6. The gate Gd2 of the small crystal T2 of the auxiliary circuit is connected to the integrated passive device IPD5 through the bonding wire group B5. The integrated passive device IPD1 is connected to the integrated passive device IPD5 through the bonding wire group B10. The integrated passive device IPD3 is connected to the integrated passive device IPD5 through the bonding wire group B9. The integrated passive device IPD2 is connected to the integrated passive device IPD4 through the bonding wire group B13. The input signal pin Pin is connected to the integrated passive device IPD5 through the bonding wire group B11. The output signal pin Pout is connected to the integrated passive device IPD2 through the bonding wire group B12. The main circuit gate power supply pin Vgs1 is connected to the integrated passive device IPD1 through the bonding wire group B14. The auxiliary circuit gate power supply pin Vgs2 is connected to the integrated passive device IPD3 through the bonding wire group B16. The main circuit second transistor T1 drain power supply pin Vds1 is connected to the integrated passive device IPD2 through the bonding wire group B15. The main circuit first transistor T2 drain power supply pin Vds3 is connected to the integrated passive device IPD1 through the bonding wire group B18. The auxiliary circuit second transistor T4 drain power supply pin Vds2 is connected to the integrated passive device IPD4 through the bonding wire group B17. The auxiliary circuit first transistor T3 drain power supply pin Vds4 is connected to the integrated passive device IPD3 through the bonding wire group B19.

[0042] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A cascaded Doherty power amplifier, comprising a main amplifier and at least one auxiliary amplifier, wherein the main amplifier and the auxiliary amplifier respectively comprise a pre-stage driver amplifier and a final amplifier, wherein the pre-stage driver amplifier comprises a driving input matching circuit, the pre-stage driver amplifier and the final amplifier are connected via an input matching circuit, the final amplifier is connected to an output matching circuit, the main output matching circuit is connected to the auxiliary matching amplifier via a delay line, the pre-stage driver amplifier comprises a first transistor, and the final amplifier comprises a second transistor, wherein: The first transistor and the second transistor are integrated on a chip, the gates and drains of the first transistor and the second transistor are alternately placed, the gate of the first transistor and the drain of the second transistor are on the same side of the chip, the drain of the first transistor and the gate of the second transistor are on the other side of the chip, the first transistor and the second transistor are in an isolated state, and the first transistor and the second transistor have the same process parameters.

2. The cascaded Doherty power amplifier according to claim 1, characterized in that: An isolation ground hole is arranged between the first transistor and the second transistor on the chip.

3. The cascaded Doherty power amplifier according to claim 1, characterized in that: The first transistor adopts a multi-unit structure, and the gate is connected to a damping resistor.

4. The cascaded Doherty power amplifier according to claim 1, characterized in that: The gate power supplies of the first transistor and the second transistor are respectively connected to the same pin after passing through the input matching circuit and the driving input matching circuit.

5. The cascaded Doherty power amplifier according to claim 1, characterized in that: The gate of the first transistor of the main path and the gate of the first transistor of the auxiliary path are respectively connected to the main path drive input matching circuit and the auxiliary path drive input matching circuit, the main path drive input matching circuit and the auxiliary path drive input matching circuit are connected to the input power divider, and the connection point between the auxiliary path output matching circuit and the output delay line serves as the final signal output end.

6. The cascaded Doherty power amplifier according to claim 1, characterized in that: The electrical length of the delay line is adjusted according to the electrical length of the output impedance of the second transistor of the main path and the electrical length of the main path output matching circuit. The electrical length of the delay line, the output impedance equivalent electrical length of the second transistor of the main path and the electrical length of the main path output matching circuit add up to an integer multiple of 90 degrees.

7. The cascaded Doherty power amplifier according to claim 1, characterized in that: The sum of the equivalent electrical length of the output impedance of the second transistor of the auxiliary path and the electrical length of the auxiliary path output matching circuit is an integer multiple of 180 degrees.

8. The cascaded Doherty power amplifier according to claim 1, characterized in that: The main input matching circuit is implemented by a first integrated passive device, the main output matching circuit and the delay line are implemented by a second integrated passive device, the auxiliary input matching circuit is implemented by a third integrated passive device, the auxiliary output matching circuit is implemented by a fourth integrated passive device, the input power divider, the main drive input matching circuit and the auxiliary drive input matching circuit are implemented by a fifth integrated passive device, all the integrated passive devices and the main chip and the auxiliary chip integrated with the first transistor and the second transistor are placed on the packaging base, and the fifth integrated passive device is located in the middle of the first integrated passive device and the third integrated passive device, and is located in the middle of the main chip and the auxiliary chip.

9. The cascaded Doherty power amplifier according to claim 8, characterized in that: The gate of the second transistor of the main path is connected to the first integrated passive device through the first bonding wire group, the drain of the first transistor of the main path is connected to the first integrated passive device through the second bonding wire group, the drain of the second transistor of the main path is connected to the second integrated passive device through the third bonding wire group, the gate of the first transistor of the main path is connected to the fifth integrated passive device through the fourth bonding wire group, the gate of the second transistor of the auxiliary path is connected to the third integrated passive device through the seventh bonding wire group, the drain of the first transistor of the auxiliary path is connected to the third integrated passive device through the eighth bonding wire group, the drain of the second transistor of the auxiliary path is connected to the fourth integrated passive device through the sixth bonding wire group, the gate of the first transistor of the auxiliary path is connected to the fifth integrated passive device through the fifth bonding wire group, the first integrated passive device is connected to the fifth integrated passive device through the tenth bonding wire group, the third integrated passive device is connected to the first integrated passive device through the ninth bonding wire group, and the gate of the first transistor of the auxiliary path is connected to the fifth integrated passive device through the ninth bonding wire group. The fifth integrated passive device is connected, the second integrated passive device is connected to the fourth integrated passive device through the thirteenth bonding wire group, the input signal pin is connected to the fifth integrated passive device through the eleventh bonding wire group, the output signal pin is connected to the second integrated passive device through the twelfth bonding wire group, the main path gate power supply pin is connected to the first integrated passive device through the fourteenth bonding wire group, the auxiliary path gate power supply pin is connected to the third integrated passive device through the sixteenth bonding wire group, the main path second transistor drain power supply pin is connected to the second integrated passive device through the fifteenth bonding wire group, the main path first transistor drain power supply pin is connected to the first integrated passive device through the eighteenth bonding wire group, the auxiliary path second transistor drain power supply pin is connected to the fourth integrated passive device through the seventeenth bonding wire group, and the auxiliary path first transistor drain power supply pin is connected to the third integrated passive device through the nineteenth bonding wire group.

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