Delay-locked loop circuit and storage device

Abstract

The embodiment of the invention provides a delay-locked loop circuit and a storage device. The delay-locked loop circuit comprises a first delay circuit, a delay detection feedback circuit, a second delay circuit and a copy circuit. The delay detection feedback circuit is configured to generate a corresponding control code based on the phase difference between the feedback clock signal and the reference clock signal, latch the current control code as a target control code after detecting that the phase difference meets the expectation, and output an effective identification signal; a second delay circuit configured to generate and output a second clock signal based on the first clock signal and the identification signal; wherein, before the delay detection feedback circuit outputs the valid identification signal, the first clock signal is output as the second clock signal, and after the delay detection feedback circuit outputs the valid identification signal, a delay operation is performed on the first clock signal having a target delay amount.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a delay locked loop circuit and a storage device. Background Art

[0002] Clock signals are widely used as signals for synchronizing the operation timing of semiconductor devices. When the clock signal applied from an external device is used inside a semiconductor device, the internal circuit of the semiconductor device may cause a time delay problem. Therefore, a delay locked loop circuit is usually integrated into the semiconductor device. The delay locked loop circuit can be used to compensate for the time delay so that the clock signal inside the semiconductor device is synchronized with the external input clock signal. Summary of the invention

[0003] The embodiments of the present disclosure provide a delay locked loop circuit and a storage device, which are at least beneficial to reducing power consumption.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a delay phase-locked loop circuit, including: a first delay circuit, configured to delay a reference clock signal based on a control code to generate and output a first clock signal with a first delay amount; a delay detection feedback circuit, coupled to the first delay circuit, configured to generate a corresponding control code based on a phase difference between a feedback clock signal and the reference clock signal, and output the control code to the first delay circuit to adjust the first delay amount; after detecting that the phase difference meets expectations, latching the current control code as a target control code, and outputting a valid identification signal; wherein the first delay circuit locks the first delay amount corresponding to the target control code as the target delay amount; a second delay circuit, coupled to the first delay circuit and coupled to the delay detection feedback circuit, configured to generate and output a second clock signal based on the first clock signal and the identification signal; wherein, before the delay detection feedback circuit outputs the valid identification signal, the first clock signal is output as the second clock signal, and after the delay detection feedback circuit outputs the valid identification signal, a delay operation is performed on the first clock signal with the target delay amount to generate and output a second clock signal with a second delay amount; the delay fineness of the second delay circuit is greater than the delay fineness of the first delay circuit; a replica circuit, coupled to the second delay circuit and the delay detection feedback circuit, is configured to delay the second clock signal by a preset delay amount to generate and output the feedback clock signal.

[0005] In some embodiments, the delay detection feedback circuit includes: a phase detection circuit, configured to receive the feedback clock signal and the reference clock signal, generate and output a comparison signal and a reference signal, the edge difference between the comparison signal and the reference signal representing the phase difference; and delay the comparison signal n times to obtain an internal signal set including a first internal signal to an nth internal signal, respectively, compare the edge difference between each internal signal in the internal signal set and the reference signal, and output n code values, each code value represents each comparison result, and the n code values ​​constitute the control code, n is an integer greater than or equal to 2; an identification signal generating circuit, configured to receive the n code values, and generate the identification signal based on the n code values.

[0006] In some embodiments, the phase detection circuit is further configured such that, when the edge of the reference signal is no later than the edge of the mth internal signal, the code value corresponding to the mth internal signal is always logic "0"; when the edge of the reference signal is later than the edge of the mth internal signal, the code value corresponding to the mth internal signal jumps from logic "0" to logic "1", where m is a positive integer less than or equal to n.

[0007] In some embodiments, the n code values ​​include: an xth code value and an x+1th code value, wherein the xth code value is the code value at which the transition edge appears the latest, and the x+1th code value is a constant value; the identification signal generating circuit is configured to perform an XOR logic operation on the xth code value and the x+1th code value to obtain the identification signal, where x is a positive integer less than n.

[0008] In some embodiments, the mth internal signal has a third delay amount compared to the m-1th internal signal, where m is a positive integer less than or equal to n; the identification signal generating circuit includes: a delay logic circuit, configured to receive the n code values, and delay each code value by the third delay amount, wherein the yth code value among the 1st code value to the nth code value is delayed to obtain the yth delayed code value, where y is a positive integer less than n; n-1 first XOR logic circuits, the yth first XOR logic circuit is configured to receive the yth delayed code value and the y+1th code value, and perform an XOR operation; multiple levels of second XOR logic circuits, each level of the second XOR logic circuit performs a corresponding XOR operation based on the XOR operation result of the second XOR logic circuit of the previous level, the second XOR operation logic circuit of the last level outputs the identification signal, and the second XOR logic circuit at the first level performs a corresponding XOR operation based on the XOR operation result of the first XOR logic circuit.

[0009] In some embodiments, the delay locked loop circuit also includes: a phase detector, coupled to the replica circuit, configured to detect the phase difference between the reference clock signal and the feedback clock signal, and generate and output an adjustment signal corresponding to the phase difference; a delay controller, coupled to the phase detector and the delay detection feedback circuit, configured to receive the adjustment signal and the identification signal, and when the identification signal is valid, adjust the second delay amount based on the adjustment signal, and when the identification signal is invalid, set the second delay amount to 0 based on a default control signal.

[0010] In some embodiments, the phase detection circuit includes: a receiving circuit, configured to receive the feedback clock signal and the reference clock signal, generate and output the comparison signal and the reference signal; a conversion circuit, configured to receive the comparison signal and the reference signal, delay the comparison signal n times to obtain the internal signal set, and output the n code values.

[0011] In some embodiments, the receiving circuit includes: a first sampling circuit, configured to receive an input signal and sample the input signal in response to the feedback clock signal to generate and output the comparison signal and the complementary comparison signal that are in an inverse relationship with each other; a second sampling circuit, configured to receive the complementary comparison signal and sample the complementary comparison signal in response to the reference clock signal to generate and output the reference signal.

[0012] In some embodiments, the first sampling circuit includes: a plurality of cascaded first triggers, the clock end of each stage of the first trigger receives the feedback clock signal, the data input end of each stage of the first trigger is connected to the positive phase output end of the first trigger of the previous stage, the input data end of the first trigger of the first stage receives the input signal, and the positive phase output end and the negative phase output end of the first trigger of the last stage output the comparison signal and the complementary comparison signal respectively; the second sampling circuit includes: a second trigger, the data input end of the second trigger is connected to the negative phase output end of the first trigger of the last stage, and the clock end of the second trigger receives the reference clock signal.

[0013] In some embodiments, the conversion circuit includes: n cascaded delay converters including a 1st delay converter to an nth delay converter, wherein the mth delay converter is configured to receive the m-1th internal signal output by the m-1th delay converter, delay the m-1th internal signal by a third delay amount to generate an mth internal signal, and output the mth internal signal to the m+1th delay converter; wherein the 1st delay converter receives the comparison signal and delays the comparison signal by the preset delay amount to generate and output the 1st internal signal; the mth delay converter is also configured to compare the edge difference between the reference signal and the mth internal signal, and output a corresponding mth code value, wherein the mth code value represents whether the edge of the reference signal is no later than the edge of the mth internal signal.

[0014] In some embodiments, the third delay amount of each of the delay converters is the same.

[0015] In some embodiments, the mth delay converter includes: an mth delayer, configured to receive the m-1th internal signal and delay it with the third delay amount, generate and output the mth internal signal; an mth comparison converter, configured to receive and compare the mth internal signal and the reference signal, and output the mth code value.

[0016] In some embodiments, the mth comparison converter includes: a first PMOS tube, the source of the first PMOS tube is connected to the working power supply, and the gate receives a reset signal; a first NMOS tube, the gate of the first NMOS tube receives the mth internal signal, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the source of the first NMOS tube is used as an output node; a second NMOS tube, the gate of the second NMOS tube receives the reference signal, the drain of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the second NMOS tube is connected to the ground terminal; a holding circuit, the input end of the holding circuit is connected to the output node, and is used to latch and output the signal of the output node after the first NMOS tube and the second NMOS tube are both turned on; an even number of cascaded inverters, the output end of the holding circuit is connected to the input end of the inverter of the first stage, and the output end of the inverter at the tail stage outputs the mth code value. According to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a storage device on the other hand, including the delay phase-locked loop circuit provided by any of the above embodiments.

[0017] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0018] In the technical solution of the delay phase-locked loop circuit provided by the embodiment of the present disclosure, the control code generated in the delay detection feedback circuit represents the delay amount of the feedback clock signal compared to the reference clock signal. Therefore, when the reference clock signal input next time is compensated based on the control code, the reference clock signal can be accurately compensated based on the delay amount actually generated by the reference clock signal, so that the phase between the received feedback clock signal output next time is close to or the same as the reference clock signal, thereby improving the efficiency of the delay phase-locked loop circuit in compensating for time delay. In addition, the delay detection feedback circuit also generates an identification signal, and the effective identification signal represents that the first delay circuit locks the target delay amount, and the second delay circuit performs a delay operation in response to the effective identification signal to ensure that the second delay circuit will perform a delay operation only after the first delay circuit locks the target delay amount, thereby facilitating shortening the working time of the second delay circuit and reducing the power consumption of the delay phase-locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A block diagram of a delay locked loop circuit;

[0021] Figure 2 for Figure 1 The timing diagram of each signal in the delay phase-locked loop circuit;

[0022] Figure 3 A block diagram of a delay detection feedback circuit;

[0023] Figure 4 is a block diagram of a phase detection circuit;

[0024] Figure 5 A block diagram of a receiving circuit;

[0025] Figure 6 for Figure 5 A circuit structure diagram of a receiving circuit in FIG.

[0026] Figure 7 A timing diagram of phase detection performed by a phase detector in a delay detection circuit provided by an embodiment of the present disclosure;

[0027] Figure 8 A block diagram of a conversion circuit;

[0028] Fig. 9 is a block diagram of an m-th delay converter;

[0029] Fig.10 is a schematic diagram of a circuit structure of the mth delay converter;

[0030] Fig.11 A schematic diagram of a circuit structure of a conversion circuit;

[0031] Fig.12 for Fig.11 Timing diagram of each signal in;

[0032] Fig.13 A block diagram of a circuit for generating a marking signal;

[0033] Fig.14 for Fig.13 Timing diagram of each signal in;

[0034] Fig.15 is a block diagram of the identification signal generating circuit 122;

[0035] Fig.16 for Fig.15 Timing diagram of each signal in;

[0036] Fig.17 A schematic diagram of a circuit structure of an identification signal generating circuit;

[0037] Fig.18 is a schematic diagram of a circuit structure of a first delay circuit;

[0038] Fig.19 is another block diagram of a delay locked loop circuit;

[0039] Fig. 20 Another block diagram of a delay locked loop circuit. DETAILED DESCRIPTION

[0040] The delay locked loop circuit includes a coarse delay circuit (CDL) and a fine delay circuit (FDL), wherein the delay fineness of the coarse delay circuit is greater than or less than the delay fineness of the fine delay circuit. In the related art, both the coarse delay circuit and the fine delay circuit work according to the set time. Regardless of whether the coarse delay circuit locks the target delay amount, the fine delay circuit will finely delay the received clock signal after the preset time when the delay locked loop circuit starts working. Then, there is a situation where the fine delay circuit starts working before the coarse delay circuit locks the target amount, which leads to an increase in the working time of the fine delay circuit, and correspondingly brings about the problem of high power consumption of the delay locked loop circuit.

[0041] The disclosed embodiment provides a delay phase-locked loop circuit, in which the fine delay circuit starts to perform the delay operation only after ensuring that the coarse delay circuit has locked the target delay amount, which is beneficial to shortening the working time of the fine delay circuit to perform the delay operation, thereby reducing power consumption.

[0042] In order to make the purpose, technical scheme and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0043] Figure 1 A block diagram of a delay locked loop circuit.

[0044] refer to Figure 1 The embodiment of the present disclosure provides a delay phase-locked loop circuit, including a first delay circuit 101, a delay detection feedback circuit 102, a second delay circuit 103 and a replica circuit 104.

[0045] The first delay circuit 101 is configured to delay the reference clock signal CLKREF based on the control code Code to generate and output the first clock signal CLK_1 having a first delay amount.

[0046] The delay detection feedback circuit 102 is coupled to the first delay circuit 101. The delay detection feedback circuit 102 is configured to generate a corresponding control code Code based on the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, and output the control code Code to the first delay circuit 101 to adjust the first delay amount; after detecting that the phase difference meets the expectation, the current control code Code is latched as the target control code Code, and a valid identification signal Flag is output; wherein the first delay circuit 101 locks the first delay amount corresponding to the target control code Code as the target delay amount.

[0047] The second delay circuit 103 is coupled to the first delay circuit 101 and the delay detection feedback circuit 102. The second delay circuit 103 is configured to generate and output the second clock signal CLK_2 based on the first clock signal CLK_1 and the identification signal Flag; wherein, before the delay detection feedback circuit 102 outputs the valid identification signal Flag, the first clock signal CLK_1 is output as the second clock signal CLK_2, and after the delay detection feedback circuit 102 outputs the valid identification signal Flag, a delay operation is performed on the first clock signal CLK_1 having the target delay amount to generate and output the second clock signal CLK_2 having the second delay amount; the delay fineness of the second delay circuit 103 is greater than the delay fineness of the first delay circuit 101.

[0048] The replica circuit 104 is coupled to the second delay circuit 103 and the delay detection feedback circuit 102 , and is configured to delay the second clock signal CLK_2 by a preset delay amount to generate and output a feedback clock signal CLKFB.

[0049] The delay detection feedback circuit 102 is used to implement a fast locking function. The delay amount of the clock signal by the first delay circuit 101 and the second delay circuit 103 is adjustable. By adjusting the delay amount of the first delay circuit 101 and the delay amount of the second delay circuit 103, the phases of the feedback clock signal CLKFB and the second clock signal CLK_2 are made the same, so that the target clock signal finally outputted meets the requirements. The working principle of the delay detection feedback circuit 102 includes: receiving the feedback clock signal CLKFB and the reference clock signal CLKREF, and converting the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF into a control code Code composed of multiple code values, and the control code Code is used to control the first delay circuit 101 to adjust the delay amount of the first delay circuit 101. After detecting that the phase difference is in line with expectations, the delay detection feedback circuit 102 latches the current control code Code as the target control code Code. The first delay circuit 101 locks the first delay amount corresponding to the target control code Code as the target delay amount. The first clock signal CLK_1 output by the first delay circuit 101 is obtained by delaying the reference clock signal CLKREF by the target delay amount, so that the phases of the reference clock signal CLKREF and the feedback clock signal CLKFB are close.

[0050] In the above embodiment, the delay detection feedback circuit 102 outputs a valid identification signal Flag when latching the target control code Code. If the identification signal Flag is valid, it indicates that the first delay circuit 101 has locked the target delay amount, and the first delay circuit 101 ends the delay adjustment operation on the reference clock signal CLKREF. Before the delay detection feedback circuit 102 outputs a valid identification signal Flag, the second delay circuit 103 does not delay the received first clock signal CLK_1. After the delay detection feedback circuit 102 outputs a valid identification signal Flag, the second delay circuit 103 performs a delay operation on the first clock signal CLK_1 with the target delay amount to generate and output the second clock signal CLK_2. In other words, the embodiment of the present disclosure can avoid the situation where the second delay circuit 103 performs a delay operation in advance when the first delay circuit 101 has not locked the target delay amount, thereby shortening the working time of the second delay circuit 103 performing the delay operation, which is conducive to reducing power consumption.

[0051] The delay locked loop circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0052] Figure 2 for Figure 1 The timing diagram of each signal in the delay phase-locked loop circuit. Figure 1 and Figure 2 , the working principle of the delay phase-locked loop circuit is as follows:

[0053] The reference clock signal CLKREF is generated based on an external clock, and the reference clock signal CLKREF has a first sub-delay t1 relative to the external clock signal, and the second clock signal CLK_2 is transmitted as the target clock signal after passing through the second sub-delay t2. How to ensure that the target clock signal is edge-aligned with the external clock signal is one of the main functions of the delay phase-locked loop circuit. Among them, the edge correspondence between the external clock signal and the target clock signal is the ultimate goal. Since the reference clock signal CLKREF differs from the external clock signal by the first sub-delay t1, the second clock signal CLK_2 differs from the target clock signal by the second sub-delay t2, and the feedback clock signal CLKFB differs from the second clock signal CLK_2 by a preset delay t3, when the edge of the external clock signal corresponds to the edge of the target clock signal, the edge of the feedback clock signal CLKFB is aligned with the edge of the reference clock signal CLKREF. Then, correspondingly, t3=t1+t2, that is, the function of the replica circuit is to replicate the first sub-delay amount t1 and the second sub-delay amount t2, that is, the preset delay amount is the sum of the first sub-delay amount t1 and the second sub-delay amount t2.

[0054] That is, the functions of the first delay circuit 101 and the second delay circuit 103 include: sequentially and sequentially delaying and adjusting the reference clock signal CLKREF, and finally outputting the second clock signal CLK_2 having the same phase as the feedback clock signal CLKFB, so that the target clock signal obtained based on the second clock signal CLK_2 has the same phase as the external clock signal. The precision of the delay adjustment of the first delay circuit 101 is less than the precision of the delay adjustment of the second delay circuit 103, that is, coarse adjustment is performed first and then fine adjustment is performed, so as to quickly obtain the second clock signal CLK_2 having the same phase as the feedback clock signal CLKFB.

[0055] It can be understood that, unless otherwise specified, the “edge alignment” in the embodiments of the present disclosure means that the phases of the two clock signals are the same, that is, the two clock signals are in the same phase.

[0056] Figure 3 A block diagram of a delay detection feedback circuit.

[0057] refer to Figure 3 The delay detection feedback circuit 102 may include a phase detection circuit 112 and a flag signal generating circuit 122 .

[0058] The phase detection circuit 112 is configured to receive the feedback clock signal CLKFB and the reference clock signal CLKREF, generate and output the comparison signal Data_TDC and the reference signal CLK_TDC, the edge difference between the comparison signal Data_TDC and the reference signal CLK_TDC represents the phase difference; and delay the comparison signal Data_TDC n times to obtain an internal signal set including the first internal signal to the nth internal signal, compare the edge difference between each internal signal in the internal signal set and the reference signal CLK_TDC, and output n code values, each code value represents each comparison result, and the n code values ​​constitute a control code Code, n is an integer greater than or equal to 2. The control code Code includes Q <1> To Q <n>It is composed of n code values.

[0059] In addition, unless otherwise specified, the first code value mentioned later refers to the code value Q among the n code values. <1> , the second code value refers to the code value Q <2> , and so on, the nth code value refers to the code value Q <n>.

[0060] The identification signal Flag generating circuit 122 is configured to receive n code values ​​and generate an identification signal Flag based on the n code values.

[0061] The phase detection circuit 112 can convert the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF into a control code Code consisting of n code values, where the n code values ​​are binary values. In this way, the phase detection circuit 112 can convert phase information into digital information.

[0062] In some embodiments, the comparison signal Data_TDC and the second signal CLK_TDC may be level signals, and the comparison signal Data_TDC is used to characterize the feedback clock signal CLKFB, and the second signal CLK_TDC is used to characterize the reference clock signal CLKREF, so that the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF can be converted into the difference between the edges of the level signal. Since the edge moment of the level signal is easier to obtain, the difference between the edges of the obtained level signal is more accurate. Therefore, the difference between the edges of the level signal is used to characterize the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, which can more accurately characterize the actual phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, so that the delay locked loop circuit has a higher accuracy in compensating for time delay.

[0063] In some other embodiments, the comparison signal Data_TDC may also be used to characterize the reference clock signal CLKREF, and the reference signal CLK_TDC may also be used to characterize the feedback clock signal CLKFB.

[0064] Figure 4 A block diagram of a phase detection circuit.

[0065] refer to Figure 4 , the phase detection circuit 112 may include a receiving circuit 201 and a conversion circuit 202. The receiving circuit 201 is configured to receive the feedback clock signal CLKFB and the reference clock signal CLKREF, generate and output the comparison signal Data_TDC and the reference signal CLK_TDC. The conversion circuit 202 is configured to receive the comparison signal and the reference signal CLK_TDC, and delay the comparison signal Data_TDC n times to obtain an internal signal set, and output n code values.

[0066] In some embodiments, the receiving circuit 201 can be configured to receive an input signal, sample the input signal in response to the feedback clock signal CLKFB, and output a comparison signal Data_TDC; sample the first complementary signal in response to the reference clock signal CLKREF, and output a reference signal CLK_TDC, wherein the complementary comparison signal and the comparison signal Data_TDC are mutually inverted signals. The input signal is a level signal, so the comparison signal Data_TDC obtained by sampling the input signal in response to the feedback clock signal CLKFB will also be a level signal, and the reference signal CLK_TDC is also a level signal. The complementary comparison signal has the same edge position as the comparison signal Data_TDC, but is mutually inverted, that is, the complementary comparison signal has the same edge transition moment as the comparison signal Data_TDC, but the transition mode is opposite. For example, when the edge transition moment of the complementary comparison signal is a rising edge, the edge transition moment of the comparison signal Data_TDC is a falling edge. The reference signal CLK_TDC is obtained based on the complementary comparison signal. Therefore, the edge of the reference signal CLK_TDC is opposite to the edge of the comparison signal Data_TDC. This is beneficial for the subsequent use of the conversion circuit 202 to compare the comparison signal Data_TDC and the reference signal CLK_TDC with opposite edges.

[0067] The comparison signal Data_TDC is obtained by sampling the input signal in response to the feedback clock signal CLKFB, and the reference signal CLK_TDC is obtained by sampling the complementary comparison signal in response to the reference clock signal CLKREF, and the complementary comparison signal is the same as the comparison signal Data_TDC, that is, it is also obtained based on sampling the input signal. It can be seen that the comparison signal Data_TDC and the reference signal CLK_TDC are actually obtained by sampling the input signal, and the comparison signal Data_TDC is used to characterize the feedback clock signal CLKFB, and the reference signal CLK_TDC is used to characterize the reference clock signal CLKREF. Therefore, the difference between the edges obtained by comparing the edge differences of the comparison signal Data_TDC and the reference signal CLK_TDC can accurately characterize the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF. The difference between the edge timings of the comparison signal Data_TDC and the reference signal CLK_TDC refers to the difference between the rising edge timing of the comparison signal Data_TDC and the rising edge timing of the reference signal CLK_TDC; or the difference between the falling edge timing of the comparison signal Data_TDC and the falling edge timing of the reference signal CLK_TDC.

[0068] Figure 5 A block diagram of a receiving circuit.

[0069] refer to Figure 5 , the receiving circuit 201 may include a first sampling circuit 211 and a second sampling circuit 221. The first sampling circuit 211 is configured to receive an input signal DL_TDCRSTB, and sample the input signal DL_TDCRSTB in response to a feedback clock signal CLKFB to generate and output a comparison signal Data_TDC and a complementary comparison signal Data_TDCB that are in an anti-phase relationship with each other. The second sampling circuit 221 is configured to receive a complementary comparison signal Data_TDCB, and sample the complementary comparison signal Data_TDCB in response to a reference clock signal CLKREF to generate and output a reference signal CLK_TDC.

[0070] The comparison signal Data_TDC and the complementary comparison signal Data_TDCB are acquired by the first sampling circuit 211 , so that the comparison signal Data_TDC and the complementary comparison signal Data_TDCB are the same signal, and the comparison signal Data_TDC and the complementary comparison signal Data_TDCB are inverted signals.

[0071] The first sampling circuit 211 and the second sampling circuit 221 perform sampling respectively to output the comparison signal Data_TDC and the reference signal CLK_TDC. It can be known that if there is a phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, the edge of the comparison signal Data_TDC is earlier than the edge of the reference signal CLK_TDC, that is, there is a moment when the comparison signal Data_TDC and the reference signal CLK_TDC are both at a logic high level, and the length of time when the comparison signal Data_TDC and the reference signal CLK_TDC are both at a logic high level is the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF; if there is no phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, the edge of the comparison signal Data_TDC and the edge of the reference signal CLK_TDC are at the same time, that is, there is no moment when the comparison signal Data_TDC and the reference signal CLK_TDC are both at a logic high level.

[0072] In this way, sampling can be performed in response to the feedback clock signal CLKFB and the reference clock signal CLKREF respectively, so that the first sampling circuit 211 and the second sampling circuit 221 will not affect each other, which is conducive to improving the accuracy of the obtained comparison signal Data_TDC and the reference signal CLK_TDC. It is worth noting that the feedback clock signal CLKFB and the reference clock signal CLKREF are simultaneously input into the first sampling circuit 211 and the second sampling circuit 221, so that the difference between the edges of the obtained comparison signal Data_TDC and the reference signal CLK_TDC can accurately represent the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.

[0073] Figure 6 for Figure 5 A circuit structure diagram of a receiving circuit in FIG.

[0074] refer to Figure 6 The first sampling circuit 211 may include a plurality of cascaded first triggers 2111, the clock end of each stage of the first trigger 2111 receives the feedback clock signal CLKFB, the data input end of each stage of the first trigger 2111 is connected to the positive phase output end of the first trigger 2111 of the previous stage, the input data end of the first trigger 2111 of the first stage receives the input signal DL_TDCRSTB, and the positive phase output end and the negative phase output end of the first trigger 2111 of the last stage output the comparison signal Data_TDC and the complementary comparison signal Data_TDCB respectively.

[0075] Continue to refer Figure 6 The second sampling circuit 221 may include a second flip-flop 2211, a data input terminal of the second flip-flop 2211 is connected to the inverting output terminal of the first flip-flop 2111 of the last stage, and a clock terminal of the second flip-flop 2211 receives a reference clock signal CLKREF.

[0076] In the first trigger 2111 of the first stage, the data input terminal receives the input signal DL_TDCRSTB, and the clock terminal receives the feedback clock signal CLKFB. The first trigger 2111 is configured to sample the input signal DL_TDCRSTB when the edge of the feedback clock signal CLKFB arrives to output the corresponding comparison signal Data_TDC. In this way, the level change of the comparison signal Data_TDC can represent the phase change of the feedback clock signal CLKFB. Specifically, the first trigger 2111 of each stage samples the input signal DL_TDCRSTB at the edge of a feedback clock signal CLKFB cycle.

[0077] In some embodiments, when the number of first flip-flops 2111 is 4, the first first flip-flop 2111 in the cascaded first flip-flops 2111 receives the input signal DL_TDCRSTB, and samples the input signal DL_TDCRSTB when the edge moment of the feedback clock signal CLKFB arrives, and outputs the sampled input signal DL_TDCRSTB. The second-stage first flip-flop 2111 receives the sampled input signal DL_TDCRSTB output by the first-stage first flip-flop 2111, and samples the sampled input signal DL_TDCRSTB when the next edge moment of the feedback clock signal CLKFB arrives, wherein the edge moment may be the rising edge of the feedback clock signal CLKFB. In other embodiments, the edge moment may be the falling edge of the feedback clock signal CLKFB. By analogy, when the edge moment of the fourth feedback clock signal CLKFB arrives, the last first trigger 2111 in the cascaded first trigger 2111 samples the sampled input signal DL_TDCRSTB output by the previous first trigger 2111. After sampling, the signal output by the positive phase output terminal of the last first trigger 2111 is used as the comparison signal Data_TDC. Using multiple cascaded first triggers 2111 to sample the input signal DL_TDCRSTB to obtain the comparison signal Data_TDC can ensure that the first trigger 2111 can collect the input signal DL_TDCRSTB within the edge moment of a complete feedback clock signal CLKFB cycle, so that the obtained comparison signal Data_TDC can represent the complete phase of the feedback clock signal CLKFB.

[0078] The inverting output terminal of the last-stage first flip-flop 2111 outputs the complementary comparison signal Data_TDCB, so that the output complementary comparison signal Data_TDCB is inverted with the comparison signal Data_TDC.

[0079] The second trigger 2211 is configured to sample the complementary comparison signal Data_TDCB when the edge of the reference clock signal CLKREF arrives to output the corresponding reference signal CLK_TDC. In this way, the level change of the comparison signal Data_TDC can represent the phase change of the feedback clock signal CLKFB. Specifically, the second trigger 2211 samples the input signal DL_TDCRSTB at the edge of a reference clock signal CLKREF.

[0080] Specifically, in some embodiments, the principle that the first sampling circuit 211 samples the input signal DL_TDCRSTB and the second sampling circuit 221 samples the complementary comparison signal Data_TDCB can be referred to. Figure 4 .

[0081] Figure 7 A timing diagram of phase detection performed by a phase detector in a delay detection circuit provided in an embodiment of the present disclosure.

[0082] refer to Figure 6 as well as Figure 7 , among the multiple cascaded first flip-flops 2111, each level of the first flip-flop 2111 responds to the feedback clock signal CLKFB, and samples the input signal DL_TDCRSTB at the arrival time of each feedback clock signal CLKFB edge moment. Among them, the last level of the first flip-flop 2111 samples the input signal DL_TDCRSTB output by the previous level of the first flip-flop 2111 at the arrival time of the fourth feedback clock signal CLKFB edge moment in the four feedback clock signal CLKFB cycles, and outputs the comparison signal Data_TDC, and at the same time, outputs the complementary comparison signal Data_TDCB. It is not difficult to find that the edge moment of the complementary comparison signal Data_TDCB is the same as the edge moment of the comparison signal Data_TDC, and the complementary comparison signal Data_TDCB and the comparison signal Data_TDC are mutually inverted signals. In some embodiments, the first flip-flop 2111 can sample the input signal DL_TDCRSTB at the rising edge moment of the feedback clock signal CLKFB. In some other embodiments, the second flip-flop 2211 may also sample the input signal DL_TDCRSTB at the falling edge of the feedback clock signal CLKFB cycle.

[0083] The inverting output terminal of the first trigger 2111 of the last stage transmits the complementary comparison signal Data_TDCB to the second trigger 2211, and the second trigger 2211 samples the complementary comparison signal Data_TDCB in response to the reference clock signal CLKREF. Specifically, the second trigger 2211 samples the complementary comparison signal Data_TDCB at the moment when the reference clock signal CLKREF cycle arrives to obtain the reference signal CLK_TDC. It is worth noting that when the first trigger 2111 samples the input signal DL_TDCRSTB at the rising edge of the feedback clock signal CLKFB cycle, the second trigger 2211 also needs to sample the complementary comparison signal Data_TDCB at the rising edge of the reference clock signal CLKREF. When the second trigger 2211 samples the input signal DL_TDCRSTB at the falling edge of the feedback clock signal CLKFB, the second trigger 2211 also needs to sample the complementary comparison signal Data_TDCB at the falling edge of the reference clock signal CLKREF, thereby ensuring that the difference between the edges of the obtained comparison signal Data_TDC and the reference signal CLK_TDC can accurately characterize the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.

[0084] Since the reference clock signal CLKREF and the feedback clock signal CLKFB are input into the first sampling circuit 211 and the second sampling circuit 221 at the same time, that is, the second sampling circuit 221 receives the complementary comparison signal Data_TDCB from the first sampling circuit 211, and the reference clock signal CLKREF is also input into the second sampling circuit 221 in real time. In this way, when the complementary comparison signal Data_TDCB is input into the second flip-flop 2211, the second flip-flop 2211 can synchronously respond to the reference clock signal CLKREF to sample the complementary comparison signal Data_TDCB, so that the edge difference between the obtained comparison signal Data_TDC and the reference signal CLK_TDC can accurately represent the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB.

[0085] In some embodiments, when there is a phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, there is a time delay between the edge of the feedback clock signal CLKFB and the edge of the reference clock signal CLKREF. Thus, when the second flip-flop 2211 samples the complementary comparison signal Data_TDCB in response to the edge of the reference clock signal CLKREF, the complementary comparison signal Data_TDCB will be sampled after the delay time corresponding to the difference between the edge of the feedback clock signal CLKFB and the edge of the reference clock signal CLKREF, so that there is a time difference between the edge of the output reference signal CLK_TDC and the edge of the complementary comparison signal Data_TDCB, and the time difference can reflect the delay time corresponding to the difference between the edge of the feedback clock signal CLKFB and the edge of the reference clock signal CLKREF.

[0086] In other embodiments, when there is no phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, since the complementary comparison signal Data_TDCB is obtained by the first trigger 2111 sampling the input signal DL_TDCRSTB at the edge moment of the feedback clock signal CLKFB, such as the rising edge moment, when the complementary comparison signal Data_TDCB is input to the second trigger 2211, the rising edge moment of the reference clock signal CLKREF just arrives, and therefore, the second trigger 2211 can synchronously sample the complementary comparison signal Data_TDCB without the delay time between the edge moment of the feedback clock signal CLKFB and the edge moment of the reference clock signal CLKREF, so that the edge of the output complementary comparison signal Data_TDCB is aligned with the edge of the reference signal CLK_TDC.

[0087] In some embodiments, when the delay detection circuit is not used, the feedback clock signal CLKFB and the reference clock signal CLKREF transmitted to the phase detector 101 can be turned off, that is, the feedback clock signal CLKFB and the reference clock signal CLKREF are gated (clock gating), and the gated signals are respectively the gated feedback clock signal CLKFB_SYSC and the gated reference clock signal CLKREF_SYSC. The phase difference of the gated feedback clock signal CLKFB_SYSC and the gated reference clock signal CLKREF_SYSC is detected to obtain the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, which can reduce the power consumption generated by the delay detection circuit.

[0088] In some other embodiments, the second sampling circuit 221 may also include a plurality of cascaded second flip-flops 2211, and the number of the second flip-flops 2211 is equal to the number of the first flip-flops 2111. The clock signal end of each stage of the second flip-flops 2211 receives the reference clock signal CLKREF, and the data input end of each stage of the second flip-flops 2211 is connected to the positive phase output end of the second flip-flop 2211 of the previous stage, the data input end of the second flip-flop 2211 of the first stage receives the input signal DL_TDCRSTB, and the positive phase output end of the second flip-flop 2211 of the last stage outputs the reference signal CLK_TDC. That is to say, the first sampling circuit 211 and the second sampling circuit 221 simultaneously and respectively sample the input signal DL_TDCRSTB in response to the feedback clock signal CLKFB and the reference clock signal CLKREF, and output the comparison signal Data_TDC and the reference signal CLK_TDC. Since the same input signal DL_TDCRSTB is sampled in response to the feedback clock signal CLKFB and the reference clock signal CLKREF, the difference between the edges of the comparison signal Data_TDC and the reference signal CLK_TDC can be used to characterize the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.

[0089] It can be understood that in other embodiments, the first sampling circuit 211 can sample the input signal DL_TDCRSTB in response to the reference clock signal CLKREF to output the comparison signal Data_TDC, and accordingly, the second sampling circuit 221 can sample the complementary comparison signal Data_TDCB in response to the feedback clock signal CLKFB and output the reference signal CLK_TDC.

[0090] The conversion circuit 202 receives the comparison signal Data_TDC and the reference signal CLK_TDC, and delays the comparison signal Data_TDC n times, so that the edge of the comparison signal Data_TDC is aligned with the edge of the reference signal CLK_TDC or the edge of the comparison signal Data_TDC is later than the edge of the reference signal CLK_TDC, wherein after each delay, the edge difference between the comparison signal Data_TDC and the reference signal CLK_TDC will be smaller, so that the edge difference between the comparison signal Data_TDC and the reference signal CLK_TDC is smaller or aligned. n is a positive integer greater than or equal to 2.

[0091] Figure 8 A block diagram of a conversion circuit.

[0092] refer to Figure 8 , the conversion circuit 202 may include: n cascaded delay converters 212 including the first delay converter 212 to the nth delay converter 212, wherein the mth delay converter 212 is configured to receive the m-1th internal signal Data_TDCm-1 output by the m-1th delay converter 212, delay the m-1th internal signal Data_TDCm-1 by a third delay amount to generate the mth internal signal Data_TDCm, and output the mth internal signal Data_TDCm to the m+1th delay converter; wherein the first delay converter 212 receives the comparison signal Data_TDC and delays the comparison signal Data_TDC by a third delay amount to generate and output the first internal signal Data_TDC1. The mth delay converter 212 is also configured to compare the edge difference between the reference signal CLK_TDC and the mth internal signal Data_TDCm, and output the corresponding code value Q <m>, code value Q <m>Characterizes whether the edge of the reference signal CLK_TDC is no later than the edge of the mth internal signal Data_TDCm.

[0093] The internal signal set includes n internal signals from the first internal signal DATA_TDC1 to the nth internal signal DATA_TDCn, and the mth internal signal is DATA_TDCm. <1> -Q <n>The code value corresponding to the first internal signal is identified as Q <1> , which is the first code value, and the code value corresponding to the mth internal signal is identified as Q <m>, which is the mth code value.

[0094] Wherein, the code value is a binary value. In some examples, the phase detection circuit 112 (refer to Figure 3 ) can be configured such that when the edge of the reference signal CLK_TDC is not later than the edge of the mth internal signal Data_TDCx, the code value Q corresponding to the mth internal signal Data_TDCx <x>is always logic "0"; when the edge of the reference signal CLK_TDC is later than the edge of the mth internal signal Data_TDCx, the code value Q corresponding to the mth internal signal Data_TDCx <x>From logic "0" to logic "1". Code value Q <x>The transition time from logic "0" to logic "1" is at the edge (rising edge) of the mth internal signal Data_TDCx. m is any positive integer less than or equal to n.

[0095] The conversion circuit 202 can delay the comparison signal Data_TDC to obtain the corresponding internal signal, and then compare the edge difference between the internal signal and the reference signal CLK_TDC. If the edge of the internal signal obtained after the delay of the n-stage delay converter 212 is still earlier than the edge of the reference signal CLK_TDC, that is, the delay of the comparison signal Data_TDC by the n-stage delay converter 212 is still not enough to offset the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF. If the edge of the internal signal obtained after the delay of the m-stage delay converter 212 is later than or equal to the edge of the reference signal CLK_TDC, the delay of the comparison signal Data_TDC by the m-stage delay converter 212 can offset the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF. At this time, the code value Q output by each stage of the 1st to m-1st stage delay converters 212 jumps from logic "0" to logic "1", and the code value Q output by each stage of the m-stage to n-stage delay converters 212 is always logic "0".

[0096] The third delay amount of each stage of the delay converter 212 is the same, that is, the received comparison signal Data_TDC or the internal signal is delayed by the third delay amount.

[0097] Fig. 9 A block diagram of an m-th delay converter.

[0098] refer to Fig. 9 The mth delay converter 212 includes an mth delayer 2121 and an mth comparison converter 2122. The mth delayer 2121 is configured to receive the m-1th internal signal Data_TDCm-1, delay it by a third delay amount, generate and output the mth internal signal Data_TDCm. The mth comparison converter 2122 is configured to receive and compare the mth internal signal Data_TDCm and the reference signal CLK_TDC, and output the mth code value Q <m>.

[0099] Fig.10 Schematic diagram of a circuit structure of the mth delay converter. Fig.11 A schematic diagram of a circuit structure of a conversion circuit is shown in FIG. Fig.12 for Fig.11 Timing diagram of each signal in .

[0100] refer to Fig.10 and Fig.11 In some embodiments, the m-th delayer 2121 may include: a first delay unit 1101, configured to receive the m-1th internal signal DATA_TDCm-1 output by the previous stage delay converter 212, and delay the m-1th internal signal DATA_TDCm-1 to generate a sub-delay signal; a second delay unit 1102, configured to receive the sub-delay signal, and delay the sub-delay signal to generate and output the m-th internal signal DATA_TDCm. In other words, each m-th delayer 2121 may include different first delay units 1101 and second delay units 1102, so that the first delay unit 1101 and the second delay unit 1102 can respectively delay the m-1th internal signal DATA_TDCm-1, and flexibly adjust the delay amount of the m-1th internal signal DATA_TDCm-1.

[0101] In some embodiments, the mth delayer 2121 may include two second delay units 1102 with the same delay amount, wherein the output end of one second delay unit 1102 is connected to the first delay unit 1101 of the m+1th delay converter, and the output end of the other second delay unit 1102 is connected to the mth comparison converter 2122. Specifically, the output end of one second delay unit 1102 is used to provide the mth internal signal DATA_TDCm to the m+1th delay converter, thereby further delay adjusting the comparison signal Data_TDC. The output end of the other second delay unit 1102 is used to transmit the mth internal signal DATA_TDCm to the mth comparison converter 2122 to detect the edge difference between the mth internal signal DATA_TDCm and the reference signal CLK_TDC.

[0102] Since the two second delay units 1102 have the same delay amount, the mth internal signal DATA_TDCm output by the two second delay units 1102 is the same signal, so that the mth internal signal DATA_TDCm used for detection and the mth internal signal DATA_TDCm used for further delay can be highly consistent.

[0103] In addition, compared to using only one second delay unit 1102, and the second delay unit 1102 includes a first end and a second end, which are respectively used to input the mth internal signal DATA_TDCm to the next stage (m+1)th delay converter, and to input the mth internal signal DATA_TDCm to the mth comparison converter, using two second delay units 1102 with the same delay amount makes the transmitted mth internal signal DATA_TDCm have higher integrity.

[0104] It can be understood that, in some other embodiments, the mth delay converter may also include only one second delay unit 1102 .

[0105] Continue to refer Fig.10 and Fig.11 In some embodiments, the first delay unit 1101 includes a first NAND gate, one input end of which is connected to the working power supply VDD, and the other end receives the m-1th internal signal DATA_TDCm-1 output by the m-1th delayer 2121; the second delay unit 1102 includes a second NAND gate, one input end of which is connected to the working power supply VDD, and the other input end is connected to the output end of the first delay unit 1101, and the output end provides the mth internal signal DATA_TDCm.

[0106] It can be understood that when the comparison signal Data_TDC is not delayed, the edge time of the comparison signal Data_TDC is earlier than the edge time of the reference signal CLK_TDC. In this way, the difference between the edges of the comparison signal Data_TDC and the reference signal CLK_TDC can be used to determine the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB. When the code value Q is always logic "0", that is, the logic level of the code value is low, it is considered that the edge of the reference signal CLK_TDC is earlier than the edge of the corresponding internal signal or is aligned with the edge of the internal signal. After the delay process, the edge time of the comparison signal Data_TDC is delayed, so that the edge difference between the reference signal CLK_TDC and the delayed comparison signal Data_TDC is reduced; when the code value jumps from logic "0" to logic "1", that is, the logic level of the code value jumps from low level to high level, it is considered that the edge time of the reference signal CLK_TDC is later than the edge time of the corresponding internal signal, and there is no need to further delay the comparison signal Data_TDC.

[0107] Continue to refer Fig.10 and Fig.11 The mth comparison converter 2122 may include a first PMOS tube MP1, the source of the first PMOS tube MP1 is connected to the working power supply VDD, and the gate receives the reset signal LRSTB; a first NMOS tube MN1, the gate of the first NMOS tube MN1 receives the mth internal signal DATA_TDCm-1, and the drain of the first NMOS tube MN1 is connected to the drain of the first PMOS tube MP1; a second NMOS tube MN2, the gate of the second NMOS tube MN2 receives the reference signal CLK_TDC, the drain of the second NMOS tube MN2 is connected to the source of the first NMOS tube MN1, the source of the second NMOS tube MN2 is connected to the ground terminal GND, and the source of the first NMOS tube MN1 is used as the output node NET; a holding circuit 21, the input end of which is connected to the source of the first NMOS tube MN1, and is used to latch and output the signal of the output node NET after inversion processing; an even number of cascaded inverters 22, the input end of the inverter 22 at the first stage is connected to the output end of the holding circuit 21, and the output end of the inverter 22 at the last stage outputs the mth code value Q <m>.

[0108] The holding circuit 21 may be composed of two inverters connected end to end. After the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, the holding circuit 21 holds the signal of the output node NET for a target time and then outputs it in an inverted manner.

[0109] In some examples, the reset signal LRSTB may be the same signal as the aforementioned input signal DL_TDCRSTB.

[0110] The following will be combined Figures 10 to 12 , the working principle of the conversion circuit is explained:

[0111] When the edge timing of the reference signal CLK_TDC is aligned no later than the edge timing of the internal signal, it includes two cases: the edge timing of the reference signal CLK_TDC is earlier than the edge timing of the internal signal; and the edge timing of the reference signal CLK_TDC is aligned with the edge timing of the internal signal.

[0112] Taking the example that the edge timing of the xth internal signal Data_TDCx is aligned with the edge timing of the reference signal and the edge timing of the reference signal is earlier than the edge timing of the x+1th internal signal Data_TDCx+1, x is any positive integer less than n.

[0113] When the edge time of the reference signal CLK_TDC is earlier than the edge time of the x+1th internal signal Data_TDCx+1, before time T2, the level of the reference signal CLK_TDC is high, the level of the x+1th internal signal Data_TDCx+1 is low, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, and the level of the output node NET is pulled to be consistent with the working power supply, so that the output node NET is a logic high level "1", and the code value Q outputted after passing through the holding circuit 21 and the inverter 22 is<x+1> is logic "0"; during the period T2-T3, the level of the reference signal CLK_TDC is low, the level of the x+1th internal signal Data_TDCx+1 is low, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, and the level of the output node NET is pulled to be consistent with the working power supply, so that the output node NET is a logic high level "1", and the code value Q<x+1> is still logic "0"; after time T3, the level of the reference signal CLK_TDC is low, the level of the x+1th internal signal Data_TDCx+1 is high, and the output node NET is logic high "1". That is, the code value Q<x+1> The constant logic "0" can indicate that after the comparison signal DATA_TDC is delayed, the edge timing of the reference signal CLK_TDC is earlier than the edge timing of the corresponding internal signal.

[0114] When the edge timing of the reference signal CLK_TDC is aligned with the xth internal signal Data_TDCx, that is, the logic levels of the reference signal CLK_TDC and the xth internal signal Data_TDCx are always opposite, so that one of the first NMOS transistor MN1 and the second NMOS transistor MN2 is in a non-conductive state, so that the output node NET outputs a logic high level, and the code value Q <x>It is always logic "0", thereby indicating that the edge of the reference signal CLK_TDC is aligned with the edge of the x-th internal signal Data_TDCx.

[0115] Of course, there may be a situation where no internal signal is aligned with the edge of the reference signal, that is, the edge of the xth internal signal Data_TDCx is later than the edge of the reference signal, and the edge of the x+1th internal signal Data_TDCx+1 is earlier than the edge of the reference signal. Then, correspondingly, Q <x>From logic "0" to logic "1", Q<x+1> Always logic "0".

[0116] When the edge of the reference signal is later than the edge of the internal signal, taking the first internal signal DATA_TDC1 as an example, the working principle is as follows:

[0117] When the reset signal LRSTB is at a low level, the first PMOS transistor MP1 is turned on, and the logic level of the output node NET is "1", making the code value Q <1> is logic "0"; before time T1, at least one of the first NMOS transistor MN1 and the second NMOS transistor MN2 is not turned on. Although the first PMOS transistor MP1 changes from the on state to the off state, the level of the output node NET is latched by the holding circuit 21, so the code value Q <1> It is still logic "0". During the period of time T1-T2, the first PMOS transistor MP1 is turned off, the logic level of the first internal signal DATA_TDC1 is the same as the logic level of the reference signal CLK_TDC, and both are high level, that is, during the period of time T1-T2, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, the logic level of the output node NET is "0", and the signal of the output node NET passes through the holding circuit 21 and the inverter 22, and the output code value Q <1> After T2 time, the holding circuit 21 keeps the signal of the output node NET at a logic high level, and the corresponding code value Q <1> Maintained at logic "1".

[0118] That is to say, during the period when the reference signal CLK_TDC overlaps with the internal signal at a high level, i.e., the T2-T3 period, the corresponding code value Q has a logic "1" corresponding to the period. After the overlapping period, the code value Q can be maintained as logic "1" due to the action of the holding circuit 21.

[0119] If not otherwise specified, the internal signal described in the embodiments of the present disclosure refers to any signal from the first internal signal Data_TDC1 to the nth internal signal Data_TDCn in the internal signal set.

[0120] Fig.12 In the figure, t1 represents the delay amount of the first internal signal Data_TDC1 compared to the comparison signal Data_TDC, and t2 represents the delay amount of the second internal signal Data_TDC2 compared to the comparison signal Data_TDC. t1 is the third delay amount, and t2 is twice the third delay amount.

[0121] The control code Code is composed of all Q values, and a Q value that is always "0" is an invalid Q value, and a Q value that jumps from logic "0" to logic "1" is a valid Q value. After the n delay converters 212 all generate corresponding Q values, the control code Code composed of all valid Q values ​​is the target control code, and the sum of the third delay amounts of the delay converters 212 corresponding to all valid Q values ​​is the target delay amount.

[0122] In some embodiments, the third delay amount of each stage of the delay converter 212 is the same, that is, the comparison signal Data_TDC is delayed by the same third delay amount, so when the total delay amount of the comparison signal Data_TDC needs to be obtained, it is only necessary to multiply the third delay amount by the number of delays, which is conducive to simplifying the calculation design.

[0123] From the above analysis, we can see that the n code values ​​include the xth code value Q <x>and the x+1th code value Q<x+1> , where the xth code value is Q <x>is the code value with the latest transition edge, that is, the latest transition from logic "0" to logic "1". In other words, the xth code value Q <x>is the latest valid code value.<x+1> is a constant value, that is, the xth code value is always logical "0", in other words, the x+1th code value Q<x+1> is the earliest invalid code value. x is any positive integer less than n.

[0124] Fig.13 A block diagram of a circuit for generating identification signals. Fig.14 for Fig.13 Timing diagram of each signal in .

[0125] Combined with reference Fig.13 and Fig.14 The identification signal generating circuit 122 is configured to generate the x-th code value Q <x>and the x+1th code value Q<x+1> An XOR logic operation is performed to obtain a flag signal Flag, where x is a positive integer less than n.

[0126] Since the xth code value Q <x>Including logical "0" and logical "1" appearing in sequence, the x+1th code value Q<x+1> It is always logic "0". According to the XOR logic principle, the result of the XOR logic operation will also have logic "0" and logic "1" appearing in sequence. In other words, the identification signal Flag will also have a jump edge. Before the jump edge, the identification signal Flag is invalid, and after the jump edge appears, the identification signal Flag is valid.

[0127] In one example, the result of the XOR logic operation is used as the identification signal Flag, and the identification signal Flag changes from logic "0" to logic "1", that is, when a rising edge appears in the identification signal Flag, the identification signal Flag will be characterized to change from invalid to valid, wherein the identification signal Flag is invalid before the rising edge appears, and becomes a valid identification signal Flag after the rising edge appears.

[0128] In another example, the result of the XOR logic operation is inverted to obtain the identification signal Flag, and the identification signal Flag changes from logic "1" to logic "0", that is, when a falling edge occurs in the identification signal Flag, the identification signal Flag changes from invalid to valid, wherein the identification signal Flag is invalid before the falling edge occurs and becomes a valid identification signal Flag after the falling edge occurs.

[0129] That is, after the last valid Q value appears, the identification signal Flag changes from invalid to valid.

[0130] Fig.15 is a block diagram of the identification signal generating circuit 122, Fig.16 for Fig.15 Timing diagram of each signal in .

[0131] Combined with reference Fig.15 and Fig.16 As can be seen from the above discussion, the mth internal signal has a third delay compared to the m-1th internal signal. The identification signal generating circuit 122 may include a delay logic circuit 1221 , n first XOR logic circuits 1222 , and multiple stages of second XOR logic circuits 1223 .

[0132] The delay logic circuit 1221 is configured to receive the n code values ​​and delay each code value by a third delay amount, wherein the first code value Q <1> To the nth code value Q <n>The yth code value Q in <y>After delay, the yth delayed code value QD is obtained <y>, y is a positive integer less than n.

[0133] The third delay amount of the delay logic circuit 1221 is the same as the third delay amount of the aforementioned delay converter 212.<y+1> In the case of logic "1", the yth code value Q <y>The yth delayed code value QD obtained after delay <y>and the y+1th code value Q<y+1> The edge of the code is aligned, that is, the rising edge is aligned. <x>is the latest valid code value, the x+1th code value Q<x+1> Taking the earliest invalid code value as an example, the x-1th delayed code value QD <x-1>With the xth code value Q <x>The edge of the xth delay code value is QD <x>Has logic "1", and the x+1th code value is Q<x+1> Always logic "0". Fig.17 The present invention is a circuit structure diagram of an identification signal generating circuit.

[0134] Combined with reference Figures 15 to 17 The delay logic circuit 1221 may include n delay units 301, each delay unit 301 includes a cascaded first NAND gate and a second NAND gate, an input end of the first NAND gate receives a code value, and the other output end is connected to the working power supply VDD, an input end of the second NAND gate is connected to the output end of the first NAND gate, the other input end of the second NAND gate is connected to the working power supply VDD, and the output end of the second NAND gate outputs a corresponding delay code value.

[0135] The yth first XOR logic circuit 1222 is configured to receive the yth delayed code value QD <y>and the y+1th code value Q<y+1> , and perform an XOR operation.

[0136] The first XOR logic circuit 1222 may be a first XOR gate. Two input terminals of the first XOR gate receive the first delayed code value QD <1> and the second code value Q <2> , the two input ends of the other first XOR gate receive the second delayed code value QD <2> and the third code value Q <3> , and the two input ends of the first XOR gate receive the third delayed code value QD <3> and the 4th code value Q <4> , and so on, the last input end of the first XOR gate receives the nth delayed code value QD <n>, and the other input terminal is connected to the ground terminal GND.

[0137] If the yth delayed code value QD <y>and the y+1th code value Q<y+1> are both "0" or both "1", then the output terminal of the first XOR gate has a corresponding logic "0". <y>and the y+1th code value Q<y+1> If one of them is "0" and the other is "1", the output terminal of the first XOR gate has a logic "1" accordingly.

[0138] The second XOR logic circuit 1223 at each level performs a corresponding XOR operation based on the XOR operation result of the second XOR logic circuit 1223 at the previous level. The second XOR operation logic circuit 1223 at the last level outputs an identification signal Flag. The second XOR logic circuit 1223 at the first level performs a corresponding XOR operation based on the XOR operation result of the first XOR logic circuit 1222.

[0139] The second XOR logic circuit 1223 may be a second XOR gate. It is understandable that, in the case where the second XOR logic circuit 1223 lacks connection to the previous stage, an input terminal of the second XOR logic circuit 1223 is connected to the ground terminal GND.

[0140] The identification signal generating circuit 122 may further include a final inverter 302, the input end of the final inverter 302 is connected to the output end of the last second XOR logic circuit 1223, and the output end of the final inverter 302 outputs the identification signal Flag. Accordingly, a valid identification signal Flag is logic "0", and an invalid identification signal Flag is logic "1".

[0141] It can be understood that, in other examples, the output signal of the output terminal of the last-stage second XOR logic circuit 1223 can also be used as an identification signal Flag, and accordingly, a valid identification signal Flag is logic "1" and an invalid identification signal Flag is logic "0".

[0142] In addition, for ease of understanding, Fig.16 The result of the XOR logic operation of the code value and the corresponding delayed code value is identified in .

[0143] Fig.18 A schematic diagram of a circuit structure of a first delay circuit.

[0144] refer to Fig.18 The first delay circuit 101 includes: a plurality of cascaded first sub-delay circuits 111, each of which has a corresponding sub-delay amount, and the output end of the first sub-delay circuit 111 at the tail stage serves as the total output end of the first delay circuit 101, for outputting the first clock signal. A switch K is connected between the input end and the total output end of each first sub-delay circuit 111, wherein each switch K is turned on or off by a corresponding code value to adjust the number of the first sub-delay circuits 111 that actually play a delay role, thereby adjusting the first delay amount.

[0145] It should be noted that Fig.18 This is only an example of the first delay circuit, and the embodiment of the present disclosure does not limit the specific circuit of the first delay circuit.

[0146] Fig.19 Another block diagram of a delay locked loop circuit.

[0147] refer to Fig.19 The delay locked loop circuit may further include a phase detector 401 and a delay controller 402. The phase detector 401 is coupled to the replica circuit 104. The phase detector 401 is configured to detect the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB, and generate and output an adjustment signal Ctr corresponding to the phase difference; the delay controller 402 is coupled to the phase detector 401 and the delay detection feedback circuit 102. The delay controller 402 is configured to receive the adjustment signal Ctr and the identification signal Flag, and when the identification signal Flag is valid, adjust the second delay amount based on the adjustment signal Ctr, and when the identification signal Flag is invalid, set the second delay amount to 0 based on the default control signal.

[0148] That is, when the flag signal Flag is invalid, the second delay circuit 103 only receives and outputs the first clock signal without delaying it. When the flag signal Flag is valid, the second delay amount is adjusted based on the adjustment signal Ctr, and the first clock signal is delayed by the second delay amount to output the second clock signal.

[0149] Fig. 20 Another block diagram of a delay locked loop circuit.

[0150] refer to Fig. 20 The delay locked loop circuit may further include a clock buffer 61, a phase divider 62, a frequency divider 63 and a first duty cycle regulator 64 connected in sequence.

[0151] The clock buffer 61 receives an external clock signal, and the phase splitter 62 and the frequency divider 63 respectively perform phase splitting and frequency division processing on the received external clock signal to obtain a reference clock signal. The first duty cycle regulator 64 is used to adjust the duty cycle of the reference clock signal CLKREF to 50%, which is beneficial for the first delay circuit 101 and the second delay circuit 102 to compensate for the delay of the reference clock signal CLKREF.

[0152] Based on this, the first delay circuit 101 first performs a compensation delay on the reference clock signal CLKREF and outputs the first clock signal; before the identification signal Flag is valid, the second delay circuit 103 outputs the first clock signal. After the first clock signal is output through the replica circuit 104, a feedback clock signal CLKFB is generated.

[0153] The control code Code represents the actual delay amount of the feedback clock signal CLKFB compared to the reference clock signal CLKREF. In this way, the first delay circuit 101 can compensate the reference clock signal CLKREF based on the actual delay amount of the reference clock signal CLKREF, so that the phase between the output received feedback clock signal CLKFB and the reference clock signal CLKREF is reduced or is 0.

[0154] The phase detector 401 is used to compare the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB. The delay controller 402 obtains a control signal (not shown) and an adjustment signal Ctr based on the phase difference. The adjustment signal Ctr is used to input the second delay circuit 103, and after the identification signal Flag is valid, the second delay circuit 103 responds to the adjustment signal Ctr to perform delay compensation on the first clock signal CLK_1 and outputs the second clock signal CLK_2; when the identification signal Flag is valid and the second delay circuit 103 still cannot adjust the phase of the reference clock signal CLKREF and the feedback clock signal CLKFB to be the same after performing multiple delay compensation on the first clock signal CLK_1, the control signal is input into the first delay circuit 101, so that the first delay circuit 101 responds to the control signal to perform delay compensation on the reference clock signal CLKREF and outputs the first clock signal CLK_1. After the compensation, the second clock signal CLK_2 is outputted via the replica circuit 104 to generate the feedback clock signal CLKFB. Then the phase detector 401 compares the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB again, and repeats the above steps until the phases of the reference clock signal CLKREF and the feedback clock signal CLKFB are the same.

[0155] Continue to refer Fig. 20 The delay locked loop circuit may further include: a second duty cycle regulator 65 and a driving circuit 66 connected to the second duty cycle regulator 65. The second duty cycle regulator 65 is connected to the output end of the second delay circuit 103, and the output end of the driving circuit 66 is connected to the replica circuit 104. The output end of the driving circuit 66 is connected to the transmission path 67, and the transmission path 67 receives the clock signal output by the driving circuit 66 and transmits it to the address where the clock signal is required, and the clock signal reaching the address is the target clock signal.

[0156] From the above analysis, it can be seen that in the embodiment of the present disclosure, the second delay circuit will only perform the delay operation after the first delay circuit locks the target delay amount, which is beneficial to reducing the actual working time of the second delay circuit and reducing the power consumption of the delay phase-locked loop circuit.

[0157] The present disclosure also provides a storage device, including the delay locked loop circuit of any of the above embodiments. It should be noted that the same or corresponding parts as the above embodiments can refer to the description of the above embodiments, and will not be repeated below.

[0158] The memory device may be a random access memory device (RAM), a read-only memory device (ROM), a state-of-the-art random access memory device (SRAM), a dynamic random access memory device (DRAM), a synchronous dynamic random access memory device (SDRAM), a resistive random access memory device (RRAM), a double data rate memory device (DDR), a low power double data rate memory device (LPDDR), a phase change memory device (PCM), or a flash memory device.

[0159] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.< / y> < / y> < / n> < / y> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / n> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / m> < / m> < / x> < / x> < / x> < / m> < / n> < / m> < / m> < / n> < / n>

Claims

1. A delay locked loop circuit, characterized in that: include: A first delay circuit is configured to delay a reference clock signal based on a control code to generate and output a first clock signal having a first delay amount; A delay detection feedback circuit is coupled to the first delay circuit and is configured to generate a corresponding control code based on a phase difference between a feedback clock signal and the reference clock signal, and output the control code to the first delay circuit to adjust the first delay amount; after detecting that the phase difference meets expectations, the current control code is latched as a target control code, and a valid identification signal is output; wherein the first delay circuit locks the first delay amount corresponding to the target control code as the target delay amount; a second delay circuit, coupled to the first delay circuit and the delay detection feedback circuit, configured to generate and output a second clock signal based on the first clock signal and the identification signal; wherein, before the delay detection feedback circuit outputs the valid identification signal, the first clock signal is output as the second clock signal, and after the delay detection feedback circuit outputs the valid identification signal, a delay operation is performed on the first clock signal having the target delay amount to generate and output a second clock signal having a second delay amount; the delay fineness of the second delay circuit is greater than the delay fineness of the first delay circuit; The replica circuit is coupled to the second delay circuit and the delay detection feedback circuit, and is configured to delay the second clock signal by a preset delay amount to generate and output the feedback clock signal.

2. The delay locked loop circuit according to claim 1, wherein: The delay detection feedback circuit comprises: The phase detection circuit is configured to receive the feedback clock signal and the reference clock signal, generate and output a comparison signal and a reference signal, wherein the edge difference between the comparison signal and the reference signal represents the phase difference; and delay the comparison signal n times to obtain an internal signal set including a first internal signal to an nth internal signal, compare the edge difference between each internal signal in the internal signal set and the reference signal, and output n code values, wherein each code value represents each comparison result, and the n code values ​​constitute the control code, where n is an integer greater than or equal to 2; The identification signal generating circuit is configured to receive the n code values ​​and generate the identification signal based on the n code values.

3. The delay locked loop circuit according to claim 2, characterized in that: The phase detection circuit is also configured such that, when the edge of the reference signal is no later than the edge of the mth internal signal, the code value corresponding to the mth internal signal is always logic "0"; when the edge of the reference signal is later than the edge of the mth internal signal, the code value corresponding to the mth internal signal jumps from logic "0" to logic "1", where m is a positive integer less than or equal to n.

4. The delay locked loop circuit according to claim 2 or 3, characterized in that: The n code values ​​include: an xth code value and an x+1th code value, wherein the xth code value is the code value at which a transition edge appears the latest, and the x+1th code value is a constant value; the identification signal generating circuit is configured to perform an XOR logic operation on the xth code value and the x+1th code value to obtain the identification signal, where x is a positive integer less than n.

5. The delay locked loop circuit according to claim 4, characterized in that: The mth internal signal has a third delay compared to the m-1th internal signal, where m is a positive integer less than or equal to n; the identification signal generating circuit comprises: A delay logic circuit is configured to receive the n code values ​​and delay each code value by the third delay amount, wherein a yth code value among the first code value to the nth code value is delayed to obtain a yth delayed code value, where y is a positive integer less than n; n-1 first XOR logic circuits, the yth first XOR logic circuit being configured to receive the yth delayed code value and the y+1th code value and perform an XOR operation; A plurality of levels of second XOR logic circuits, each level of the second XOR logic circuit performs a corresponding XOR operation based on the XOR operation result of the second XOR logic circuit of the previous level, the second XOR operation logic circuit of the last level outputs the identification signal, and the second XOR logic circuit at the first level performs a corresponding XOR operation based on the XOR operation result of the first XOR logic circuit.

6. The delay locked loop circuit according to claim 1, characterized in that: The delay locked loop circuit also includes: a phase detector, coupled to the replica circuit, configured to detect a phase difference between the reference clock signal and the feedback clock signal, and to generate and output an adjustment signal corresponding to the phase difference; A delay controller is coupled to the phase detector and the delay detection feedback circuit, and is configured to receive the adjustment signal and the identification signal, and when the identification signal is valid, adjust the second delay amount based on the adjustment signal, and when the identification signal is invalid, set the second delay amount to 0 based on a default control signal.

7. The delay locked loop circuit according to claim 2, characterized in that: The phase detection circuit comprises: A receiving circuit, configured to receive the feedback clock signal and the reference clock signal, generate and output the comparison signal and the reference signal; The conversion circuit is configured to receive the comparison signal and the reference signal, delay the comparison signal n times to obtain the internal signal set, and output the n code values.

8. The delay locked loop circuit according to claim 7, characterized in that: The receiving circuit comprises: A first sampling circuit is configured to receive an input signal and sample the input signal in response to the feedback clock signal to generate and output the comparison signal and the complementary comparison signal which are in an anti-phase relationship with each other; The second sampling circuit is configured to receive the complementary comparison signal and sample the complementary comparison signal in response to the reference clock signal to generate and output the reference signal.

9. The delay locked loop circuit according to claim 8, characterized in that: The first sampling circuit comprises: A plurality of cascaded first flip-flops, wherein a clock terminal of each stage of the first flip-flops receives the feedback clock signal, a data input terminal of each stage of the first flip-flops is connected to a positive phase output terminal of the first flip-flop of the previous stage, an input data terminal of the first stage of the first flip-flops receives the input signal, and a positive phase output terminal and a negative phase output terminal of the first flip-flops of the last stage output the comparison signal and the complementary comparison signal respectively; The second sampling circuit comprises: A second trigger, wherein a data input terminal of the second trigger is connected to an inverting output terminal of the first trigger of the last stage, and a clock terminal of the second trigger receives the reference clock signal.

10. The delay locked loop circuit according to claim 7, characterized in that: The conversion circuit comprises: A delay converter comprising n cascaded delay converters from a first delay converter to an nth delay converter, wherein the mth delay converter is configured to receive an m-1th internal signal output by an m-1th delay converter, delay the m-1th internal signal by a third delay amount to generate an mth internal signal, and output the mth internal signal to an m+1th delay converter; wherein the first delay converter receives the comparison signal and delays the comparison signal by the preset delay amount to generate and output the first internal signal; The mth delay converter is further configured to compare the edge difference between the reference signal and the mth internal signal, and output a corresponding mth code value, wherein the mth code value indicates whether the edge of the reference signal is not later than the edge of the mth internal signal.

11. The delay locked loop circuit according to claim 10, characterized in that: The third delay amount of each of the delay converters is the same.

12. The delay locked loop circuit according to claim 10, characterized in that: The mth delay converter comprises: The mth delayer is configured to receive the m-1th internal signal, delay it by the third delay amount, and generate and output the mth internal signal; The mth comparison converter is configured to receive and compare the mth internal signal and the reference signal, and output the mth code value.

13. The delay locked loop circuit according to claim 12, characterized in that: The mth comparison converter comprises: A first PMOS tube, wherein a source of the first PMOS tube is connected to a working power supply, and a gate receives a reset signal; a first NMOS transistor, wherein a gate of the first NMOS transistor receives the mth internal signal, a drain of the first NMOS transistor is connected to a drain of the first PMOS transistor, and a source of the first NMOS transistor serves as an output node; a second NMOS transistor, wherein a gate of the second NMOS transistor receives the reference signal, a drain of the second NMOS transistor is connected to a source of the first NMOS transistor, and a source of the second NMOS transistor is connected to a ground terminal; A holding circuit, wherein an input end of the holding circuit is connected to the output node, and is used to invert the signal of the output node, latch it, and output it after the first NMOS transistor and the second NMOS transistor are both turned on; There are an even number of cascaded inverters, the output end of the holding circuit is connected to the input end of the inverter at the first stage, and the output end of the inverter at the last stage outputs the mth code value.

14. A storage device, characterized in that: Comprising a delay locked loop circuit as described in any one of claims 1-13.

Images