Scaling analog-to-digital converter
By combining coarse quantization, digital logic, fine quantization and noise coupling modules in the scaled analog-to-digital converter, power consumption and stability problems in traditional technologies are solved, and high-precision and energy-efficient analog-to-digital conversion effects are achieved.
Patent Information
- Application Number
- CN202411413617.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-07
AI Technical Summary
When traditional scaling analog-to-digital converters pursue accuracy and bandwidth, power consumption increases, and the higher-order ΔΣ ADC loop is difficult to stabilize, resulting in a reduction in input dynamic range and an increase in design difficulty.
Adopt a combined structure of coarse quantization module, digital logic module, fine quantization module and noise coupling module. The noise coupling module is used to feed the quantization noise to the fine quantization module, increasing the first-order noise shaping capability, avoiding the use of high-power operational amplifiers, and improving the system stability.
It achieves the accuracy equivalent to higher-order ΔΣ ADCs at smaller power consumption, improves energy efficiency, and avoids power consumption and stability problems caused by the increase in the number of operational amplifiers.
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Figure CN119276269A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and more specifically, to a scaling analog-to-digital converter. Background Art
[0002] Analog-to-Digital Converter (ADC) is widely used in sensors such as temperature, humidity, pressure and biology. It converts analog signals into digital signals before sending them to digital circuits for complex storage and calculation. Therefore, as the first-level processing circuit for the target signal, the conversion accuracy and bandwidth of the ADC determine the main performance of the sensor. In the above application environment, the analog signal is usually very small in amplitude and changes slowly, and the ADC is often required to have an accuracy of more than 16 bits and a bandwidth of about 1KHz. In addition, the sensors in the above environment are usually powered by batteries and have limited heat dissipation capabilities, so the ADC is required to have lower power consumption. The improvement of ADC accuracy and bandwidth comes at the cost of power consumption. It is not possible to simply pursue one of the accuracy or bandwidth, but to reduce the overall power consumption through improvements at the architecture or circuit level while ensuring accuracy and bandwidth.
[0003] In a zooming analog-to-digital converter, its performance is mainly determined by the ΔΣ ADC (Delta-sigma ADC), and its accuracy depends on the order of the noise transfer function (NTF) of the modulator. The higher the order, the more quantization noise can be shaped out of the signal band. The traditional ZOOM ADC increases the order of the NTF by increasing the number of integrators in the ΔΣ ADC, thereby improving the overall ADC accuracy. However, the disadvantage of this method is that more operational amplifiers are needed to build cascaded integrators. The operational amplifier is usually the module with the highest power consumption in the circuit. Therefore, the traditional method greatly increases the power consumption in pursuit of accuracy, weakening the high energy efficiency advantage of the ZOOM ADC. At the same time, the loop of the high-order ΔΣ ADC is difficult to stabilize, which will lead to a smaller input dynamic range and increased design difficulty. Summary of the invention
[0004] 1. Technical issues to be resolved
[0005] The present disclosure provides a scaling analog-to-digital converter, which is used to at least partially solve one of the above-mentioned technical problems.
[0006] (II) Technical solution
[0007] The present disclosure provides a scaling analog-to-digital converter, which includes: a coarse quantization module, which is used to convert an input analog signal and output a residual signal and a first digital signal; a digital logic module, which is used to expand the first digital signal and output a first reference voltage and a second reference voltage; a fine quantization module, which is used to fine quantize the residual signal and output a second digital signal or a third digital signal, wherein the second digital signal is fed back to the fine quantization module after being processed by a noise coupling module; a noise coupling module, which is used to generate a feedback signal based on the second digital signal; wherein the feedback signal is used to reduce quantization noise in the fine quantization process; and an output module, which is used to generate an output result based on the first digital signal and the third digital signal.
[0008] According to an embodiment of the present disclosure, the coarse quantization module includes: an N-bit analog-to-digital converter, which is used to sample, convert and quantize the input analog signal, and output a residual signal and a first digital signal, wherein the first digital signal is a digital expression of the input analog signal, the residual signal is output to the fine quantization module, and the first digital signal is output to the digital logic module.
[0009] According to an embodiment of the present disclosure, the digital logic module includes: a digital logic circuit for converting a first digital signal into a fourth digital signal and determining a first reference voltage and a second reference voltage based on the fourth digital signal; wherein the data range of the fourth digital signal is greater than that of the first digital signal.
[0010] According to an embodiment of the present disclosure, a fine quantization module includes: a first digital-to-analog converter, used to convert a second digital signal into a first analog signal based on a first reference voltage and a second reference voltage; an integrator group, used to shape the input analog signal, the residual signal and the first analog signal to obtain a first shaped signal and a second shaped signal; an adder, used to integrate the first shaped signal, the second shaped signal and the feedback signal to obtain a second analog signal; and a quantizer, used to convert the second analog signal and output a second digital signal or a third digital signal.
[0011] According to an embodiment of the present disclosure, the feedback signal includes at least a first feedback signal and a third feedback signal, and the noise coupling module includes: an analog delay unit, used to delay the second analog signal to obtain a first feedback signal; a digital delay unit, used to delay the second digital signal to obtain a second feedback signal; and a second digital-to-analog converter, used to convert the second feedback signal into a third feedback signal.
[0012] According to an embodiment of the present disclosure, the conversion coefficient of the second digital-to-analog converter is determined based on the second digital signal output by the quantizer in the previous cycle.
[0013] According to an embodiment of the present disclosure, the analog delay unit includes: a first capacitor array and a second capacitor array, wherein the first capacitor array and the second capacitor array have the same structure, and signal delay is achieved through capacitors, wherein the state of the capacitors is determined based on the phase.
[0014] According to an embodiment of the present disclosure, the digital delay unit includes: a D flip-flop, which is used to delay a digital signal.
[0015] According to an embodiment of the present disclosure, multiple cycles of fine quantization processing are performed in the fine quantization module. When the fine quantization processing cycle meets a preset condition, the second digital signal output by the quantizer of the current cycle is output to the output module as the third digital signal.
[0016] According to an embodiment of the present disclosure, an output module obtains an output result by combining a first digital signal and a third digital signal, wherein the combination method is determined based on the value of the third digital signal; when the value of the third digital signal is 1, the first content in the first digital signal is taken; when the value of the third digital signal is 0, the second content in the first digital signal is taken; and the output result is obtained by arranging the first content or the second content in sequence.
[0017] (III) Beneficial effects
[0018] The scaling analog-to-digital converter provided by the present disclosure includes at least the following beneficial effects:
[0019] By adding a noise coupling module, the quantizer input and output are subtracted to obtain the quantization noise, and then the quantization noise is fed back to the quantizer input after a delay of one clock cycle. In this way, a first-order noise shaping is added on the basis of the original noise transfer function NTF, avoiding the use of high-power operational amplifiers, increasing the shaping order while avoiding the increase in the number of operational amplifiers, effectively improving the stability of the system, and thus achieving the same accuracy as a high-order ΔΣ ADC at a lower power consumption cost, achieving higher energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0021] Figure 1 The module connection diagram of the scaling analog-to-digital converter according to an embodiment of the present disclosure is schematically shown;
[0022] Figure 2 A schematic diagram of a scaling analog-to-digital converter according to an embodiment of the present disclosure is shown;
[0023] Figure 3A schematic diagram schematically shows the magnitude relationship between the first digital signal and the input analog signal in an embodiment of the present disclosure;
[0024] Figure 4 A schematic diagram schematically shows a digital logic module in an embodiment of the present disclosure performing boundary expansion;
[0025] Figure 5 The circuit structure diagram of the noise coupling module in the embodiment of the present disclosure is schematically shown;
[0026] Figure 6 The mathematical model of a scaling analog-to-digital converter according to an embodiment of the present disclosure is schematically shown;
[0027] Figure 7 The schematic diagram shows the architecture of the second digital-to-analog converter in the noise coupling module in the embodiment of the present disclosure;
[0028] Figure 8 The circuit structure diagram of the analog delay unit in the embodiment of the present disclosure is schematically shown;
[0029] Fig. 9 The working principle of the noise coupling module in the embodiment of the present disclosure is schematically shown;
[0030] Fig.10 Schematically shows the relevant timing of noise coupling of an embodiment of the present disclosure;
[0031] Fig.11 The effect diagram of the scaling analog-to-digital converter of the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.
[0033] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.
[0034] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0035] In the description of the present disclosure, it is necessary to understand that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0036] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. The shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual size, proportion, and actual positional relationship. In addition, in the claims, any reference symbol between brackets shall not be construed as a limitation to the claims.
[0037] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0039] It should be noted that the signals mentioned in the present disclosure can be input to the corresponding modules in the form of differential signals.
[0040] Figure 1 The figure schematically shows a module connection diagram of a scaling analog-to-digital converter according to an embodiment of the present disclosure.
[0041] like Figure 1 As shown, the scaling analog-to-digital converter at least includes a coarse quantization module, a digital logic module, a fine quantization module, a noise coupling module and an output module.
[0042] The coarse quantization module is used to convert the input analog signal and output a residual signal and a first digital signal.
[0043] The digital logic module is used to expand and decode the first digital signal and output a first reference voltage and a second reference voltage.
[0044] The fine quantization module is used to finely quantize the residual signal based on the first reference voltage and the second reference voltage, and output a second digital signal or a third digital signal, wherein the second digital signal is fed back to the fine quantization module after being processed by the noise coupling module.
[0045] The noise coupling module is used to generate a feedback signal based on the second digital signal; wherein the quantization noise in the fine quantization process is reduced.
[0046] The output module is used to generate an output result based on the first digital signal and the third digital signal.
[0047] Figure 2 The structure diagram of a scaling analog-to-digital converter according to an embodiment of the present disclosure is schematically shown.
[0048] The following combination Figure 2 Each module in the scaling analog-to-digital converter disclosed in the present invention is further introduced.
[0049] The coarse quantization module includes: an N-bit analog-to-digital converter, which is used to sample and convert the input signal and quantize it, and output a residual signal and a first digital signal. The N-bit analog-to-digital converter used in the embodiment of the present disclosure may be an asynchronous successive approximation analog-to-digital converter (SAR ADC).
[0050] The first digital signal is a digital expression of the input analog signal, the residual signal is output to the fine quantization module, and the first digital signal is output to the digital logic module.
[0051] Specifically, the coarse quantization module converts the input signal Vin to generate an N-bit output code DOUT <n:1>(i.e. the first digital signal, where the lowest bit is the lowest bit for DOUT <1> , the highest bit is DOUT <n>). The decimal corresponding to the N-digit code is recorded as K, then:
[0052]
[0053] Figure 3 The schematic diagram schematically shows the magnitude relationship between the first digital signal and the input analog signal in the embodiment of the present disclosure.
[0054] like Figure 3 As shown in the figure, K is the decimal representation of the N-bit binary number obtained after Vin is converted by the coarse quantization module, which can directly reflect the relative position of Vin in the ADC quantization range. , is the quantization step of the N-bit SAR ADC.
[0055] Figure 4 The schematic diagram of expanding the digital logic module in the embodiment of the present disclosure is schematically shown.
[0056] If the ADC is ideal and linear, there will be a direct linear relationship between K and Vin, where K is the value obtained by scaling Vin and quantizing it to the nearest N-bit binary number. However, in the actual SAR conversion process, due to the non-ideal characteristics of the SAR ADC, such as the offset error of the capacitor or comparator, the coarse quantization result K may deviate from the input signal, such as Figure 4 In this case, the sigma delta ADC in the fine quantization stage will be saturated, greatly reducing the system accuracy.
[0057] Therefore, the present disclosure proposes to expand the first digital signal (i.e., the coarse quantization result K) based on the digital logic module, convert the first digital signal into a fourth digital signal (i.e., the coarse quantization result K after expansion), and determine the first reference voltage and the second reference voltage based on the fourth digital signal. The data range of the fourth digital signal is greater than that of the first digital signal, and the first digital signal is contained in the fourth digital signal.
[0058] Use digital logic circuit to expand the first reference voltage V refp and the second reference voltage V refn , where the first reference voltage V refp =(K+M+1)×LSB SAR , the second reference voltage V refn =(KM)×LSB SAR , M is the expansion coefficient.
[0059] The coarse quantization result K after expansion is as follows Figure 4 As shown in (b), by expanding the coarse quantization result K, it can be ensured that the SARADC quantization result always follows the input signal and reduces the quantization error.
[0060] The fine quantization module includes a first digital-to-analog converter, an integrator group, an adder and a quantizer.
[0061] The first digital-to-analog converter is used to convert the second digital signal into a first analog signal based on the first reference voltage and the second reference voltage.
[0062] The integrator group is used to shape the input analog signal, the residual signal and the first analog signal to obtain a first shaped signal and a second shaped signal.
[0063] In some embodiments, the integrator group includes a first integrator and a second integrator, and the first integrator and the second integrator perform second-order noise shaping on the input analog signal, the residual signal and the first analog signal. The input signal of the integrator is in the form of double-ended inversion, the first integrator shapes the input residual signal and the first analog signal to obtain a first shaped signal, and then uses the first shaped signal as the input of the second integrator, and the second integrator further shapes the first shaped signal to obtain a second shaped signal.
[0064] The adder is used to integrate the first shaped signal, the second shaped signal and the feedback signal to obtain a second analog signal.
[0065] The quantizer is used to convert the second analog signal and output a second digital signal or a third digital signal.
[0066] Figure 5 The circuit structure diagram of the noise coupling module in the embodiment of the present disclosure is schematically shown.
[0067] like Figure 5 As shown, the noise coupling module includes an analog delay unit, a digital delay unit and a second digital-to-analog converter.
[0068] The analog delay unit is used to delay the second analog signal to obtain a first feedback signal.
[0069] The digital delay unit is used to delay the second digital signal to obtain a second feedback signal.
[0070] The second DAC (i.e. Figure 5 DAC2 in the embodiment of the present invention is used to convert the second feedback signal into a third feedback signal.
[0071] The conversion coefficient of the second digital-to-analog converter is determined based on the second digital signal output by the quantizer in the previous cycle. The analog delay unit is composed of two sets of capacitors and switches controlled by related timing signals: C H1 , Φ even , Φ 2e , Φ 1o , Φ 1e With C H2 , Φ odd , Φ 2o , Φ 1o , Φ 1e The digital delay is realized by a D flip-flop. DAC2 is composed of positive and negative reference voltages V REFP 、V REFN and signal BsD, , Φ 1o , Φ2 controlled switch.
[0072] The present disclosure only adds a passive switched capacitor circuit to the input and output of the quantizer, and does not affect the original integrator coefficient and architecture, and thus does not affect the stability of the original loop.
[0073] Figure 6 The mathematical model of a scaling analog-to-digital converter according to an embodiment of the present disclosure is schematically shown.
[0074] Figure 7 The schematic diagram shows the architecture of the second digital-to-analog converter in the noise coupling module in the embodiment of the present disclosure.
[0075] The following combination Figure 6 , Figure 7 The working principles of the fine quantization module and the noise coupling module are further explained.
[0076] like Figure 6 As shown, the residual signal Q input to the integrator group SAR The range is Figure 4 (b) [-(M+1)LSB SAR , (M+1)LSB SAR ]. The difference between the residual signal and the feedback signal is subjected to noise shaping by the integrator group, and its output value is used as the input of the quantizer.
[0077] The quantizer and the second DAC substantially quantize the quantizer input to (M+1)LSBs. SAR or -(M+1)LSB SAR , as a feedback signal to complete fine quantization. Therefore, in the above process, the quantization noise QSD of fine quantization should be the quantizer input minus the output of the second digital-to-analog converter (M+1)LSB SAR or -(M+1)LSB SAR .
[0078] like Figure 7 As shown, the second digital-to-analog converter is connected through a capacitor C c With the summing capacitor C s The second feedback signal output by the digital delay unit is converted into a third feedback signal, namely (M+1)LSB SAR AND-(M+1)LSB SAR Among them, the capacitor C c The value of is related to the expansion coefficient M.
[0079] When the second feedback signal B output by the digital delay unit in the previous cycle S D is 1, that is, the first DAC output at the in-phase end is (K+M+1)LSB SAR The second DAC should generate (M+1)LSBs SAR Used for noise coupling.
[0080] When the second feedback signal B output by the word delay unit of the previous cycle S D is 0, that is, the first digital-to-analog converter output (KM) LSB at the inverting end SAR When the second DAC generates -(M+1)LSB SAR .
[0081] Wherein, different from the first reference voltage V refp and the second reference voltage V refn ,,V in the second DAC REFP 、V REFN is the reference voltage of the entire ZOOM ADC, V CM =(V REFP +V REFN ) / 2 is the common mode voltage of the ZOOM ADC.
[0082] Take the in-phase terminal DAC2-P when BsD=1 as an example: In the Φ2 phase, the summing capacitor is reset and the charge is cleared. c One end is connected to the common mode, and the other end is connected to the op amp input, and the charge is also cleared. s With C c The total charge on is:
[0083] Q P2 =0
[0084] In the Φ1 phase, assuming that the voltage at the output of the op amp, that is, the summed voltage, is V out , then C s The charge on is: (V out -V CM )×C s ; C c One end is connected to V REFP , the other end is connected to the virtual ground V CM , then C c The charge on is: (V REFP -V CM )×Cc=2×(V REFP -V CM )×Cc / 2=(V REFP -V REFN )× Cc / 2.
[0085] So at this time C s With C c The total charge on is:
[0086]
[0087] According to the law of charge conservation, we can get:
[0088]
[0089] At this time, the feedback value of DAC2-P should be (M+1) LSB SAR , then:
[0090]
[0091] Get C c Should meet:
[0092]
[0093] The second feedback signal B S D is generated by the second digital signal Bs output by the quantizer through a digital delay unit, thereby realizing digital delay, and based on the second digital-to-analog converter, the second feedback signal generated by the digital delay unit is converted into a third feedback signal, wherein the third feedback signal is an analog signal.
[0094] Figure 8 The circuit structure diagram of the analog delay unit in the embodiment of the present disclosure is schematically shown.
[0095] like Figure 8 As shown, the analog delay unit includes a first capacitor array and a second capacitor array, wherein the first capacitor array and the second capacitor array have the same structure, and each capacitor array has two groups of capacitors and switches controlled by related timing signals: C H1 , Φ even , Φ 2e , Φ 1o , Φ 1e With C H2 , Φ odd , Φ 2o , Φ 1o , Φ 1e The analog delay unit realizes signal delay through a capacitor, wherein the state of the capacitor is determined based on the phase.
[0096] C H1 , C H2 , C s In Φ even The workflow under the same timing is shown in Table 1.
[0097] Table 1 Capacitor working status in noise coupling module
[0098] <![CDATA[Φ 2e ]]> <![CDATA[Φ 1e ]]> <![CDATA[Φ 2o ]]> <![CDATA[Φ 1o ]]> <![CDATA[C H1 ]]> Reset sampling Floating Sum <![CDATA[C H2 ]]> Floating Sum Reset sampling <![CDATA[C s ]]> Reset Sum Reset Sum
[0099] Fig. 9 The working principle of the noise coupling module of the embodiment of the present disclosure is schematically shown.
[0100] Fig.10 The relevant timing of noise coupling in the embodiment of the present disclosure is schematically shown.
[0101] The following combination Fig. 9 and Fig.10 , with the non-inverting end of C H1 Taking capacitor as an example, the working principle of the noise coupling module is explained.
[0102] In Φ 2e Phase, C H1 With C s The two ends are short-circuited, the charge is cleared, and the device enters the reset state.
[0103] In Φ 1e Phase, Φ even Open, then C H1 One side is connected to the common mode voltage, and the other side is connected to the quantizer input, so that the quantizer input V in (n-1) sampling to C H1 At this time C H1 The total charge is:
[0104]
[0105] In Φ 2o Phase, C H1 The two ends are floating to achieve a one-cycle analog delay.
[0106] In Φ 1o Phase, C H1 The left side is connected to the amplifier input, and the right side is connected to V CM , due to virtual ground, C H1 All the charges on the s Assume that the charge transfer causes C s The voltage change is ΔV(n). When C s = C H1 When , we have:
[0107]
[0108] get:
[0109]
[0110] This will cause the comparator input V of the (n-1)th cycle to in (n-1) is delayed for one cycle and participates in the adder operation in the nth cycle.
[0111] C H2 With C H1 The working principle is the same as C H1 Work alternately to complete the simulation delay of each cycle.
[0112] In some embodiments, a plurality of cycles of fine quantization processing are performed in the fine quantization module. When the fine quantization cycle meets the preset condition, the second digital signal Bs output by the quantizer of the current cycle is output to the output module as the third digital signal. <n:1>and the third digital signal to obtain an output result, wherein the combination method is determined based on the value of the third digital signal.
[0113] When the value of the first digital signal is 1, the first content in the first digital signal is taken, and all N-bit digital codes in the first content are arranged in sequence to obtain the output result. In the specific implementation process, when the third digital signal Bs=1, the first content is DOUT <n:1>+M+1.
[0114] When the first digital signal value is 0, the second content in the first digital signal is taken, and all N-bit digital codes in the second content are arranged in sequence to obtain an output result. In a specific implementation process, when the third digital signal Bs=0, the second content DOUT<6:1>-M.
[0115] In summary, the input of the quantizer and the delayed output of the quantizer are respectively sent to the adder in the form of analog voltage to obtain the difference through the analog delay unit, the digital delay unit and the second digital-to-analog converter, and the delayed quantization noise is obtained, and noise coupling is realized in ZOOMADC. On the one hand, the noise shaping ability of the zooming analog-to-digital converter is improved by the noise coupling module, and the accuracy is effectively improved. On the other hand, the present disclosure adopts the noise coupling module for shaping, which can effectively avoid the problems of greatly increased power consumption and system instability caused by the increase of cascaded integrators. The present disclosure only needs to add passive switches and capacitors to the quantizer to increase the first-order noise shaping capability, obtain higher accuracy at a lower power consumption cost, and thus improve the energy efficiency of the analog-to-digital converter.
[0116] Fig.11 The effect diagram of the scaling analog-to-digital converter of the embodiment of the present disclosure is schematically shown.
[0117] Fig.11 A is the FFT spectrum of the analog-to-digital converter output when there is no noise coupling module. Fig.11 B is the FFT spectrum of the analog-to-digital converter output when there is a noise coupling module. It can be seen that when the analog-to-digital converter has a noise coupling module, its accuracy is improved by 5dB.
[0118] Table 2 shows the circuit power consumption with and without the noise coupling module.
[0119] Table 2
[0120] Power consumption Noise-free coupling 65.88 μW Noise coupling 67.30 μW
[0121] According to Table 2, compared with the analog-to-digital converter without the noise coupling module, the analog-to-digital converter with the noise coupling module only increases the power consumption by 1.42 μW.
[0122] The energy efficiency index FOMs of the above analog-to-digital converters are calculated to obtain the energy efficiency index of each analog-to-digital coupler. , where ENOB is the effective number of bits of the analog-to-digital converter, reflecting the accuracy of the analog-to-digital converter; Bw is the bandwidth of the analog-to-digital converter, reflecting the speed of the analog-to-digital converter, and P is the power consumption of the analog-to-digital converter.
[0123] Through calculation, it can be obtained that the energy efficiency of the analog-to-digital converter when there is no noise coupling module is FOMs=174.81dB, and the energy efficiency of the analog-to-digital converter when there is a noise coupling module is FOMs=180.02dB, that is, the energy efficiency of the analog-to-digital converter provided by the embodiment of the present disclosure is significantly improved.
[0124] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all be included in the scope of protection of the present disclosure. < / n>
Claims
1. A scaling analog-to-digital converter, characterized in that: The system includes: A coarse quantization module, used for converting an input analog signal and outputting a residual signal and a first digital signal; A digital logic module, used for expanding the first digital signal and outputting a first reference voltage and a second reference voltage; A fine quantization module, used to perform fine quantization on the residual signal and output a second digital signal or a third digital signal, wherein the second digital signal is fed back to the fine quantization module after being processed by the noise coupling module; A noise coupling module, configured to generate a feedback signal based on the second digital signal; wherein the feedback signal is used to reduce quantization noise in a fine quantization process; An output module is used to generate an output result based on the first digital signal and the third digital signal.
2. The scaling analog-to-digital converter according to claim 1, characterized in that: The coarse quantization module comprises: An N-bit analog-to-digital converter is used to sample, convert and quantize an input analog signal, and output a residual signal and a first digital signal, wherein the first digital signal is a digital expression of the input analog signal, the residual signal is output to the fine quantization module, and the first digital signal is output to the digital logic module.
3. The scaling analog-to-digital converter according to claim 1, characterized in that: The digital logic module comprises: A digital logic circuit is used to convert the first digital signal into a fourth digital signal, and determine a first reference voltage and a second reference voltage based on the fourth digital signal; wherein the data range of the fourth digital signal is greater than that of the first digital signal.
4. The scaling analog-to-digital converter according to claim 3, characterized in that: The fine quantization module comprises: A first digital-to-analog converter, configured to convert the second digital signal into a first analog signal based on the first reference voltage and the second reference voltage; an integrator group, used for shaping the input analog signal, the residual signal and the first analog signal to obtain a first shaped signal and a second shaped signal; an adder, configured to integrate the first shaped signal, the second shaped signal and the feedback signal to obtain a second analog signal; A quantizer is used to convert the second analog signal and output a second digital signal or a third digital signal.
5. The scaling analog-to-digital converter according to claim 1, characterized in that: The feedback signal at least includes a first feedback signal and a third feedback signal, and the noise coupling module includes: An analog delay unit, used for delaying the second analog signal to obtain a first feedback signal; A digital delay unit, used for delaying the second digital signal to obtain a second feedback signal; The second digital-to-analog converter is used to convert the second feedback signal into a third feedback signal.
6. The scaling analog-to-digital converter according to claim 5, characterized in that: The conversion coefficient of the second digital-to-analog converter is determined based on the second digital signal output by the quantizer in the previous cycle.
7. The scaling analog-to-digital converter according to claim 5, characterized in that: The analog delay unit comprises: A first capacitor array and a second capacitor array, wherein the first capacitor array and the second capacitor array have the same structure, and signal delay is achieved through capacitors, wherein the state of the capacitors is determined based on the phase.
8. The scaling analog-to-digital converter according to claim 5, characterized in that: The digital delay unit comprises: D flip-flop is used to delay digital signals.
9. The scaling analog-to-digital converter according to claim 1, characterized in that: A plurality of cycles of fine quantization processing are performed in the fine quantization module. When the fine quantization processing cycle meets a preset condition, the second digital signal output by the quantizer of the current cycle is output to the output module as the third digital signal.
10. The scaling analog-to-digital converter according to claim 1, wherein: The output module obtains an output result by combining the first digital signal and the third digital signal, wherein the combination method is determined based on the value of the third digital signal; When the value of the third digital signal is 1, taking the first content of the first digital signal; When the value of the third digital signal is 0, the second content in the first digital signal is obtained; An output result is obtained by sequentially arranging the first content or the second content.