Enhanced nitride semiconductor transistor structure

Abstract

The invention relates to an enhanced nitride semiconductor transistor structure, which belongs to the technical field of semiconductors and comprises an epitaxial structure, the epitaxial structure comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the barrier layer, and a source electrode, a grid electrode and a drain electrode of the transistor structure are manufactured on the surface of the epitaxial structure. A cap layer on the barrier layer includes a polarized doped p-type nitride semiconductor structure, and an n-type nitride semiconductor structure thereover. According to the enhanced nitride semiconductor transistor structure, the p-type polarization doping structure is arranged in the cap layer, so that higher ionization charge and hole concentration compared with impurity doping can be realized, two-dimensional electron gas in the channel layer can be effectively exhausted, and meanwhile, the memory effect when Mg is doped with p-type nitride is avoided; a pn structure with a good interface is formed between the P-type polarization doping layer and the n-type layer above the P-type polarization doping layer, a commonly-used metal semiconductor Schottky contact grid electrode is replaced, the withstand voltage of the grid electrode is improved, and electric leakage of the grid electrode is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an enhanced nitride semiconductor transistor structure. Background Art

[0002] Compared with traditional silicon material devices, nitride semiconductor power devices have high breakdown electric field, are more energy-efficient, have more stable physical and chemical properties, can operate at higher ambient temperatures, have higher switching speeds and can reduce the volume and weight of application systems. They can be used in a wide range of fields such as various household appliances, electric vehicles, solar and wind energy and other new energy power generation, electric vehicles, robots, intelligent manufacturing industries, large data processing centers, etc.

[0003] At present, nitride transistor devices mainly adopt high electron mobility transistor (HEMT) structure, using Al Due to the discontinuity of the polarization electric field, a high-concentration two-dimensional electron gas is formed at the interface of the GaN barrier layer and the GaN channel layer. The two-dimensional electron gas has a high electron mobility and can significantly reduce the on-resistance of the device. However, due to the presence of the two-dimensional electron gas, the nitride transistor is a depletion-type (normally open) device. The channel is conductive without an external gate voltage. Considering the safety of use, an enhancement-type (normally closed) device is required. At present, there are two main technical routes for commercializing enhancement-type nitride transistors. One is to use a depletion-type nitride device and a normally-off silicon transistor to form a cascode cascade structure to achieve an enhancement-type function; the other is to grow a p-type GaN cap layer on the barrier layer to deplete the two-dimensional electron gas in the channel layer under the gate to achieve an enhancement-type. The presence of Si transistors in the cascode structure limits the performance of the device under high temperature and high frequency conditions, and has high requirements for the performance matching of nitride transistors and Si transistors, which will also increase the cost of the chip; the p-type GaN cap layer is used to achieve the enhancement type. In order to increase the gate voltage swing and reduce gate leakage, a Schottky contact electrode is generally made on the p-type GaN cap layer.

[0004] However, due to the characteristics of metal Schottky contact and the difficulty in forming an ideal metal Schottky contact at the p-type GaN interface, the gate leakage of the transistor is still high. The use of a semiconductor pn junction has a lower leakage current and a higher withstand voltage characteristic than a metal Schottky contact. However, since the p-type GaN cap layer is usually doped with a high concentration of Mg, there is a so-called memory effect. After the doping gas stops, Mg doping still exists for a long time in the subsequent growth process, making it difficult to continue growing n-type nitride materials to form a better pn structure. Therefore, an enhancement nitride semiconductor transistor structure is proposed to solve the above problem. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides an enhanced nitride semiconductor transistor structure having the advantages of good gate voltage resistance and low leakage, thereby solving the problem of poor gate voltage resistance and high leakage.

[0006] To achieve the above object, the present invention provides the following technical solutions: an enhanced nitride semiconductor transistor structure, comprising an epitaxial structure, the epitaxial structure comprising a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the barrier layer, and a source, a gate and a drain of the transistor structure are fabricated on the surface of the epitaxial structure;

[0007] The cap layer on the barrier layer includes a polarization-doped p-type nitride semiconductor structure and an n-type nitride semiconductor structure thereon.

[0008] Furthermore, the substrate is a silicon substrate, a silicon carbide substrate, a sapphire substrate or a gallium nitride substrate. The substrate may also be a composite substrate formed by using the above substrate materials as the surface and other materials.

[0009] Furthermore, the nucleation layer is AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure. The nucleation layer can also be a layer of 3C-SiC or SiN grown on the surface of the silicon layer first and then the AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure.

[0010] Furthermore, the buffer layer is a single layer or multi-layer stacked structure of AlN, AlGaN, GaN, or an AlN / GaN, AlN / AlGaN, and AlGaN / GaN superlattice structure. The buffer layer may also be a composite structure including the above structures.

[0011] Furthermore, the barrier layer is AlGaN, AlN, AlInN, AlInGaN, and the barrier layer may also be a composite stack of the above layers.

[0012] Furthermore, the channel layer is a GaN layer, and the channel layer may also be an alloy of Al, In, and GaN in any other proportion or a composite stack of the above layers.

[0013] Furthermore, the p-type polarization doped nitride semiconductor structure in the cap layer is realized by the change of polarization electric field caused by the change of components in the nitride alloy layer. The p-type polarization doped nitride semiconductor structure in the cap layer comprises an AlInGaN alloy layer of any proportion. The components of Al and In in the AlInGaN alloy layer can vary in the range of 0 to 100%, respectively. The Al component decreases along the epitaxial growth direction, the In component remains unchanged or increases along the epitaxial growth direction, or the In component increases along the epitaxial growth direction while the Al component remains unchanged, thereby forming a p-type polarization doped structure. The AlInGaN alloy layer can also be further doped with B element to form a BAlInGaN alloy.

[0014] Furthermore, the AlInGaN p-type polarization doped layer in the cap layer may be a single layer or may include multiple layers. Other layers, such as an undoped nitride layer, a carbon-doped nitride layer or a nitride superlattice, may be inserted between the pn junctions in the cap layer as needed. There is no specific limitation on the other layers included in the cap layer.

[0015] Furthermore, the n-type nitride semiconductor structure in the cap layer can be an unintentionally doped weak n-type semiconductor or a part or all of the region can be n-doped with impurity atoms. The n-type nitride semiconductor structure in the cap layer can also be n-doped by polarization doping caused by component changes in the AlInGaN nitride alloy layer.

[0016] Furthermore, after the source and drain of the transistor and the cap layer except the gate region are etched away by a photolithography process, ohmic contact electrodes are made in the source and drain regions, and the gate electrode is made above the n-type semiconductor layer of the cap layer in the gate region to form an ohmic contact with the n-type semiconductor layer.

[0017] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0018] The enhanced nitride semiconductor transistor structure, by setting a p-type polarized doping structure in the cap layer, can not only achieve higher ionized charge and hole concentrations than impurity doping, effectively deplete the two-dimensional electron gas in the channel layer, but also avoid the memory effect when Mg doped p-type nitride, realize a pn structure with a better interface, replace the commonly used metal semiconductor Schottky contact gate, improve the gate's withstand voltage and reduce gate leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the transistor structure of Example 1 of the present invention;

[0020] Figure 2a to Figure 2c A flow chart of transistor manufacturing according to embodiment 1 of the present invention;

[0021] Figure 3 Schematic diagram of the transistor structure of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] See also Figure 1 Embodiment 1, an enhanced nitride semiconductor transistor structure, including an epitaxial structure, the epitaxial structure includes a substrate 10, a nucleation layer 11, a buffer layer 12, a channel layer 13, a barrier layer 14 and a cap layer on the barrier layer 14, and a source 171, a gate 172 and a drain 173 of the transistor structure are made on the surface of the epitaxial structure.

[0024] The cap layer on the barrier layer 14 includes a polarization-doped p-type nitride semiconductor structure 15 and an n-type nitride semiconductor structure 16 thereon.

[0025] In addition, the substrate 10 may be a silicon substrate, a silicon carbide substrate, a sapphire substrate or a gallium nitride substrate. The substrate 10 may also be a composite layer formed by the above substrate materials and other materials. In this embodiment, a conductive silicon substrate is used.

[0026] The nucleation layer 11 is AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure. The nucleation layer 11 can also be a layer of 3C-SiC or SiN grown on the surface of the silicon layer first and then AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure. The nucleation layer 11 is an AlN layer with a thickness of 100nm.

[0027] In addition, the buffer layer 12 is a single-layer or multi-layer stacked structure of Al N, Al GaN, and GaN, or an Al N / GaN, Al N / Al GaN, and Al GaN / GaN superlattice structure. The buffer layer 12 can also be a composite structure including the above structures. The buffer layer 12 includes an Al N / Al GaN / superlattice structure grown from bottom to top, wherein Al N is 100 nm, and Al GaN can be a single layer or a multilayer of different components. In this embodiment, the Al GaN single-layer structure with an Al component of 50% is 100 nm. In this embodiment, an Al N / GaN superlattice structure is used, and each period includes Al N of 4 nm, Al GaN of 20 nm, and Al component of 20%. The total thickness is about 3 microns, and the carbon doping concentration is about 1×10 19 / cm 3 The channel layer 13 is grown on the buffer layer 12, using 300nm of unintentionally doped GaN and a background electron concentration of about 4×10 16 / cm 3 .

[0028] The barrier layer 14 is AlGaN, AlN, AlInN, AlInGaN, or a composite stack of the above layers.

[0029] The barrier layer 14 is made of AlGaN with an Al content of 22% and has a thickness of 10 nm. A polarization-doped AlGaN layer with an Al content gradually decreasing along the growth direction is continuously grown on the barrier layer 14 and has a thickness of 50 nm. The Al content gradually decreases from 22% to 0%.

[0030] Furthermore, the channel layer 13 is a GaN layer, and the channel layer 13 may also be an alloy of AlInGaN in any other proportion or a composite stack of the above layers.

[0031] It can be known that the p-type polarization doped nitride semiconductor structure in the cap layer is realized by the change of polarization electric field caused by the change of components in the nitride alloy layer. The p-type polarization doped nitride semiconductor structure in the cap layer includes an Al InGaN alloy layer of any proportion. The components of Al and In in the Al InGaN alloy layer can vary in the range of 0 to 100%, respectively. The Al component decreases along the epitaxial growth direction, and the In component remains unchanged or increases along the epitaxial growth direction, or the In component increases along the epitaxial growth direction while the Al component remains unchanged, thereby forming a p-type polarization doped structure. The Al InGaN alloy layer can also be further doped with B element to form BAl InGaN alloy. The n-type doped nitride semiconductor layer continues to grow on the polarization doped Al GaN layer. In this embodiment, a Si-doped GaN layer is used with a thickness of 100nm and a doping concentration of 5×10 17 / cm3 .

[0032] It should be noted that the Al InGaN p-type polarization doped layer in the cap layer can be a single layer or can contain multiple layers. Other layers can be inserted between the pn junctions in the cap layer as needed, such as an undoped nitride layer, a carbon-doped nitride layer, or a nitride superlattice, etc. There is no specific limitation on the other layers contained in the cap layer.

[0033] In addition, the n-type nitride semiconductor structure in the cap layer can be an unintentionally doped weak n-type semiconductor or part or all of the region can be n-doped with impurity atoms. The n-type nitride semiconductor structure in the cap layer can also be n-doped by polarization doping caused by composition changes in the AlInGaN nitride alloy layer.

[0034] It should be further explained that after the source 171 and drain 173 of the transistor are etched away through a photolithography process except for the cap layer in the gate area, ohmic contact electrodes are made in the source 171 and drain 173 areas, and the gate electrode 172 is made above the n-type semiconductor layer of the cap layer in the gate area to form an ohmic contact with the n-type semiconductor layer. The polarization-doped Al GaN layer and the Si-doped GaN layer outside the gate area are etched away through a photolithography process to make transistor electrodes, including ohmic contact electrode source 171, drain 173, and an ohmic contact gate electrode 172 is made above the Si-doped GaN layer in the gate area.

[0035] See also Figure 2a to Figure 2c In order to demonstrate the process flow, the substrate 10 in this embodiment is used as the substrate 10, on which a nucleation layer 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a cap layer polarization-doped p-type nitride semiconductor structure and an n-type nitride semiconductor structure are sequentially grown.

[0036] The following steps are involved:

[0037] 1) a. The growth process is metal organic chemical vapor deposition MOCVD or molecular beam epitaxy MBE, or sputtering process, or other vapor deposition processes. This embodiment adopts MOCVD process; the nucleation layer 11 is an Al N layer with a thickness of 100 nm;

[0038] b. Buffer layer 12, including AlN / AlGaN / superlattice structure grown sequentially from bottom to top, wherein AlN is 100nm, AlGaN can be a single layer or a multilayer with different components, and in this embodiment, it is a 100nm AlGaN single layer structure with an Al component of 50%;

[0039] c. In this embodiment, an AlN / GaN superlattice structure is used. Each period includes AlN 4nm, AlGaN 20nm, Al component is 20%, the total thickness is about 3 microns, and the carbon doping concentration is about 1×10 19 / cm 3 ;

[0040] d. A channel layer 13 is grown on the buffer layer 12, using 300nm of unintentionally doped GaN with a background electron concentration of about 4×10 16 / cm 3 ;

[0041] e. The barrier layer 14 is made of AlGaN with an Al content of 22% and a thickness of 10 nm;

[0042] f. A cap layer is continuously grown on the barrier layer 14, including a p-type polarization doped AlGaN layer with a thickness of 50 nm and an Al component gradually decreasing from 22% to 0% along the growth direction, and an n-type doped nitride semiconductor cap layer on the polarization doped AlGaN layer. In this embodiment, a Si-doped GaN layer is used with a thickness of 100 nm and a doping concentration of 5×10 17 / cm 3 ;

[0043] 2) using a photolithography process in combination with a Cl-containing plasma etching process to etch away the polarization-doped Al GaN layer and the Si-doped GaN layer outside the gate region;

[0044] 3) Ohmic contact electrodes, source 171, gate electrode 172, and drain 173 are fabricated on the barrier layer 14 in the source 171 and drain 173 regions, and on the Si-doped GaN layer in the gate region using a metal alloy containing Ti and Al combined with an annealing process.

[0045] See also Figure 3 Embodiment 2, an enhanced nitride semiconductor transistor structure, including an epitaxial structure, the epitaxial structure includes a substrate 20, a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24 and a cap layer on the barrier layer 24, a transistor structure is fixed on the top of the epitaxial material, and the transistor structure includes a source 271, a gate 272 and a drain 273.

[0046] In addition, the cap layer on the barrier layer 24 includes a polarization-doped p-type nitride semiconductor structure 25 and an n-type nitride semiconductor structure thereon, wherein the polarization-doped p-type nitride semiconductor structure is an Al GaN layer, and the n-type nitride semiconductor structure is an unintentionally doped n-type GaN layer 261 and a Si-doped n-type GaN layer 262.

[0047] In addition, the substrate 20 is a silicon substrate, a silicon carbide substrate, a sapphire substrate or a gallium nitride substrate. The substrate 20 may also be a composite substrate formed by the above substrate materials and other materials. In this embodiment, a conductive silicon substrate is used.

[0048] It can be known that the nucleation layer 21 is AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure. The nucleation layer 21 can also be a layer of 3C-SiC or SiN grown on the surface of the silicon layer first and then AlN, GaN, InN or their alloys are grown, or the above-mentioned multi-layer stacked structure, the nucleation layer 21 is an AlN layer with a thickness of 100nm.

[0049] In addition, the buffer layer 22 is a single layer or multilayer stacked structure of Al N, Al GaN, GaN or a super lattice structure of Al N / GaN, Al N / Al GaN and Al GaN / GaN. The buffer layer 22 can also be a composite structure including the above structures, wherein Al N is 100 nm, Al GaN can be a single layer or a multilayer of different components, and in this embodiment, it is a 50 nm Al GaN single layer structure with an Al component of 50%. In this embodiment, an Al N / Al GaN super lattice structure is adopted, and each period includes Al N 4 nm, Al GaN 20 nm, and an Al component of 20%, with a total thickness of about 3 microns and a carbon doping concentration of about 1×10 19 / cm 3 .

[0050] It should be further explained that the barrier layer 25 is AlGaN, AlN, AlInN, AlInGaN, and the barrier layer 24 can also be a multiple superposition of the above layers. A polarization-doped AlGaN layer 25 with an Al component gradually decreasing along the growth direction continues to grow above the barrier layer 24, with a thickness of 50nm and an Al component gradually decreasing from 22% to 0%.

[0051] Furthermore, the channel layer 23 is a GaN layer. The channel layer 23 can also be an alloy of Al, In, and GaN in any proportion or a composite stack of the above layers. The channel layer 23 uses unintentionally doped GaN 300nm, and the background electron concentration is about 4×10 16 / cm 3 .

[0052] It can be known that the p-type polarization doped nitride semiconductor structure in the cap layer is realized by the change of polarization electric field caused by the change of components in the nitride alloy layer. The p-type polarization doped nitride semiconductor structure in the cap layer includes an AlInGaN alloy layer of any proportion. The components of Al and In in the AlInGaN alloy layer can vary in the range of 0 to 100%, respectively. The Al component decreases along the epitaxial growth direction, the In component remains unchanged or increases along the epitaxial growth direction, or the In component increases along the epitaxial growth direction while the Al component remains unchanged, thereby forming a p-type polarization doped structure. The AlInGaN alloy layer can also be further doped with B element to form a BAlInGaN alloy. An unintentionally doped n-type GaN layer 261 with a thickness of 50nm and an electron concentration of about 4×10 16 / cm 3 , and a Si-doped n-type GaN layer 262 with a thickness of 100 nm and an electron concentration of 5×10 17 / cm 3 .

[0053] It should be noted that the AlInGaN p-type polarization doped layer in the cap layer may be a single layer or may include multiple layers, and no specific limitation is imposed on other layers included in the cap layer.

[0054] In addition, the n-type nitride semiconductor structure in the cap layer can be an unintentionally doped weak n-type semiconductor or part or all of the region can be n-doped with impurity atoms. The n-type nitride semiconductor structure in the cap layer can also be n-doped by polarization doping caused by composition changes in the AlInGaN nitride alloy layer.

[0055] It should be further explained that after the source 271 and drain 273 of the transistor are etched away by a photolithography process except for the cap layer in the gate region, ohmic contact electrodes are made in the source 271 and drain 273 regions, and the gate electrode 272 is made above the n-type semiconductor layer of the cap layer in the gate region to form an ohmic contact with the n-type semiconductor layer. The polarization-doped Al GaN layer 25 and the Si-doped GaN layer outside the gate region are etched away by a photolithography process to make transistor electrodes, including the ohmic contact electrode source 272 and the drain 273. An ohmic contact gate electrode 272 is made above the Si-doped GaN layer in the gate region. By inserting an unintentionally doped n-type GaN layer 261, the gate's withstand voltage and capacitance can be better adjusted.

[0056] The electrical components appearing in the text are all electrically connected to the controller and the power supply. The control method of the present invention is controlled by the controller. The control circuit of the controller can be implemented by simple programming by technicians in this field. The provision of power supply is also common knowledge in this field. The present invention is mainly used to protect mechanical devices, so the present invention will no longer explain the control method and circuit connection in detail.

[0057] The working principle of the above embodiment is:

[0058] By setting a p-type polarization doping structure in the cap layer, the two-dimensional electron gas in the channel layer 13 can be depleted, and the memory effect when Mg doped p-type nitride is avoided, and a pn structure with a good interface is realized between the n-type layer above the p-type polarization doping layer. Using a pn junction to replace the metal semiconductor Schottky contact gate used in the conventional pGaN enhancement transistor structure can improve the gate withstand voltage and reduce gate leakage.

[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0060] While the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. An enhancement mode nitride semiconductor transistor structure, comprising an epitaxial structure, characterized in that: The epitaxial structure comprises a substrate (10), a nucleation layer (11), a buffer layer (12), a channel layer (13), a barrier layer (14) and a cap layer on the barrier layer (14); a source electrode (171), a gate electrode (172) and a drain electrode (173) of a transistor structure are fabricated on the surface of the epitaxial structure; The cap layer on the barrier layer (14) comprises a polarization-doped p-type nitride semiconductor structure (15) and an n-type nitride semiconductor structure (16) thereon.

2. An enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The substrate (10) is a silicon substrate, a silicon carbide substrate, a sapphire substrate or a gallium nitride substrate. The substrate (10) may also be a composite substrate formed by using the above substrate materials as the surface and other materials.

3. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The nucleation layer (11) is AlN, GaN, InN or their alloys, or the above-mentioned multi-layer stacked structure. The nucleation layer (11) can also be a layer of 3C-SiC or SiN grown on the surface of the silicon layer first and then the AlN, GaN, InN or their alloys are grown, or the above-mentioned multi-layer stacked structure.

4. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The buffer layer (12) is a single layer or multilayer stacked structure of AlN, AlGaN, GaN, or an AlN / GaN, AlN / AlGaN, or AlGaN / GaN superlattice structure. The buffer layer (12) may also be a composite structure including the above structures.

5. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The barrier layer (14) is AlGaN, AlN, AlInN, AlInGaN, and the barrier layer (14) may also be a composite stack of the above layers.

6. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The channel layer (13) is a GaN layer. The channel layer (13) may also be an alloy of AlInGaN in any other proportion or a composite stack of the above layers.

7. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The p-type polarization doped nitride semiconductor structure in the cap layer is realized by the change of polarization electric field caused by the change of components in the nitride alloy layer. The p-type polarization doped nitride semiconductor structure in the cap layer comprises an AlInGaN alloy layer in any proportion. The components of Al and In in the AlInGaN alloy layer can vary in the range of 0 to 100%, respectively. The Al component decreases along the epitaxial growth direction, the In component remains unchanged or increases along the epitaxial growth direction, or the In component increases along the epitaxial growth direction while the Al component remains unchanged, thereby forming a p-type polarization doped structure. The AlInGaN alloy layer can also be further doped with B element to form a BAlInGaN alloy.

8. The enhancement mode nitride semiconductor transistor structure according to claim 7, characterized in that: The AlInGaNp-type polarization doped layer in the cap layer can be a single layer or can contain multiple layers. Other layers such as an undoped nitride layer, a carbon-doped nitride layer or a nitride superlattice can be inserted between the pn junctions in the cap layer as needed. There is no specific limitation on the other layers contained in the cap layer.

9. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: The n-type nitride semiconductor structure in the cap layer can be an unintentionally doped weak n-type semiconductor or part or all of the region can be n-doped using impurity atoms. The n-type nitride semiconductor structure in the cap layer can also be n-doped by polarization doping caused by component changes in the AlInGaN nitride alloy layer.

10. The enhancement mode nitride semiconductor transistor structure according to claim 1, characterized in that: After the source (171) and drain (173) of the transistor and the cap layer except the gate region are etched away by photolithography, ohmic contact electrodes are made in the source (171) and drain (173) regions, and the gate electrode (172) is made above the n-type semiconductor layer of the cap layer in the gate region to form an ohmic contact with the n-type semiconductor layer.

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