Monolithic integrated voltage doubling rectifying device based on quasi-vertical JTE SBD

Abstract

The invention discloses a monolithic integration voltage doubling rectifying device based on quasi-vertical JTE SBD, and the device comprises two quasi-vertical JTE SBD which respectively form a first charging diode and a second charging diode; the first metal layer comprises a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode and a second charging diode cathode; the second metal layer comprises a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate and a second capacitor cathode plate; the first interlayer interconnection metal is connected with the second port and the first capacitor cathode plate; the second interlayer interconnection metal is connected with the anode of the second charging diode and the cathode of the first charging diode; and the third interlayer interconnection metal is connected with the third port, the anode plate of the second capacitor and the cathode of the second charging diode. The device provided by the invention has relatively high electrical performance and can be applied to occasions of high frequency, high power, intense radiation and the like.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE (Junction Termination Extension) SBD (Schottky Rectifier Diode). Background Art

[0002] Voltage doubler rectifier units are commonly used in voltage conversion in medium and low voltage power electronic equipment and radio frequency systems. Traditional voltage doubler rectifier units are mostly composed of silicon single tube discrete devices, among which a more representative one is a DC-DC voltage regulator converter, in which the boost unit is composed of voltage doubler circuits connected in series, and each level of the voltage doubler circuit is composed of two capacitors, two diodes and a bleeder resistor, thereby realizing multi-level voltage amplification through multi-level series connection. However, the voltage doubler rectifier unit composed of discrete devices has a low degree of integration and is difficult to adapt to the needs of the development of the times.

[0003] In addition, the core components of existing voltage doubler rectifier units - rectifier diodes are mostly made of Si materials, which have low power density, low withstand voltage, narrow application range, and are difficult to miniaturize under high power conditions. As the requirements for efficiency, power density, and device volume of power processing equipment become higher and higher, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties.

[0004] Therefore, there is an urgent need for a monolithic integrated voltage doubler rectifier unit with high electrical performance that can be used in high frequency, high power, strong radiation and other occasions. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] A monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, comprising:

[0008] Two quasi-vertical JTE SBDs are located on a silicon substrate; the two quasi-vertical JTE SBDs form a first charging diode and a second charging diode respectively;

[0009] Passivation layer; the passivation layer covers the two quasi-vertical JTE SBDs and the silicon substrate;

[0010] A first metal layer located inside the passivation layer; the first metal layer includes metals forming a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate is connected to the second charging diode cathode;

[0011] a second layer of metal located on the upper surface of the passivation layer; the second layer of metal includes metals forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively; wherein the first port, the second capacitor cathode plate, and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode, and the fourth port are connected;

[0012] A first interlayer interconnection metal; the first interlayer interconnection metal connects the second port and the first capacitor cathode plate;

[0013] A second interlayer interconnection metal; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode;

[0014] A third inter-layer interconnection metal; the third inter-layer interconnection metal connects the third port and the cathode of the second charging diode.

[0015] Optionally, the quasi-vertical JTE SBD comprises: an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring;

[0016] Among them, the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure; the epitaxial structure includes a GaN conductive layer and a GaN drift layer superimposed on the GaN conductive layer; the anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; and the cathode of the quasi-vertical JTE SBD is located on the GaN drift layer.

[0017] Optionally, the first JTE ring, the second JTE ring and the third JTE ring are all made of Mg-doped P-type BN.

[0018] Optionally, the doping concentration of the Mg-doped P-type BN is 1.0×10 16 cm -3 ~1.0×10 18 cm -3 .

[0019] Optionally, the widths of the first JTE ring, the second JTE ring and the third JTE ring are 10 μm to 30 μm; wherein the widths of the first JTE ring, the second JTE ring and the third JTE ring decrease in sequence.

[0020] Optionally, the Si doping concentration of the GaN drift layer is 1.0×10 16 cm -3 ~5.0×10 17 cm -3 .

[0021] Optionally, the Si doping concentration of the GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

[0022] Optionally, the length of the first capacitor cathode plate, the second capacitor anode plate, the first capacitor anode plate and the second capacitor cathode plate is 10 μm to 100 μm, and the width is 10 μm to 100 μm.

[0023] The present invention also provides a method for preparing a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, comprising:

[0024] Growing an epitaxial layer on a silicon substrate, and performing mesa etching and isolation etching on the epitaxial layer to form two epitaxial structures;

[0025] Preparing JTE ring structures on the upper surfaces of the two epitaxial structures respectively, so as to form two quasi-vertical JTE SBDs using the two JTE ring structures later; the two quasi-vertical JTE SBDs respectively form a first charging diode and a second charging diode;

[0026] Depositing a first passivation layer on the surface of the current device, and opening the passivation layer to expose an anode region and a cathode region; the anode region corresponds to the anode of the quasi-vertical JTE SBD, and the cathode region corresponds to the cathode of the quasi-vertical JTE SBD;

[0027] Depositing a Schottky metal in the anode region and depositing an ohmic metal in the cathode region to form two quasi-vertical JTE SBDs;

[0028] Depositing a second passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the Schottky metal and the ohmic metal;

[0029] A first metal layer is prepared on the current device; the first metal layer includes metals that form a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate and the second charging diode cathode are connected; and the metals that form the first charging diode cathode and the second charging diode cathode are connected to the ohmic metal;

[0030] A third passivation layer is deposited on the surface of the current device, and holes are opened in the passivation layer to expose the Schottky metal, the metal forming the cathode of the first charging diode and the cathode of the second charging diode, and the metal forming the cathode plate of the first capacitor.

[0031] A second metal layer, a first interlayer interconnection metal, a second interlayer interconnection metal, and a third interlayer interconnection metal are prepared on the current device; the second metal layer includes metals for forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively;

[0032] Among them, the first port, the second capacitor cathode plate and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode and the fourth port are connected; wherein the metal forming the first charging diode anode and the second charging diode anode connects the Schottky metal; the first interlayer interconnection metal connects the second port and the first capacitor cathode plate; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode; the third interlayer interconnection metal connects the third port and the second charging diode cathode.

[0033] Optionally, the JTE ring structure includes: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure.

[0034] The monolithic integrated voltage doubler rectifier device based on the quasi-vertical JTE SBD provided by the present invention has the following characteristics:

[0035] Beneficial effects:

[0036] (1) The monolithic integrated voltage doubler rectifier device provided by the present invention adopts silicon-based GaN monolithic integration. Compared with traditional GaN integrated circuits, it has a smaller volume, smaller parasitics, higher power density, lower cost and higher reliability, so that it can be used in high-power power conversion systems with complex working conditions and limited volume. In addition, in the quasi-vertical JTE SBD adopted by the present invention, the JTE terminal structure has good electric field regulation capability, improves the withstand voltage of the diode, and enhances the power handling capability of the voltage doubler rectifier device.

[0037] (2) The present invention uses silicon-based GaN materials to reduce circuit costs, and adopts a quasi-vertical JTE SBD with Mg-doped P-BN to replace the traditional Schottky diode. The high breakdown field strength of the BN material and the electric field regulation capability of the JTE terminal structure are utilized to improve the withstand voltage of the diode and enhance the power handling capability of the voltage doubler rectifier device.

[0038] (3) The core device of the present invention adopts GaN-based materials. Compared with Si materials, GaN has a larger bandgap, a higher critical breakdown electric field and a higher saturation velocity, which makes it have better electrical properties. In addition, its thermal conductivity, temperature stability and corrosion resistance are far superior to Si materials. Therefore, the monolithic integrated voltage doubler rectifier device provided by the present invention has excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility and high device resistance, and can work stably under complex working conditions such as high frequency, high power and strong radiation, and has a wider application prospect.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a three-dimensional structural diagram of a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD provided by an embodiment of the present invention;

[0041] Figure 2 is a top view of a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD provided by an embodiment of the present invention;

[0042] FIG3( a ) is a circuit schematic diagram of a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD according to an embodiment of the present invention;

[0043] FIG3( b ) shows the working principle of a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD provided in an embodiment of the present invention;

[0044] Figure 4 FIG. 4 shows an epitaxial structure of a monolithically integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD according to an embodiment of the present invention;

[0045] Figure 5 3D structure of the quasi-vertical JTE SBD in the embodiment of the present invention is shown in FIG.

[0046] Figure 6 3D structural cross section of the quasi-vertical JTE SBD in an embodiment of the present invention is shown in FIG.

[0047] Figure 7 to Figure 17 The invention shows a process for preparing a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD according to an embodiment of the invention. DETAILED DESCRIPTION

[0048] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0049] In order to realize a monolithic integrated voltage doubler rectifier unit with high electrical performance and applicable to high frequency, high power, strong radiation and other occasions, the embodiment of the present invention provides a monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD. Figure 1 and Figure 2 As shown, the device includes: a silicon substrate (Si-substrate, crystal plane (111)), two quasi-vertical JTE SBDs, a passivation layer, a first layer of metal, a second layer of metal, a first interlayer interconnection metal a, a second interlayer interconnection metal b and a third interlayer interconnection metal c.

[0050] Two quasi-vertical JTE SBDs are located on a silicon substrate; the two quasi-vertical JTE SBDs form a first charging diode D1 and a second charging diode D2 respectively.

[0051] The passivation layer covers the two quasi-vertical JTE SBDs and the silicon substrate.

[0052] The first metal layer is located inside the passivation layer; the first metal layer includes metals that form the first capacitor cathode plate, the second capacitor anode plate, the first charging diode cathode and the second charging diode cathode respectively; wherein the second capacitor anode plate and the second charging diode cathode are connected.

[0053] The second metal layer is located on the upper surface of the passivation layer; the second metal layer includes metals that respectively form the first port 1, the second port 2, the third port 3, the fourth port 4, the first charging diode anode, the second charging diode anode, the first capacitor anode plate and the second capacitor cathode plate. The first port 1 and the second port 2 are two AC input ports, and the third port 3 and the fourth port 4 are two boosted AC output ports. The first port 1, the second capacitor cathode plate and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode and the fourth port 4 are connected.

[0054] The first interlayer interconnection metal connects the second port 2 and the first capacitor cathode plate; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode; the third interlayer interconnection metal connects the third port 3 and the second charging diode cathode.

[0055] In the embodiment of the present invention, the first capacitor cathode plate and the first capacitor anode plate correspond to each other up and down, and cooperate with the passivation layer between the plates to form a first MIM parallel plate dielectric capacitor C1; the second capacitor cathode plate and the second capacitor anode plate correspond to each other up and down, and cooperate with the passivation layer between the plates to form a second MIM parallel plate dielectric capacitor C2. The first MIM parallel plate dielectric capacitor C1 and the second MIM parallel plate dielectric capacitor C2 adopt a MIM structure, which is suitable for monolithic integration.

[0056] The thickness of the inter-plate passivation layer of the first MIM parallel plate dielectric capacitor C1 and the second MIM parallel plate dielectric capacitor C2 is preferably 0.5 μm to 5 μm; the length of the second capacitor anode plate, the first capacitor cathode plate, the first capacitor anode plate and the second capacitor cathode plate can be 10 μm to 100 μm, and the width can be 10 μm to 100 μm. By adjusting the thickness of the inter-plate passivation layer and the plate area, different capacitance values ​​can be obtained.

[0057] FIG3 shows a circuit schematic diagram of a monolithic integrated voltage doubler rectifier device provided in an embodiment of the present invention; the working principle of the monolithic integrated voltage doubler rectifier device provided in an embodiment of the present invention is described below in conjunction with the circuit schematic diagram:

[0058] All diodes and capacitors in the device are in the initial state. Assuming that an AC input signal with a peak voltage of U0 is input into the device, the general operation process of the signal in the device is as follows:

[0059] In the first cycle, the positive polarity voltage U0 is input to the first port 1, the first charging diode D1 is turned on, the second charging diode D2 is turned off, the first port 1 charges the first MIM parallel plate dielectric capacitor C1 through the first charging diode D1, and makes the right side of the first MIM parallel plate dielectric capacitor C1 have an electric potential of U0; at this time, the polarity is reversed, and the positive polarity voltage is input to the device from the second port 2. At this time, the total voltage at the right end of the first MIM parallel plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel plate dielectric capacitor C1 2U0. At this time, the second charging diode D2 is turned on, the first MIM parallel plate dielectric capacitor C1 begins to charge the second MIM parallel plate dielectric capacitor C2 through the second charging diode D2, and finally reaches equilibrium after the right side of the second MIM parallel plate dielectric capacitor C2 has an electric potential of U0.

[0060] In the second cycle, at this time, the positive polarity voltage U0 is input to the first port 1, at this time the first charging diode D1 is turned on, the second charging diode D2 is turned off, the first port 1 charges the first MIM parallel plate dielectric capacitor C1 through the first charging diode D1, and makes the right side of the first MIM parallel plate dielectric capacitor C1 have an electric potential of U0; at this time, the polarity is reversed, and the positive polarity voltage is input to the device from the second port 2. At this time, the total voltage at the right end of the first MIM parallel plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel plate dielectric capacitor C1 2U0. At this time, the second charging diode D2 is turned on, and the first MIM parallel plate dielectric capacitor C1 begins to charge the second MIM parallel plate dielectric capacitor C2 through the second charging diode D2. At this time, the right side of the second MIM parallel plate dielectric capacitor C2 maintains the voltage U0 charged in the previous cycle, that is, it will eventually reach equilibrium after the first MIM parallel plate dielectric capacitor C1 has a potential of 0.5U0 and the right side of the second MIM parallel plate dielectric capacitor C2 has a potential of 1.5U0.

[0061] In the third cycle, the positive polarity voltage U0 is input to the first port 1, and the first charging diode D1 is turned on, and the second charging diode D2 is turned off. The first port 1 charges the first MIM parallel plate dielectric capacitor C1 through the first charging diode D1, and makes the right side of the first MIM parallel plate dielectric capacitor C1 have an electric potential of U0; at this time, the polarity is reversed, and the positive polarity voltage is input into the circuit from the second port 2. At this time, the total voltage at the right end of the first MIM parallel plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel plate dielectric capacitor C1 2U0. At this time, the second charging diode D2 is turned on, and the first MIM parallel plate dielectric capacitor C1 begins to charge the second MIM parallel plate dielectric capacitor C2 through the second charging diode D2. At this time, the right side of the second MIM parallel plate dielectric capacitor C2 maintains the voltage 1.5U0 charged in the previous cycle, that is, it will eventually reach equilibrium after the first MIM parallel plate dielectric capacitor C1 has a potential of 0.75U0 and the right side of the second MIM parallel plate dielectric capacitor C2 has a potential of 1.75U0.

[0062] From the above three cycles, we can see the pattern that, as the voltage cycle goes back and forth, the potential on the second MIM parallel plate dielectric capacitor C2 will become increasingly close to 2U0, which is twice the amplitude of the input signal, thus achieving the voltage doubling function.

[0063] The monolithic integrated voltage doubler rectifier device based on the quasi-vertical JTE SBD provided in the embodiment of the present invention adopts silicon-based GaN monolithic integration. Compared with the traditional GaN integrated circuit, it has a smaller volume, smaller parasitics, higher power density, lower cost and higher reliability, so that it can be used in high-power power conversion systems with complex working conditions and limited volume. In addition, in the quasi-vertical JTE SBD adopted in the embodiment of the present invention, the JTE terminal structure has good electric field regulation capability, improves the withstand voltage of the diode, and enhances the power handling capability of the voltage doubler rectifier device.

[0064] In one embodiment, the quasi-vertical JTE SBD includes: an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring.

[0065] Among them, see Figure 5 and Figure 6 The first JTE ring (JTE1), the second JTE ring (JTE2) and the third JTE ring (JTE3) are superimposed to form a stepped JTE ring structure. The anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; according to the different power capacities of the device, the radius of the anode can be set at 30um to 90um.

[0066] In the stepped JTE ring structure, the first JTE ring, the second JTE ring and the third JTE ring have different widths and thicknesses, so that they can play the best electric field modulation function under different sizes and doping conditions.

[0067] Preferably, the widths of the first JTE ring, the second JTE ring and the third JTE ring are 10 μm to 30 μm; wherein the widths of the first JTE ring, the second JTE ring and the third JTE ring decrease in sequence.

[0068] Preferably, the materials of the first JTE ring, the second JTE ring and the third JTE ring are all Mg-doped P-type BN. Therefore, the embodiment of the present invention adopts a quasi-vertical JTE SBD with Mg-doped P-BN to replace the traditional Schottky diode, and utilizes the high breakdown field strength of the BN material and the electric field regulation capability of the JTE terminal structure to improve the withstand voltage of the diode and enhance the power handling capability of the voltage doubler rectifier device.

[0069] Preferably, the doping concentration of Mg-doped P-type BN is 1.0×10 16 cm -3 ~1.0×10 18 cm -3 .

[0070] In the embodiment of the present invention, see Figure 4The epitaxial structure includes a GaN conduction layer (N GaN) and a GaN drift layer (N+GaN) superimposed on the GaN conduction layer; the cathode (Cathode) of the quasi-vertical JTE SBD is located on the GaN drift layer.

[0071] Preferably, the Si doping concentration of the GaN drift layer is 1.0×10 16 cm -3 ~5.0×10 17 cm -3 .

[0072] Preferably, the Si doping concentration of the GaN conductive layer is 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

[0073] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, comprising:

[0074] Step 1: grow an epitaxial layer on a silicon substrate, perform mesa etching and isolation etching on the epitaxial layer to form two epitaxial structures.

[0075] Specifically, a GaN conduction layer and a GaN drift layer are epitaxially grown on a silicon substrate in sequence to form an epitaxial layer. Then, the epitaxial layer is etched into two independent circular terraces, so that two quasi-vertical JTESBDs can be prepared on the two circular blocks respectively. The two circular terraces are respectively etched to expose a circle of GaN conduction layer, such as Figure 7 Then, the exposed GaN conductive layer is isolated and etched to form an isolation region, thereby obtaining the following: Figure 7 The two epitaxial structures are shown in the right sub-figure.

[0076] Step 2: Prepare JTE ring structures on the upper surfaces of the two epitaxial structures respectively, so as to form two quasi-vertical JTE SBDs using the two JTE ring structures later; the two quasi-vertical JTE SBDs respectively form a first charging diode and a second charging diode.

[0077] Here, a JTE ring structure is prepared on the epitaxial structure to facilitate subsequent connection of the device using on-chip wiring. Specifically, a sputtering process is used to prepare a JTE ring structure on the upper surface of each epitaxial structure, that is, the upper surface of the GaN drift layer.

[0078] Specifically, sputtering is first performed on the upper surface of the GaN drift layer to form a first JTE ring, and then sputtering is performed again on the upper surface of the JTE ring to form a second JTE ring. The second JTE ring is superimposed on the first JTE ring and is concentric with the first JTE ring, and has a smaller radius than the first JTE ring; then, referring to the method of sputtering the second JTE ring on the first JTE ring, sputtering is performed on the second JTE ring to form a third JTE ring, and so on, thereby forming a structure in which multiple JTE rings are stacked in sequence, that is, a JTE ring structure.

[0079] In one embodiment, the JTE ring structure may include: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure. In the specific preparation, firstly, a sputtering is performed on the upper surface of the GaN drift layer to form a first JTE ring, such as Figure 8 Then, secondary sputtering is performed on the upper surface of the first JTE ring to form a second JTE ring, such as Figure 8 Then, three sputterings are performed on the upper surface of the second JTE ring to form a third JTE ring, such as Fig. 9 The left sub-figure in .

[0080] Step 3: deposit a first passivation layer on the surface of the current device, and make holes in the passivation layer to expose the anode region and the cathode region; the anode region corresponds to the anode of the quasi-perpendicular JTE SBD, and the cathode region corresponds to the cathode of the quasi-perpendicular JTE SBD.

[0081] Specifically, a first passivation layer (material such as SiN) is deposited on the surface of the current device using a growth process. x ),like Fig. 9 Then, a cathode region is selected on the passivation layer directly above the GaN conduction layer with a passivation layer deposited on the surface, and an anode region is selected on the passivation layer directly above the anode of the quasi-vertical JTE SBD, and holes are opened in the passivation layer on the cathode region and the anode region to expose the GaN drift layer directly below the anode region, which corresponds to the anode of the quasi-vertical JTE SBD, and expose the GaN conduction layer directly below the cathode region, which corresponds to the cathode of the quasi-vertical JTE SBD, as shown in FIG. Fig.10 The left sub-figure in .

[0082] Step 4: deposit a Schottky metal in the anode region and deposit an ohmic metal in the cathode region to form two quasi-vertical JTE SBDs.

[0083] Specifically, a Schottky metal (eg, a Ni / Au stacked structure) is deposited in the anode region using a metal evaporation process to form an anode of a quasi-vertical JTE SBD, such as Fig.10 Then, using a metal evaporation process, an ohmic metal (such as a Ti / Al / Ni / Au stacked structure) is deposited in the cathode region to form the cathode of the quasi-vertical JTE SBD, as shown in FIG. Fig.11 .

[0084] Step 5: deposit a second passivation layer on the surface of the current device, and make holes in the first passivation layer to expose the Schottky metal and the ohmic metal.

[0085] Specifically, a second passivation layer is deposited on the surface of the current device using an epitaxial growth process, such as Fig.12 Then, the Schottky metal and the ohmic metal below are aligned, and the passivation layer is opened to expose the Schottky metal and the ohmic metal below, such as Fig.13 .

[0086] Step 6: Prepare a first metal layer on the current device.

[0087] Here, the first metal layer (Metal layer 1) includes metals that respectively form a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode (i.e., a cathode of a quasi-vertical JTE SBD) and a second charging diode cathode (i.e., a cathode of another quasi-vertical JTE SBD); wherein the second capacitor anode plate and the second charging diode cathode are connected; and the metals that form the first charging diode cathode and the second charging diode cathode are connected to the ohmic metal.

[0088] Specifically, the area where the interconnecting metal between the metal parts contained in the first layer of metal and the metal parts therein is located is selected on the surface of the current device; the interconnecting metal here refers to the metal connecting the anode plate of the second capacitor and the cathode of the second charging diode. Then, metal is evaporated in the selected area using a metal evaporation process; by evaporating the metal, the metal forming the cathode of the first charging diode and the cathode of the second charging diode is also connected to the ohmic metal below, such as Fig.14 .

[0089] Step 7: deposit a third passivation layer on the surface of the current device, and make holes in the passivation layer to expose the Schottky metal, the metal forming the cathode of the first charging diode and the cathode of the second charging diode, and the metal forming the cathode plate of the first capacitor.

[0090] Specifically, a third passivation layer is deposited on the surface of the current device using an epitaxial growth process, such as Fig.15Then, the third passivation layer is opened by aligning the Schottky metal below, the metal forming the cathode of the first charging diode, the metal forming the cathode of the second charging diode, and the metal forming the cathode plate of the first capacitor, such as Fig.16 .

[0091] Step eight: prepare a second metal layer, a first interlayer interconnection metal, a second interlayer interconnection metal and a third interlayer interconnection metal on the current device.

[0092] Here, the second metal layer (Metal layer 2) includes metals that respectively form the first port, the second port, the third port, the fourth port, the first charging diode anode, the second charging diode anode, the first capacitor anode plate, and the second capacitor cathode plate.

[0093] Among them, the first port, the second capacitor cathode plate and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode and the fourth port are connected; the metal forming the first charging diode anode and the second charging diode anode is connected to the Schottky metal; the first interlayer interconnection metal connects the second port and the first capacitor cathode plate; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode; the third interlayer interconnection metal connects the third port and the second charging diode cathode; the interlayer interconnection metal of these three parts actually forms a metal via (Metal Via).

[0094] Specifically, the area where the interconnecting metal between the metal parts contained in the second layer of metal and the metal parts therein is located is selected on the surface of the current device; the interconnecting metal here includes the metal connecting the first port, the second capacitor cathode plate and the first charging diode anode, and also includes the metal connecting the first capacitor anode plate, the second charging diode anode and the fourth port. Then, metal is evaporated in the selected area using a metal evaporation process; by evaporating the metal, not only the metal forming the first charging diode anode and the second charging diode anode are connected to the Schottky metal, but also the three metal vias mentioned above are formed, such as Fig.17 .

[0095] Thus, the preparation of the monolithic integrated voltage doubler rectifier device is completed. The structure of the prepared monolithic integrated voltage doubler rectifier device is shown in Figure 1 and Figure 2 .

[0096] It should be noted that, for the preparation method embodiment, the structure of the device prepared therefrom is basically similar to that of the device embodiment, so the description is relatively simple, and the relevant parts may refer to the partial description of the device embodiment.

[0097] In summary, the embodiment of the present invention proposes for the first time a monolithic integrated voltage doubler rectifier unit based on a JTE SBD with Mg-doped P-BN, which improves the integration level, greatly improves the withstand voltage level of the Schottky diode, greatly reduces the circuit volume, improves the circuit reliability, and broadens the voltage application window of the integrated voltage doubler rectifier unit.

[0098] The embodiment of the present invention utilizes the high breakdown field strength of the BN material and the electric field regulation capability of the JTE structure, greatly improving the withstand voltage level of the Schottky diode and broadening the voltage application window of the integrated voltage doubler rectifier unit. However, the existing technology mostly uses traditional Schottky diodes, lacks effective junction terminal technology to increase the device operating voltage, and limits the operating range of the existing devices.

[0099] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0101] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0102] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0103] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0104] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0105] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, characterized in that: include: Two quasi-vertical JTE SBDs are located on a silicon substrate; the two quasi-vertical JTE SBDs form a first charging diode and a second charging diode respectively; Passivation layer; The passivation layer covers the two quasi-vertical JTE SBDs and the silicon substrate; A first metal layer located inside the passivation layer; the first metal layer includes metals forming a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate is connected to the second charging diode cathode; a second layer of metal located on the upper surface of the passivation layer; the second layer of metal includes metals forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively; wherein the first port, the second capacitor cathode plate, and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode, and the fourth port are connected; A first interlayer interconnection metal; the first interlayer interconnection metal connects the second port and the first capacitor cathode plate; A second interlayer interconnection metal; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode; A third inter-layer interconnection metal; the third inter-layer interconnection metal connects the third port and the cathode of the second charging diode.

2. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 1, characterized in that: The quasi-vertical JTE SBD comprises: an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; Among them, the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure; the epitaxial structure includes a GaN conductive layer and a GaN drift layer superimposed on the GaN conductive layer; the anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; and the cathode of the quasi-vertical JTE SBD is located on the GaN drift layer.

3. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 2, characterized in that: The materials of the first JTE ring, the second JTE ring and the third JTE ring are all Mg-doped P-type BN.

4. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The doping concentration of the Mg-doped P-type BN is 1.0×10 16 cm -3 ~1.0×10 18 cm -3 .

5. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The widths of the first JTE ring, the second JTE ring and the third JTE ring are 10 μm to 30 μm; wherein the widths of the first JTE ring, the second JTE ring and the third JTE ring decrease in sequence.

6. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The Si doping concentration of the GaN drift layer is 1.0×10 16 cm -3 ~5.0×10 17 cm -3 .

7. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

8. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 1, characterized in that: The length of the first capacitor cathode plate, the second capacitor anode plate, the first capacitor anode plate and the second capacitor cathode plate is 10 μm to 100 μm, and the width is 10 μm to 100 μm.

9. A method for preparing a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, characterized in that: include: Growing an epitaxial layer on a silicon substrate, and performing mesa etching and isolation etching on the epitaxial layer to form two epitaxial structures; Preparing JTE ring structures on the upper surfaces of the two epitaxial structures respectively, so as to form two quasi-vertical JTE SBDs using the two JTE ring structures later; the two quasi-vertical JTE SBDs respectively form a first charging diode and a second charging diode; Depositing a first passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode region and the cathode region; The anode region corresponds to the anode of the quasi-perpendicular JTE SBD, and the cathode region corresponds to the cathode of the quasi-perpendicular JTE SBD; Depositing a Schottky metal in the anode region and depositing an ohmic metal in the cathode region to form two quasi-vertical JTE SBDs; Depositing a second passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the Schottky metal and the ohmic metal; Preparing a first metal layer on the current device; The first layer of metal includes metals forming a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate and the second charging diode cathode are connected; and the metals forming the first charging diode cathode and the second charging diode cathode are connected to the ohmic metal; A third passivation layer is deposited on the surface of the current device, and holes are opened in the passivation layer to expose the Schottky metal, the metal forming the cathode of the first charging diode and the cathode of the second charging diode, and the metal forming the cathode plate of the first capacitor. A second metal layer, a first interlayer interconnection metal, a second interlayer interconnection metal, and a third interlayer interconnection metal are prepared on the current device; the second metal layer includes metals for forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively; Among them, the first port, the second capacitor cathode plate and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode and the fourth port are connected; wherein the metal forming the first charging diode anode and the second charging diode anode connects the Schottky metal; the first interlayer interconnection metal connects the second port and the first capacitor cathode plate; the second interlayer interconnection metal connects the second charging diode anode and the first charging diode cathode; the third interlayer interconnection metal connects the third port and the second charging diode cathode.

10. The preparation method according to claim 9, characterized in that: The JTE ring structure includes: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure.

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