Perovskite crystalline silicon laminated cell and preparation method thereof

Abstract

The invention relates to the technical field of perovskite crystalline silicon laminated cells, in particular to a perovskite crystalline silicon laminated cell and a preparation method thereof. The perovskite crystal silicon laminated cell comprises a bottom cell, a passivation adjustable light limiting layer, a connecting layer and a top cell which are connected in sequence. In the process of manufacturing the bottom cell of the laminated cell, a PECVD (Plasma Enhanced Chemical Vapor Deposition) method is matched with a mask or laser grooving equipment to grow and passivate the adjustable light limiting layer. The operation can be combined with the current performance of upper and lower bottom cells to grow the passivation light limiting layer, the adjustable range of the refractive index of the passivation light limiting layer material (silicon oxynitride or silicon nitride) is relatively wide, and the adjustment is relatively easy; the current matching problem of the top cell and the bottom cell of the laminated cell is improved. According to the invention, the passivation light limiting layer is manufactured in advance before the cell connection layer is laminated, and the material of the light limiting layer and the deposition pattern can be flexibly designed, so that the passivation performance of the bottom cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of perovskite crystalline silicon stacked cells, and in particular to a perovskite crystalline silicon stacked cell and a preparation method thereof. Background Art

[0002] As the third generation of photovoltaic cells, perovskite solar cells have a simple manufacturing process and can be combined with crystalline silicon cells to form stacked cells. The theoretical efficiency is higher than that of traditional crystalline silicon cells. The common stacking methods of perovskite crystalline silicon stacked cells are divided into two-terminal stacking and four-terminal mechanical stacking. Different stacking methods of stacked cells have different advantages and disadvantages. The two-terminal stacked cells are relatively simple to make, and the production cost of separate auxiliary materials has certain advantages, but there is a problem of current matching between the top cell and the bottom cell; because the two-terminal stacked cells can be understood as upper and lower sub-cells in series, the current in the series circuit depends on the lower part of the sub-cell. The two-terminal stacked cells need to better match the current effects of the perovskite top cell and the crystalline silicon bottom cell, which can further improve the efficiency and performance of the stacked cells. Conventional perovskite crystalline silicon two-terminal stacked cells generally consist of a crystalline silicon bottom cell, a perovskite top cell, and a connecting layer. The currents of the bottom cell and the top cell are independent of each other, and it is relatively difficult to better match the current effects of the top cell and the bottom cell, and there is a risk of current loss in the stacked cell.

[0003] Therefore, how to match the current of the upper and lower batteries in the process of preparing perovskite crystalline silicon two-terminal stacked cells and reduce the unsatisfactory performance of the perovskite / crystalline silicon two-terminal stacked cells caused by poor current matching is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a perovskite crystalline silicon stacked cell and a preparation method thereof. The present invention provides the following technical solutions:

[0005] The present invention provides a perovskite crystalline silicon stacked cell, which comprises a bottom cell, a passivation adjustable light-limiting layer, a connection layer and a top cell which are connected in sequence.

[0006] Furthermore, the bottom cell includes a silicon nitride layer, an aluminum oxide layer, a P-type base doping layer, a first tunneling oxide layer, an N-type silicon wafer, a second tunneling oxide layer and an N-type base doping layer, which are arranged in sequence from bottom to top.

[0007] Furthermore, the first surface of the N-type silicon wafer in contact with the first tunneling oxide layer is a velvet surface, wherein the depth of the velvet surface is 0.5-3.0 um.

[0008] Furthermore, the second surface of the N-type silicon wafer in contact with the second tunnel oxide layer is a velvet surface or a polished surface.

[0009] Furthermore, the second tunneling oxide layer and the first tunneling oxide layer are both silicon oxide;

[0010] The thickness of the second tunneling oxide layer is smaller than that of the first tunneling oxide layer; the thickness of the first tunneling oxide layer and the second tunneling oxide layer ranges from 1.5 to 2 nm.

[0011] Furthermore, the passivation adjustable light-limiting layer is arranged on the surface of the N-type base doping layer;

[0012] The passivation adjustable light-limiting layer is a silicon nitride layer or a silicon oxynitride layer;

[0013] The thickness of the passivation adjustable light-limiting layer is 5-100 nm.

[0014] Furthermore, a plurality of slots are provided on the passivation adjustable light-limiting layer; each slot is evenly distributed on the passivation adjustable light-limiting layer; wherein,

[0015] The groove width is 15-300 μm, and the groove depth is consistent with the thickness of the passivation adjustable light limiting layer;

[0016] The middle spacing of each slot is ≤200 μm, and the total area of ​​the slots accounts for more than 70% of the surface area of ​​the passivation adjustable light-limiting layer.

[0017] Furthermore, the connection layer is laid on the surface of the passivation adjustable light limiting layer;

[0018] The connection layer is made of TCO material.

[0019] Also provided is a method for preparing the perovskite crystalline silicon tandem cell as described above.

[0020] Make bottom battery;

[0021] Depositing a passivation adjustable light-limiting layer on the surface of the bottom cell;

[0022] A connection layer and a top battery are sequentially laid on the surface of the passivation adjustable light-limiting layer.

[0023] Further, a bottom battery is manufactured, comprising:

[0024] Cleaning and texturing an N-type silicon wafer, wherein the first surface of the N-type silicon wafer is a velvet surface, and the second surface of the N-type silicon wafer is a velvet surface or a polished surface;

[0025] On the first surface, sequentially growing a first tunneling oxide layer, depositing a P-type base doping layer, depositing an aluminum oxide layer, and depositing a silicon nitride layer;

[0026] A second tunneling oxide layer is grown and an N-type base doping layer is deposited on the second surface in sequence.

[0027] Furthermore, a passivation adjustable light-limiting layer is deposited on the surface of the bottom cell, including:

[0028] A passivation adjustable light-limiting layer is deposited on the surface of the N-type base doping layer of the bottom cell by a mask method or a laser etching method.

[0029] Further, a passivation adjustable light limiting layer is deposited by a mask method, including:

[0030] Covering the surface of the N-type base doping layer with a mask plate; the slot width of the mask plate is 15-300 μm, the middle spacing of each slot is ≤ 200 μm, and the total slot area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer;

[0031] Depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer covering the mask plate;

[0032] The mask plate is removed, and the silicon nitride layer or silicon nitride oxide layer is a passivation adjustable light limiting layer.

[0033] Furthermore, a passivation adjustable light-limiting layer is deposited by laser etching, comprising:

[0034] Depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer;

[0035] Using laser to groove the silicon nitride layer or silicon oxynitride layer, the groove width is 15-300 μm, the middle spacing of each groove is ≤200 μm, and the total groove area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer;

[0036] The grooved silicon nitride layer or silicon oxynitride layer is a passivation adjustable light limiting layer.

[0037] Furthermore, the connection layer is laid using physical vapor deposition sputtering, magnetron sputtering or thermal evaporation.

[0038] Technical effects and advantages of the present invention:

[0039] 1. In the process of manufacturing the bottom cell of the stacked battery, the present invention adopts the PECVD (plasma enhanced chemical vapor deposition) method with a mask or laser slotting equipment to grow a passivation adjustable light-limiting layer. This operation can be combined with the current performance of the upper and lower bottom cells to grow the passivation light-limiting layer. The refractive index of the passivation light-limiting layer material (silicon oxynitride or silicon nitride) can be adjusted in a wide range and is relatively easy to adjust; the current matching problem of the top cell and the bottom cell of the stacked battery is improved.

[0040] 2. The present invention prepares the passivation light-limiting layer in advance before the stacked battery connection layer, and the light-limiting layer material and deposition pattern can be flexibly designed, and the connection layer can increase the current matching flexibility of the top battery and the bottom battery.

[0041] 3. The present invention prepares the passivation light-limiting layer in advance before the stacked battery connection layer, and the light-limiting layer material and deposition pattern can be flexibly designed, thereby increasing the passivation performance of the bottom battery.

[0042] Other features and advantages of the present invention will be described in the following description, and partly become obvious from the description, or be understood by implementing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a structural diagram of a perovskite crystalline silicon stacked battery provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In order to solve the shortcomings of the existing technology, such as Figure 1 As shown, the present invention discloses a perovskite crystalline silicon stacked cell, the perovskite crystalline silicon stacked cell comprises a bottom cell, a passivation adjustable light-limiting layer, a connection layer and a top cell connected in sequence, wherein the bottom cell comprises a silicon nitride layer, an aluminum oxide layer, a P-type base doping layer (also referred to as a P-poly layer), a first tunneling oxide layer (silicon oxide), an N-type silicon wafer, a second tunneling oxide layer (ultra-thin oxide layer) and an N-type base doping layer (also referred to as an N-poly layer) arranged in sequence from bottom to top. The passivation adjustable light-limiting layer is arranged on the surface of the N-type base doping layer; the connection layer is laid on the surface of the passivation adjustable light-limiting layer. As can be seen from the figure, the first surface of the N-type silicon wafer can also be referred to as the lower surface; the second surface of the N-type silicon wafer can also be referred to as the upper surface.

[0046] In a specific embodiment of the present invention, the first surface of the N-type silicon wafer in contact with the first oxide layer is a velvet surface, that is, the lower surface of the N-type silicon wafer is a velvet surface, wherein the depth of the velvet surface is 0.5-3.0um. The second surface of the N-type silicon wafer in contact with the second oxide layer is a velvet surface or a polished surface, that is, the upper surface of the N-type silicon wafer is a velvet surface or a polished surface.

[0047] In a specific embodiment of the present invention, the second oxide layer and the first oxide layer are also called tunneling oxide layers, and are both made of silicon oxide materials; wherein the thickness of the first oxide layer and the second oxide layer is 1.5-2.5 nm.

[0048] In a specific embodiment of the present invention, the passivation adjustable light-limiting layer is a silicon nitride layer or a silicon oxynitride layer with a thickness of 5-100nm. A plurality of grooves are arranged on the passivation adjustable light-limiting layer; each groove is evenly distributed on the passivation adjustable light-limiting layer; the groove pattern is in the form of a linear strip or a segmented linear strip. The groove width is controlled at 15-300μm, and the groove depth is 5-100nm, which is consistent with the thickness of the passivation adjustable light-limiting layer, effectively removing the adjustable light-limiting layer, and the middle spacing of the groove pattern (the spacing is controlled within 200μm), and the total groove area accounts for more than 70% of the surface area.

[0049] In a specific embodiment of the present invention, the connecting layer is a TCO (transparent conductive oxide) material, such as ITO (indium tin oxide), FTO (fluorine tin oxide), IZO (indium zinc oxide), etc. It can be deposited and manufactured by PVD (physical vapor deposition) sputtering, RPD (magnetron sputtering), thermal evaporation, etc. Figure 1 It can be seen that a part of the TCO material of the connection layer is filled into the grooves of the passivation adjustable light-limiting layer, and a part of it is spread on the surface of the passivation adjustable light-limiting layer.

[0050] In a specific embodiment of the present invention, the top cell structure is a PIN structure (the bottom cell P+ emitter is at the bottom) or a NIP structure (the bottom cell P+ emitter is at the top); wherein the top cell perovskite cell PIN structure is sequentially a hole transport layer (or hole transport layer, Sam layer), a perovskite layer, an electron transport layer, and a metal electrode; the top cell perovskite cell NIP structure is sequentially an electron transport layer, a perovskite layer, a hole transport layer (or a hole transport layer, Sam layer), and a metal electrode.

[0051] The present invention also provides a method for preparing a perovskite crystalline silicon stacked cell, comprising the following steps:

[0052] Step 1: Make the bottom battery;

[0053] Step 2: depositing a passivation adjustable light-limiting layer on the surface of the bottom cell;

[0054] Step 3: Laying a connection layer and a top battery in sequence on the surface of the passivation adjustable light-limiting layer.

[0055] In a specific embodiment of the present invention, step 1: making the bottom battery is specifically performed as follows:

[0056] Step 101: Cleaning and texturing the N-type silicon wafer, wherein the first surface (lower surface) of the N-type silicon wafer is a texturing surface, and the second surface (upper surface) of the N-type silicon wafer is a texturing surface or a polishing surface:

[0057] Step 1011: Using N-type single crystal silicon as the silicon substrate, using deionized water and liquid sodium hydroxide solution to prepare a 1% mass concentration NaOH solution, the silicon substrate is initially polished for 50 seconds, and each time it enters the NaOH solution tank, it enters the water tank for water washing.

[0058] Step 1012: Use deionized water and liquid sodium hydroxide solution to prepare a NaOH solution with a mass concentration of 1.5%, and add a texturing additive solution. The temperature of the tank solution is controlled at 80°C, and the etching time is controlled at 450s. The silicon wafer is anisotropically etched to form a pyramid velvet surface. The size of the pyramid is controlled at 1.5μm, and the integrated inversion rate is controlled within 10%, forming a double-sided velvet structure for an N-type silicon wafer, or a velvet surface on one side and a polished surface on the other side.

[0059] Step 102: Boron diffusion is performed on the first surface (lower surface) by using LPCVD or PECVD, specifically:

[0060] A first tunneling oxide layer is grown on the first surface (lower surface), a Poly layer (polycrystalline silicon layer) is deposited on the first tunneling oxide layer, and then P-poly is doped in a boron diffusion furnace tube to complete the deposition of a P-type base doping layer (P-poly doping layer); preferably, LPCVD is used to introduce oxygen to grow a 2nm tunneling oxide layer at about 600 degrees Celsius; silane gas is introduced at 590°C and a certain pressure to deposit a 200nm thick Poly layer, and then doping is carried out in a 900°C boron diffusion furnace tube for 80 minutes to complete P-poly boron doping.

[0061] or,

[0062] A first tunneling oxide layer is grown on the first surface, and a 200 nm thick Poly layer (polycrystalline silicon layer) is deposited on the first tunneling oxide layer. Boron tribromide or boron trichloride diffusion source is used, the high-temperature doping advancement temperature is controlled at 950°C, and the boron doping high-temperature advancement time is controlled at 80 minutes to form P+ boron doping.

[0063] Through this step, a PN junction is formed. The P-poly boron doping method will enhance the passivation effect and improve the bottom battery performance compared to the P+ boron diffusion method.

[0064] It should be noted that during the process of depositing the tunnel oxide layer, a small amount of tunnel oxide layer may be deposited on the upper surface (second surface) of the silicon wafer. During the boron diffusion process, a borosilicate glass layer (BSG) is generated on the P-poly layer on the lower surface of the silicon wafer and the small amount of tunnel oxide layer deposited on the upper surface of the silicon wafer.

[0065] Step 103: Use HF to clean the borosilicate glass layer (BSG) on the upper surface (second surface) of the bottom cell, and perform alkali polishing or alkali velvet treatment on the upper surface of the bottom cell to form a double-sided velvet structure of the N-type silicon wafer, or a velvet surface on one side and a polished surface on the other side. The specific operation is as follows:

[0066] In a specific embodiment of the present invention, since borosilicate glass is also generated around the bottom battery during the boron diffusion process, a chain etching device is used with a 10% HF solution and the etching time is 150s to completely remove the borosilicate glass layer (BSG) on the upper surface of the bottom battery silicon wafer and the borosilicate glass layer (BSG) around the silicon wafer layer during the preparation process. Then a tank cleaning device is used with a 3.5% mass concentration of NaOH solution, with an alkali polishing or texturing additive solution, the temperature is controlled at 75°C, the etching time is controlled at 300s, and the P-poly doped layer on the upper surface and side (the side is the height position around the bottom battery, and the surface and the surroundings are diffused and doped during the high-temperature diffusion process) and a small amount of SiO deposited on the lower surface of the bottom battery are removed. 2 The tunnel oxide layer is removed and a velvet or polished surface is formed on the upper surface. HF pickling and water washing steps can also be added after alkaline corrosion to ensure a small amount of SiO 2 Remove thoroughness.

[0067] Since the borosilicate glass layer (BSG) of the P-poly layer on the lower surface of the silicon wafer has not been etched by the HF solution, when the NaOH solution is used in combination with alkaline polishing or a texturing additive solution for treatment, the borosilicate glass layer (BSG) on the lower surface of the P-poly layer can effectively block the corrosion of the NaOH solution, which is combined with alkaline polishing or a texturing additive solution, on the lower surface of the P-poly layer.

[0068] During the etching process of step 103, the tunnel oxide layer will be removed because it is too thin, so it will be removed first and then the tunnel oxide layer will be remade as the second oxide layer.

[0069] Step 104: Use LPCVD to sequentially grow an oxide layer, a polycrystalline layer or N-poly on the second surface (upper surface) of the bottom cell, and then perform a phosphorus doping process or an annealing process; the specific operations are as follows: Use high-temperature LPCVD vacuum equipment, through oxygen and silane gas sources, to carry out chemical reactions in a high-temperature environment to prepare a 2.0nm second oxide layer (tunneling oxide layer) and an 80nm polycrystalline silicon dielectric layer on both sides or one side of the silicon wafer; Use high-temperature phosphorus doping equipment to introduce phosphorus oxychloride, oxygen, and nitrogen to complete the deposition of an N-type base doping layer, that is, to form an N-poly doping layer.

[0070] It should be noted that the difference between the double-sided or single-sided preparation of the 2.0 nm second oxide layer refers to the production method during the manufacturing process: the difference between placing one piece in the fixture or placing two pieces face to face, wherein placing two pieces is single-sided, and placing one piece is double-sided.

[0071] Then use high-temperature doping equipment to diffuse phosphorus, introduce phosphorus oxychloride, oxygen, and nitrogen gas sources, and carry out chemical reactions in a high-temperature environment of 800℃-900℃ to complete N-poly doping.

[0072] It should be noted that in this step, during the process of depositing the tunnel oxide layer, there is still a borosilicate glass layer (BSG) on the P-poly layer on the lower surface (first surface) of the silicon wafer, and a small amount of tunnel oxide layer will also be deposited on the P-poly-BSG layer to form a P-poly-BSG-tunnel oxide layer. During the phosphorus diffusion process, a phosphorus silicon glass layer (PSG) will be deposited on the P-poly-BSG-tunnel oxide layer on the lower surface of the silicon wafer and the N-poly doped layer on the upper surface of the silicon wafer.

[0073] Step 105: Cleaning and removing the wrap-around plating: Use the chain equipment HF to remove the phosphosilicate glass on the lower surface of the bottom cell, and then use the trough equipment alkaline solution to remove the polysilicon wrap-around plating layer and the PSG (phosphosilicate glass) and BSG (borosilicate glass) layers; the specific operations are as follows:

[0074] Use chain etching equipment with 15% HF solution, and the etching time is 150s to remove the phosphorus silicon glass on the lower surface (first surface) of the bottom battery and around the silicon wafer. Then use a tank cleaning equipment with 1.2% mass concentration of NaOH solution and de-plating additive solution, the temperature is controlled at 70℃, the etching time is controlled at 300s, and the N-poly doped layer and SiO2 on the lower surface and side of the bottom battery are removed. 2 The tunneling oxide layer is completely removed, and the PSG (phosphosilicate glass) and BSG (borosilicate glass) layers on and below the silicon wafer are completely removed using a 10% concentration HF solution.

[0075] Step 106: Deposit aluminum oxide using PECVD (plasma enhanced chemical vapor deposition) or ALD equipment; the specific operation is as follows:

[0076] Through high temperature vacuum ALD equipment (atomic layer deposition), TMA gas source is introduced to grow a 3.0nm thick aluminum oxide dielectric layer Al on the lower surface of the bottom cell. 2 O 3 ;

[0077] Step 107: Deposit a silicon nitride layer on the lower surface of the bottom cell using PECVD or CVD equipment; the specific operation is as follows:

[0078] A silane and ammonia gas source is introduced through a high-temperature vacuum PECVD device to grow an 80nm silicon nitride dielectric layer on the aluminum oxide dielectric layer.

[0079] In a specific embodiment of the present invention, step 2: depositing a silicon nitride or silicon oxynitride passivation adjustable light-limiting layer on the surface of the bottom cell, comprises: depositing the passivation adjustable light-limiting layer on the surface of the N-type base doping layer of the bottom cell by a mask method or a laser etching method. Depositing the passivation adjustable light-limiting layer by a mask method comprises:

[0080] Step 201: Covering the surface of the N-type base doping layer with a mask; the slot width of the mask is 15-300 μm, the middle spacing of each slot is ≤200 μm, and the total slot area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer;

[0081] Step 202: depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer covering the mask;

[0082] Step 203: removing the mask, the silicon nitride layer or silicon oxynitride layer is a passivation adjustable light limiting layer.

[0083] With the mask, silane, ammonia and nitrous oxide gas sources are introduced through high-temperature vacuum PECVD equipment to grow a silicon nitride dielectric layer with a refractive index of 1.9 or a silicon nitride oxide dielectric layer (refractive index 2.3) on the upper surface of the bottom battery.

[0084] Alternatively, a passivation adjustable light-limiting layer is deposited by laser etching, comprising:

[0085] Step 201 ′: depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer;

[0086] Step 202': Use laser to groove the silicon nitride layer or silicon oxynitride layer, the groove width is 15-300μm, the middle spacing of each groove is ≤200μm, and the total groove area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer; preferably, the laser power is 50W, the frequency is 300Hz, and the speed is 5000mm / s, and the silicon wafer is grooved, and the groove pattern is carried out according to the set pattern.

[0087] Step 203 ′: the grooved silicon nitride layer or silicon oxynitride layer is a passivation adjustable light limiting layer.

[0088] In a specific embodiment of the present invention, step 3: laying down the connection layer using PVD (physical vapor deposition) sputtering, RPD (reactive plasma deposition) or thermal evaporation.

[0089] The top cell structure is a PIN structure (the bottom cell P+ emitter is at the bottom) or a NIP structure (the bottom cell P+ emitter is at the top); wherein the top cell perovskite cell PIN structure is sequentially a hole transport layer (or a hole transport layer, a Sam layer), a perovskite layer, an electron transport layer, and a metal electrode. wherein the top cell perovskite cell NIP structure is sequentially an electron transport layer, a perovskite layer, a hole transport layer (or a hole transport layer, a Sam layer), and a metal electrode.

[0090] In the process of manufacturing the bottom cell of the stacked battery, the present invention adopts the PECVD method with a mask plate or a laser slotting device to grow a passivation adjustable light-limiting layer. This operation can be combined with the current performance of the upper and lower bottom cells to grow the passivation light-limiting layer. The refractive index of the passivation light-limiting layer material (silicon oxynitride or silicon nitride) can be adjusted in a wide range and is relatively easy to adjust; the current matching problem between the top cell and the bottom cell of the stacked battery is improved.

[0091] The invention prepares the passivation light-limiting layer in advance before the stacked battery connection layer, and the light-limiting layer material and deposition pattern can be flexibly designed, thereby increasing the current matching flexibility of the top battery and the bottom battery.

[0092] The present invention manufactures the passivation light-limiting layer in advance before the stacked battery connection layer, and the light-limiting layer material and deposition pattern can be flexibly designed to increase the passivation performance of the bottom battery.

[0093] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A perovskite crystalline silicon tandem battery, characterized in that: The perovskite crystalline silicon stacked cell comprises a bottom cell, a passivation adjustable light-limiting layer, a connection layer and a top cell which are connected in sequence.

2. The titanium ore crystalline silicon laminated battery according to claim 1, characterized in that: The bottom cell comprises a silicon nitride layer, an aluminum oxide layer, a P-type base doping layer, a first tunneling oxide layer, an N-type silicon wafer, a second tunneling oxide layer and an N-type base doping layer which are sequentially arranged from bottom to top.

3. The titanium ore crystalline silicon laminated battery according to claim 2, characterized in that: The first surface of the N-type silicon wafer in contact with the first tunnel oxide layer is a velvet surface, wherein the depth of the velvet surface is 0.5-3.0 um.

4. The titanium ore crystalline silicon laminated battery according to claim 2, characterized in that: The second surface of the N-type silicon wafer in contact with the second tunnel oxide layer is a velvet surface or a polished surface.

5. The titanium ore crystalline silicon laminated battery according to claim 2, characterized in that: The second tunneling oxide layer and the first tunneling oxide layer are both silicon oxide; The thickness of the second tunneling oxide layer is smaller than that of the first tunneling oxide layer; the thickness of the first tunneling oxide layer and the second tunneling oxide layer ranges from 1.5 to 2 nm.

6. The titanium ore crystalline silicon laminated battery according to claim 2, characterized in that: The passivation adjustable light limiting layer is arranged on the surface of the N-type base doping layer; The passivation adjustable light-limiting layer is a silicon nitride layer or a silicon oxynitride layer; The thickness of the passivation adjustable light-limiting layer is 5-100 nm.

7. The titanium ore crystalline silicon laminated battery according to claim 1 or 6, characterized in that: The passivation adjustable light-limiting layer is provided with a plurality of slots; each slot is evenly distributed on the passivation adjustable light-limiting layer; wherein, The groove width is 15-300 μm, and the groove depth is consistent with the thickness of the passivation adjustable light limiting layer; The middle spacing of each slot is ≤200 μm, and the total area of ​​the slots accounts for more than 70% of the surface area of ​​the passivation adjustable light-limiting layer.

8. The titanium ore crystalline silicon laminated battery according to claim 1, characterized in that: The connecting layer is laid on the surface of the passivation adjustable light limiting layer; The connection layer is made of TCO material.

9. The method for preparing a perovskite crystalline silicon tandem battery according to any one of claims 1 to 8, characterized in that: Make bottom battery; Depositing a passivation adjustable light-limiting layer on the surface of the bottom cell; A connection layer and a top battery are sequentially laid on the surface of the passivation adjustable light-limiting layer.

10. The method for preparing the titanium ore crystalline silicon tandem battery according to claim 9, characterized in that: Make a bottom battery, including: Cleaning and texturing an N-type silicon wafer, wherein the first surface of the N-type silicon wafer is a velvet surface, and the second surface of the N-type silicon wafer is a velvet surface or a polished surface; On the first surface, sequentially growing a first tunneling oxide layer, depositing a P-type base doping layer, depositing an aluminum oxide layer, and depositing a silicon nitride layer; A second tunneling oxide layer is grown and an N-type base doping layer is deposited on the second surface in sequence.

11. The method for preparing the titanium ore crystalline silicon laminated battery according to claim 9, characterized in that: A passivation adjustable light-limiting layer is deposited on the surface of the bottom cell, comprising: A passivation adjustable light-limiting layer is deposited on the surface of the N-type substrate doping layer of the bottom cell by a mask method or a laser etching method.

12. The method for preparing the titanium ore crystalline silicon laminated battery according to claim 11, characterized in that: Depositing a passivation adjustable light limiting layer by mask method, including: Covering the surface of the N-type base doping layer with a mask plate; the slot width of the mask plate is 15-300 μm, the middle spacing of each slot is ≤ 200 μm, and the total slot area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer; Depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer covering the mask plate; The mask plate is removed, and the silicon nitride layer or silicon nitride oxide layer is a passivation adjustable light limiting layer.

13. The method for preparing the titanium ore crystalline silicon laminated battery according to claim 11, characterized in that: The passivation adjustable light-limiting layer is deposited by laser etching, including: Depositing a silicon nitride layer or a silicon nitride oxide layer on the surface of the N-type base doping layer; Using laser to groove the silicon nitride layer or silicon oxynitride layer, the groove width is 15-300 μm, the middle spacing of each groove is ≤200 μm, and the total groove area accounts for more than 70% of the surface area of ​​the passivation adjustable light limiting layer; The grooved silicon nitride layer or silicon oxynitride layer is a passivation adjustable light limiting layer.

14. The method for preparing the titanium ore crystalline silicon laminated battery according to claim 9, characterized in that: The connecting layer is laid down using physical vapor deposition sputtering, magnetron sputtering or thermal evaporation.

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