Semiconductor image sensor device

Abstract

The invention provides a semiconductor image sensor device which suppresses the generation of leakage current caused by the interface level and operates stably without reducing the detection sensitivity of a photodiode. A first buried well layer (102-1) and a second buried well layer (102-2) are provided on the front surface side of a silicon support substrate (101), the first buried well layer (102-1) having a first impurity concentration of a second conductivity type at a first position (A) that becomes the back gate of a MOS transistor element (114), and the second buried well layer (102-2) having a second impurity concentration of a second conductivity type at a second position (A) that becomes the back gate of the MOS transistor element (114). The second buried well layer (102-2) has a first impurity concentration of the second conductivity type at a second location (B) spaced apart from the first location (A) and not opposite the back gate; a third buried well layer (103), which is separated from the first buried well layer (102-1) by a predetermined distance in the first direction and the second direction, is formed close to the second buried well layer (102-2), surrounds the first buried well layer (102-1) from both sides, and has a second impurity concentration of the first conductivity type; and a fourth buried well layer (104) which is formed so as to be in contact with the bottom surfaces of the first buried well layer (102-1) and the third buried well layer (103) at a position deeper than the first buried well layer (102-1), and which has a third impurity concentration of the first conductivity type.

Description

Technical Field

[0001] The present invention relates to a semiconductor image sensor device for detecting charged particles such as α-rays, β-rays, and light including X-rays, γ-rays, ultraviolet rays, and infrared rays (hereinafter referred to as charged particles and light). Background Art

[0002] In a semiconductor image sensor device, a photodiode and a transistor element for detecting charged particles and light are generally formed on the same semiconductor substrate.

[0003] As such a semiconductor image sensor device, a device using SOI (Silicon On Insulator) is generally known. SOI is a device in which an insulating layer such as an oxide film called BOX (Buried Oxide) is buried in a silicon substrate.

[0004] Figure 4 : is a cross-sectional view showing a basic structure of a semiconductor image sensor device using an SOI layer.

[0005] Photodiodes for detecting charged particles and light are formed in the first silicon substrate 401 , and processing circuits including transistor elements for amplifying and processing detected signals are formed in the second silicon layer 402 separated by a buried oxide film layer 403 .

[0006] By adopting such a structure, the fill factor of the unit pixel for the photodiode can be sufficiently large, and a circuit of a certain scale can be arranged in the pixel as a pixel unit.

[0007] The photodiode can be realized as a PN junction diode as follows: when the conductivity type of the first silicon substrate 401 is, for example, P type, a desired dose of phosphorus is ion-implanted into the diffusion layer 404 formed on the lower surface of the buried oxide film layer 403 of the first silicon substrate 401 to make it N type.

[0008] In addition, reference numeral 405 denotes a gate electrode of a transistor element formed in the second silicon layer 402, reference numeral 406 denotes an interlayer insulating film, and reference numeral 407 denotes a metal wiring.

[0009] Here, when a reverse bias is applied to form a depletion layer for detecting charged particles and light between the diffusion layer 404 and the first silicon substrate 401, as shown by the dotted line in the figure, the depletion layer expands in the first silicon substrate 401 and the diffusion layer 404. It extends along the interface between the buried oxide film layer 403 and the first silicon substrate 401. Due to the presence of interface energy levels at the interface, leakage current flows through the interface energy levels, which becomes a dark current (dark current) and degrades the sensor characteristics. In addition, in order to improve the detection sensitivity of charged particles and light, a high voltage is applied to the first silicon substrate 401. In this case, the first silicon substrate 401 becomes the back gate of the transistor element formed in the second silicon layer 402, and therefore, the characteristics of the transistor element will change due to the applied voltage, and erroneous operation of the processing circuit composed of the transistor element will occur.

[0010] Therefore, in the construction of the semiconductor image sensor device, (1) not only is it necessary to prevent the depletion layer from extending along the interface between the first silicon substrate 401 and the buried oxide film layer 403 as much as possible, (2) but also structural improvements are needed to suppress the back gate effect of the transistor element formed in the second silicon layer 402.

[0011] In addition, (3) in order to improve the sensitivity of the sensor, it is desired to use the PN junction surface of the photodiode used for detection completely depleted, so it is also necessary to improve the structure.

[0012] As prior art documents that have made the above-mentioned structural improvements, the following Patent Documents 1 to 3 are known.

[0013] Figure 5 The invention is a cross-sectional structural diagram of a semiconductor device described in Patent Document 1, wherein a photodiode and a transistor element are formed on the same semiconductor substrate via an insulating film. In the semiconductor device (100), a buried well (14) formed of impurities having a conductivity type opposite to that of a sensing node (182) of a PN junction of a photodiode (30) is formed at the bottom of a transistor circuit (40), thereby fixing the potential of a region serving as a back gate and suppressing a back gate effect. Furthermore, the buried well (14) is placed close to the photodiode (30) so that a depletion layer does not extend along the interface.

[0014] However, the disadvantage of this structure is that, since the buried well (14) is connected to the sensing node (182), the parasitic capacitance of the sensing node (182) increases, and the sensitivity of the photodiode (30) decreases.

[0015] Figure 6 This is a cross-sectional structural diagram of a semiconductor device described in Patent Document 2.

[0016] In the semiconductor device, the potential of a first buried well (114) formed at the bottom of a transistor circuit (40) and serving as a back gate is fixed to suppress the back gate effect.

[0017] Furthermore, the region including the first buried well (114) is surrounded and separated by a second buried well (116, 118, 119) having a conductivity type opposite to that of the substrate (11).

[0018] Thus, the depletion layer width between the second buried well (116, 118, 119) and the first buried well (114) is increased, thereby reducing the parasitic capacitance.

[0019] However, in this structure, since the depletion layer of the photodiode (30) is formed in a manner extending along the interface (151), the dark current is not reduced, and the conductive type of the sensing node (232) and the second buried well (116, 118, 119) is the same, so the carriers generated by the photoelectric effect in the photodiode (30) are not only absorbed by the sensing node (232) but also by the second buried well (116, 118, 119). Therefore, there is a disadvantage of reduced sensitivity.

[0020] Figure 7 This is a cross-sectional structural diagram of a semiconductor device described in Patent Document 3.

[0021] The semiconductor device (11) comprises: a p-type electrode (24) provided in a second region different from a first region corresponding to a device region, wherein the device region is formed on a supporting substrate (14), the supporting substrate (14) is in contact with a second surface, and the second surface is opposite to a first surface of a BOX layer (20) in contact with an SOI substrate (22); and a p-type hole accumulation layer (18) provided in a region: a region formed in a partial region of the supporting substrate (14) in contact with the second surface of the BOX layer (20), wherein at least The invention relates to a region including a first region and a covering electrode (24), the potential of which is neutralized; an n-type detection electrode (30) formed on a supporting substrate (14) in contact with a second surface of a BOX layer (20); and an n-type barrier layer (16) provided at the following position: between the second surface of the BOX layer (20) and the supporting substrate (14) where an electrode (24) formed on the supporting substrate (14) in contact with the second surface of the BOX layer (20), a hole accumulation layer (18) and a portion of the detection electrode (30) are provided, so as to form a barrier.

[0022] In this structure, the depletion layer extending at the interface is suppressed to a minimum, and the potential of the back gate formed under the pixel circuit (50) can also be fixed by the hole accumulation layer (18) serving as a buried well.

[0023] However, in this structure, current easily leaks from the hole accumulation layer (18) to the supporting substrate (14) through the barrier layer (16). To prevent this, the impurity concentration of the barrier layer (16) needs to be sufficiently high. Furthermore, since the barrier layer (16) and the detection electrode (30) are of the same conductivity type, leakage may occur between adjacent pixels.

[0024] Furthermore, in order to separate adjacent pixels via the barrier layer (16), the following operation is performed: a reverse bias voltage needs to be formed between the hole accumulation layer (18) and the barrier layer (16) and between the supporting substrate (14) and the barrier layer (16), respectively, so that the barrier layer (16) is completely depleted by forming a depletion layer in the barrier layer (16).

[0025] Therefore, there is a problem that the reverse bias voltage applied to the hole accumulation layer (18) and the supporting substrate (14) is limited.

[0026] Prior art literature

[0027] Patent Literature

[0028] Patent Document 1: Japanese Patent Application Publication No. 2013-69924

[0029] Patent Document 2: Japanese Patent Application Publication No. 2014-130920

[0030] Patent Document 3: Japanese Patent Application Publication No. 2019-106519 Summary of the invention

[0031] Problem that the invention aims to solve

[0032] The present invention has been completed in view of the above-mentioned prior art, and an object of the present invention is to provide a semiconductor image sensor device that does not reduce the sensitivity of the photodiode formed in the supporting substrate, can suppress the generation of leakage current caused by the interface energy level, and can easily completely deplete the supporting substrate even if the restriction on the applied voltage is relaxed.

[0033] Technical solutions for solving technical problems

[0034] Figure 1The semiconductor image sensor device of the present invention is shown. The semiconductor image sensor device of the present invention is formed by stacking an SOI layer (110) and a silicon support substrate (101), wherein the SOI layer (110) is in contact with a first surface of an insulating layer (107) to form a MOS transistor element (114) constituting a pixel circuit; the silicon support substrate (101) is in contact with a second surface of the SOI layer (110) opposite to the first surface to form a photodiode for detecting charged particles and light, and has a first impurity concentration of a first conductivity type, and is characterized in that a region (P) corresponding to one pixel includes:

[0035] i: a first buried well layer (102-1) and a second buried well layer (102-2), which are on the surface side of the silicon support substrate (101) and are in contact with the second surface of the insulating layer (107), the first buried well layer (102-1) having a first impurity concentration of a second conductivity type at a first position (A) serving as a back gate of the MOS transistor element (114), and the second buried well layer (102-2) having a first impurity concentration of a second conductivity type at a second position (B) separated from the first position (A) and not opposite to the back gate;

[0036] ii: a third buried well layer (103), which is separated from the first buried well layer (102-1) by a predetermined distance in the first direction and the second direction, is close to the second buried well layer (102-2), is formed in a manner of surrounding the first buried well layer (102-1) from both sides, and has a second impurity concentration of the first conductivity type;

[0037] iii: a fourth buried well layer (104), which is formed at a deeper position than the first buried well layer (102-1) in a manner of being in contact with the bottom surfaces of the first buried well layer (102-1) and the third buried well layer (103), and has a third impurity concentration of the first conductivity type;

[0038] iv: a contact diffusion layer (105) formed at desired positions of the first buried well layer (102-1) and the second buried well layer (102-2) and having a second impurity concentration of a second conductivity type,

[0039] v: forming a back diffusion layer (106) having a fourth impurity concentration of the first conductivity type on the back side of the silicon support substrate (101),

[0040] The potential (V BB ) is applied between the contact diffusion layer (105) and the back diffusion layer (106) of the first buried well layer (102-1),

[0041] The contact diffusion layer (105) of the second buried well layer (102-2) is used as a member for transmitting a signal generated in the depletion layer of the silicon support substrate (101) when charged particles and light are detected to the MOS transistor element (114).

[0042] Furthermore, the semiconductor image sensor device of the present invention is characterized in that the first conductivity type is P type, and the first impurity concentration of the silicon support substrate (101) is a doping concentration of 1×10 12 cm -3 ~1×10 14 cm -3 The second impurity concentration of the third buried well layer (103) is 110 to 150 eV with an ion implantation energy of 1×10 12 cm -2 ~5×10 13 cm -2 The third impurity concentration of the fourth buried well layer (104) is determined by ion implantation energy of 360 to 400 eV and a dose of 1×10 12 cm -2 ~5×10 13 cm -2 The fourth impurity concentration of the back diffusion layer (106) is higher than the third impurity concentration.

[0043] The second conductivity type is N type, and the first impurity concentration of the first buried well layer (102-1) and the second buried well layer (102-2) is 280 to 320 eV with an ion implantation energy of 0.5×10 12 cm -2 ~5×10 13 cm -2 The second impurity concentration of the contact diffusion layer (105) is determined by the energy of 10 to 50 KeV and the dose of 1×10 15 cm -2 ~1×10 16 cm -2 The range determines the concentration.

[0044] Furthermore, the semiconductor image sensor device of the present invention is characterized in that the thickness of the silicon support substrate (101) is 700 to 800 μm, the thickness of the insulating layer (107) is 10 to 200 nm, and the thickness of the SOI layer (110) is 10 to 1000 nm.

[0045] Effects of the Invention

[0046] According to the structure of the present invention, for example, when the pixel size is 20×20 μm2 When Figure 4 Compared with the conventional structure shown in the figure, the area of ​​the depletion layer in contact with the interface of the silicon support substrate 101 and the insulating layer 107 is about 7%, and the dark current can also be reduced to about 7%. In addition, the electrons generated by the photodiode in the depletion layer formed in the silicon support substrate 101 can all be recovered by the second buried well layer 102-2 as the detection node, thereby being able to become a highly sensitive sensor. In addition, the second buried well layer 102-2 that suppresses the formation of the surface depletion layer can also be used as an electrode that can suppress the back gate effect of the MOS transistor element 114, thereby ensuring stable operation. Structurally, only two types of buried well layers are essentially formed in the silicon support substrate 101 in which the photodiode is formed, which reduces the additional process and reduces the manufacturing cost.

[0047] Therefore, a semiconductor image sensor device can be realized that does not reduce the sensitivity of the photodiode formed in the supporting substrate, can suppress the generation of leakage current caused by the interface energy level, and can easily completely deplete the supporting substrate even if the restriction on the applied voltage is relaxed. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a cross-sectional structural diagram of a semiconductor image sensor device according to an embodiment of the present invention.

[0049] FIG. 2( 1 ) is a cross-sectional view (part 1 ) illustrating each manufacturing step of a method for manufacturing a semiconductor image sensor device according to the present invention.

[0050] FIG. 2 ( 2 ) is a cross-sectional view (part 2 ) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0051] FIG. 2 ( 3 ) is a cross-sectional view (part 3 ) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0052] FIG. 2( 4 ) is a cross-sectional view (part 4 ) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0053] FIG. 2 ( 5 ) is a cross-sectional view (part 5 ) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0054] FIG. 2(6) is a cross-sectional view (part six) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0055] FIG. 2(7) is a cross-sectional view (part seven) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0056] FIG. 2( 8 ) is a cross-sectional view (part eight) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0057] FIG. 2(9) is a cross-sectional view (part 9) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0058] FIG. 2 ( 10 ) is a cross-sectional view (part 10 ) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0059] FIG. 2 ( 11 ) is a cross-sectional view (part 11) illustrating each manufacturing step of the manufacturing method of the semiconductor image sensor device according to the present invention.

[0060] Figure 3 The simulated concentration profile of the buried well layer fabricated according to the present invention is shown.

[0061] Figure 4 : is a cross-sectional view showing a basic structure of a semiconductor image sensor device using an SOI layer.

[0062] Figure 5 This is a cross-sectional structural diagram of a semiconductor device described in Patent Document 1.

[0063] Figure 6 This is a cross-sectional structural diagram of a semiconductor device described in Patent Document 2.

[0064] Figure 7 This is a cross-sectional structural diagram of a semiconductor device described in Patent Document 3.

[0065] Description of Reference Numerals

[0066] 101: First silicon support substrate

[0067] 102-1: first buried well layer, first N-type buried well layer

[0068] 102-2: Second buried well layer

[0069] 103: third buried well layer, P-type third buried well layer

[0070] 104: fourth buried well layer, P-type fourth buried well layer

[0071] 105: Contact diffusion layer

[0072] 106: Back diffusion layer

[0073] 110: SOI layer

[0074] 114: MOS transistor element. DETAILED DESCRIPTION

[0075] First, the structure of a semiconductor imaging device according to an embodiment of the present invention will be described.

[0076] Figure 1 FIG. 1 shows a cross-sectional structure of a region P corresponding to one pixel of an image sensor. Region P is a region sandwiched between line XX and line YY in the figure and is arranged at the same interval. Figure 1 It is repeated in the first direction (left direction) and the second direction (right direction).

[0077] These pixels are arranged two-dimensionally to form an imaging area of ​​a semiconductor image sensor. Here, a pixel has a function of detecting the charge generated in the pixel and performing time domain modulation, and is called a lock pixel.

[0078] like Figure 1 As shown, the semiconductor image sensor device 1000 of this embodiment has an SOI (Silicon On Insulator) layer 110 on which a MOS transistor element 114 constituting a pixel circuit is formed, stacked via an insulating layer 107 called a BOX (Buried Oxide) layer on a silicon supporting substrate 101 having a first conductivity type and a first impurity concentration.

[0079] In addition, although the MOS transistor element 114 constituting the pixel circuit is composed of a plurality of transistor elements, Figure 1 Only one transistor element is representatively shown in the figure, 112 denotes a gate insulating film, and 113 denotes a gate.

[0080] A first buried well layer 102-1 is formed on the surface side of the silicon support substrate 101, the first buried well layer 102-1 is in contact with the insulating layer 107, and has a first impurity concentration of the second conductivity type at a position A serving as a back gate of the MOS transistor element 114. In addition, a second buried well layer 102-2 is formed at a position B spaced apart from the position A and not facing the back gate, also having the first impurity concentration of the second conductivity type.

[0081] A third buried well layer 103 having a second impurity concentration of the first conductivity type is formed at a position spaced a predetermined distance from the first buried well layer 102-1 in the first direction and the second direction (left and right) and close to the second buried well layer 102-2 so as to surround the first buried well layer 102-1 from both sides.

[0082] Furthermore, a fourth buried well layer 104 having a third impurity concentration of the first conductivity type is formed at a position deeper than the first buried well layer 102 - 1 so as to be in contact with the bottom surfaces of the first buried well layer 102 - 1 and the third buried well layer 103 .

[0083] A contact diffusion layer 105 having a second conductivity type and a second impurity concentration is formed at desired positions of the first buried well layer 102 - 1 and the second buried well layer 102 - 2 .

[0084] A back surface diffusion layer 106 having a fourth impurity concentration of the first conductivity type is formed on the back surface side of the silicon supporting substrate 101 .

[0085] The potential V required to completely deplete the silicon support substrate 101 BB It is applied between the contact diffusion layer 105 and the back diffusion layer 106 of the first buried well layer 102 - 1 .

[0086] The contact diffusion layer 105 of the second buried well layer 102-2 is used as a member for transmitting a signal generated in the depletion layer of the silicon supporting substrate 101 when charged particles and light are detected to the MOS transistor element 114. In addition, 108 denotes an interlayer insulating film, and 109 denotes a metal wiring.

[0087] Here, the first conductivity type is P type, and the first impurity concentration of the silicon support substrate 101 is a doping concentration of 1×10 12 cm -3 ~1×10 14 cm -3 The second impurity concentration of the third buried well layer 103 is 110 to 150 eV with an ion implantation energy of 1×10 12 cm -2 ~5×10 13 cm -2 The third impurity concentration of the fourth buried well layer 104 is determined by the ion implantation energy of 360 to 400 eV and the dose of 1×10 12 cm -2 ~5×10 13 cm -2 The fourth impurity concentration of the back diffusion layer 106 is higher than the third impurity concentration, the second conductivity type is N type, and the first impurity concentration of the first buried well layer 102-1 and the second buried well layer 102-2 is determined by the ion implantation energy of 280 to 320 eV and the dose of 0.5×10 12 cm -2 ~5×10 13 cm -2 The second impurity concentration of the contact diffusion layer 105 is determined by the energy of 10 to 50 KeV and the dose of 1×10 15 cm -2 ~1×10 16 cm -2 The range determines the concentration.

[0088] In addition, the thickness of the silicon support substrate 101 is 700 to 800 μm, the thickness of the insulating layer 107 is 10 to 200 nm, and the thickness of the SOI layer 110 is 10 to 1000 nm.

[0089] exist Figure 1 In the semiconductor image sensor shown, the second buried well layer 102-2 is used as a sensing node for collecting carriers and is formed with the minimum size allowed by semiconductor manufacturing technology. Therefore, the parasitic capacitance of the sensing node is suppressed to a low level, thereby achieving high sensitivity. In addition, the first buried well layer 102-1 of the same conductivity type is formed at a distance sufficient to ensure voltage resistance from the second buried well layer 102-2, so that the area of ​​the depletion layer (indicated by the dotted line in the figure) extending from the PN junction of the photodiode and the interface contact area of ​​the silicon support substrate 101 and the insulating layer 107 is minimized to suppress the generation of dark current.

[0090] The third buried well layer 103 and the fourth buried well layer 104 of opposite conductivity types are formed in a manner of surrounding the first buried well layer 102-1. Therefore, as shown in the figure, the carriers generated in the depletion layer of the photodiode due to the photoelectric effect of charged particles and light are not collected by the third buried well layer 103 and the fourth buried well layer 104, but are all collected by the second buried well layer 102-2 serving as a sensing node, thereby preventing a decrease in detection sensitivity.

[0091] In addition, in order to make the depletion layer as wide as possible, it is preferred to make it completely depleted. For this purpose, the silicon support substrate 101 is preferably very thin with a doping concentration of 1×10 12 cm -3 ~1×10 14 cm -3 ) of a P-type silicon substrate. The second buried well layer 102-2 as a sensing node is formed with a medium concentration (1×10 15 cm -3 ~1×10 18 cm -3 ) of the N-type diffusion layer. In addition, a high concentration (1×10 18 cm -3 ~1×10 21 cm -3 )'s contact diffusion layer 105.

[0092] Furthermore, ohmic connection can be established with the metal wiring 109 via the contact diffusion layer 105 .

[0093] In addition, in order to prevent the depletion layer for reducing dark current from extending at the interface between the silicon support substrate 101 and the insulating layer 107, a medium concentration (1×10 15 cm -3 ~1×10 18 cm-3 ) The first N-type buried well layer 102-1 serves as an electrode for suppressing the back gate effect of the MOS transistor element 114 formed in the SOI layer 110, and thus can be fixed at a fixed potential, usually fixed at the ground (GND) level.

[0094] In this state, when a desired voltage V is applied between the first buried well layer 102-1 and the back diffusion layer 106 BB When the depletion layer Figure 1 Expand as enclosed by the dashed line.

[0095] At this time, among the electron-hole pairs generated in the depletion layer, the electrons may be collected by the second buried well layer 102-2 as the detection node, or may be collected by the first buried well layer 102-1. In this case, there is a concern about a decrease in sensitivity. In the present invention, in order to suppress such a decrease in sensitivity, by configuring a P-type fourth buried well layer 104 and a P-type third buried well layer 103 formed at a deeper position than the first buried well layer 102-1, as shown by the dotted line, the depletion layer from the first buried well layer 102-1 other than the detection node and the depletion layer from the second buried well layer 102-2 as the detection node can be separated.

[0096] Furthermore, since all electrons (-) generated in the depletion layer in the silicon supporting substrate 101 are collected by the second buried well layer 102-2 as a detection node, the generation of dark current is suppressed while maintaining high sensitivity to charged particles and light.

[0097] Furthermore, in the above-mentioned embodiment, a P-type silicon support substrate 101 is used. If an N-type silicon support substrate 101 is used, the conductivity type of the buried well layer may be set to a P-type.

[0098] Next, a method for manufacturing a semiconductor image sensor device according to the present invention will be described.

[0099] Figure 1 The semiconductor image sensor device shown in FIG. Figure 2(1) to Figure 2(11) The manufacturing method of each step shown is used for manufacturing.

[0100] The starting material for the manufacturing is a common SOI wafer as shown in Figure 2 (1). The SOI wafer has a very low concentration (1×10 12 cm -3 ~1×10 14 cm -3) is formed on a P-type substrate 201 with a thickness of 10 to 200 nm, and a silicon layer 210 with a thickness of 10 to 1000 nm is formed thereon. At this time, there is no restriction on the doping concentration of the upper silicon layer 210.

[0101] As shown in FIG2(2), the silicon layer 210 is patterned using a known element separation method such as LOCOS or STI. Then, as shown in FIG2(3), in order to form the buried N well layer 202, a photoresist 214 is formed in the region where the buried N well layer 202 is not formed by a known photolithography technique, and phosphorus is implanted using the photoresist 214 as a mask. The implantation conditions are energy of 280 to 320 KeV, preferably 300 KeV, and a dose of 0.5×10 12 Up to 5×10 13 cm -2 , preferably 1.0×10 12 cm -2 After the ion implantation, the photoresist 214 is removed.

[0102] Similarly, as shown in FIG. 2 (4), in order to form the buried P well layer 203, boron ion implantation is performed using a known photolithography technique and a photoresist 214 as a mask. The implantation conditions are an energy of 110 to 150 KeV, preferably 130 KeV, and a dose of 1×10 12 Up to 5×10 13 cm -2 , preferably 5×10 12 cm -2 After the ion implantation, the photoresist 214 is removed. Further, as shown in FIG2(5), in order to form the buried P well layer 204, boron ion implantation is performed using the known photolithography technique and the photoresist 214 as a mask. In order to form a portion deeper than the buried N well layer 202, the energy is 360 to 400 KeV, preferably 380 KeV, and the dose is 1×10 12 Up to 5×10 13 cm -2 , preferably 5×10 12 cm -2 After the ion implantation, the photoresist 214 is removed.

[0103] At this time, the ion implantation conditions of the buried P well layer 203 and the buried P well layer 204 are adjusted in advance so that the buried P well layer 203 and the buried P well layer 204 can be connected at a concentration higher than that of the silicon support substrate 201. After that, the manufacturing process of the MOSFET is entered. As shown in FIG. 2 (6), the SOI layer 210 is first oxidized in an oxidizing atmosphere at 700 to 900°C, and an oxide film that will become a gate insulating film 212 is formed with a thickness of 1 to 5 nm. Polycrystalline silicon that will become a gate is deposited with a thickness of 100 to 300 nm on the entire surface, and phosphorus is doped to reduce resistance. In addition, the polycrystalline silicon is patterned by known photolithography and etching to form a gate 213.

[0104] Using the gate 213 as a mask, arsenic and other group 5 impurity ions are implanted into the N-type MOSFET, and boron and other group 3 impurity ions are implanted into the P-type MOSFET to form a diffusion layer 211 that will become the source / drain of the MOSFET, thereby completing the MOSFET. At this time, the MOSFET is configured on the buried N-well layer 202, and the buried N-well layer 202 acts as the back gate of the MOSFET.

[0105] As the next step, in order to form a high-concentration N+ layer 205 at the detection node, as shown in FIG2(7), an opening is formed in the buried oxide film layer 207 using known photolithography and etching techniques. This opening is formed using a high-concentration diffusion layer using a large current ion implantation device, because, in this case, the implantation energy is limited, which prevents the buried oxide film 207 from being implanted into silicon when the thickness is 100 to 200 nm.

[0106] Next, phosphorus ions are implanted into the opening using the buried oxide film 207 as a mask. The implantation conditions are energy of 10 to 50 KeV, preferably 30 KeV, and a dose of 1×10 15 Up to 1×10 16 cm -2 , preferably 5×10 15 cm -2 After the ion implantation, a heat treatment is performed to activate the implanted impurities, including the buried well, by performing a rapid thermal annealing (RTA) at 900° C. to 1100° C., preferably at 1000° C., for 10 seconds to 100 seconds, preferably 30 seconds.

[0107] In addition, as shown in FIG2(8), an interlayer insulating film 208 is deposited at about 500 to 700 nm. In order to make electrical contact with the detection node, a contact is formed by known photolithography and etching techniques, which are not shown in the figure, a barrier metal is formed, tungsten is deposited in the contact, and excess tungsten deposited on the upper part of the interlayer insulating film 208 is removed by chemical mechanical polishing (CMP), as shown in FIG2(9), to form a tungsten-filled contact.

[0108] In addition, in order to electrically transmit the signal of the detection node, as shown in FIG2 (10), a metal wiring 209 is formed by ordinary aluminum sputtering, photolithography and etching technology. Not shown in the figure, thereafter, as needed, an upper wiring layer is formed by forming an insulating film layer, forming a via hole and forming a metal wiring, and a protective film is formed and a pad opening is performed. Further, after grinding the back side, as shown in FIG2 (11), a high-concentration P+ layer 206 on the back side is formed by ion implantation and laser annealing from the back side.

[0109] Figure 3 The concentration distribution of each main part obtained by the manufacturing method of the recommended conditions (based on simulation) is shown. The buried N well 102-1 is reliably formed, and the buried P well 104 as an electron barrier is formed thereunder. In addition, the buried P wells 103 and 104 are in contact with each other at a concentration sufficiently higher than the substrate concentration. In addition, the distribution of the buried N well 102-1 and the buried P well 104 in the depth direction is also substantially the same, and it can be confirmed that the target structure has been achieved.

Claims

1. A semiconductor image sensor device, which is composed of a stacked SOI layer (110) and a silicon support substrate (101), wherein the SOI layer (110) is in contact with a first surface of an insulating layer (107) to form a MOS transistor element (114) constituting a pixel circuit; and the silicon support substrate (101) is in contact with a second surface of the SOI layer (110) opposite to the first surface to form a photodiode for detecting charged particles and light, and has a first impurity concentration of a first conductivity type, characterized in that: include: i: a first buried well layer (102-1) and a second buried well layer (102-2), which are on the surface side of the silicon support substrate (101) and are in contact with the second surface of the insulating layer (107), the first buried well layer (102-1) having a first impurity concentration of a second conductivity type at a first position (A) serving as a back gate of the MOS transistor element (114), and the second buried well layer (102-2) having a first impurity concentration of a second conductivity type at a second position (B) separated from the first position (A) and not opposite to the back gate; ii: a third buried well layer (103), which is separated from the first buried well layer (102-1) by a predetermined distance in the first direction and the second direction, is close to the second buried well layer (102-2), is formed in a manner of surrounding the first buried well layer (102-1) from both sides, and has a second impurity concentration of the first conductivity type; iii: a fourth buried well layer (104), which is formed at a deeper position than the first buried well layer (102-1) in a manner of being in contact with the bottom surfaces of the first buried well layer (102-1) and the third buried well layer (103), and has a third impurity concentration of the first conductivity type; iv: a contact diffusion layer (105) formed at desired positions of the first buried well layer (102-1) and the second buried well layer (102-2) and having a second impurity concentration of a second conductivity type, v: forming a back diffusion layer (106) having a fourth impurity concentration of the first conductivity type on the back side of the silicon support substrate (101), The potential (V BB ) is applied between the contact diffusion layer (105) and the back diffusion layer (106) of the first buried well layer (102-1), The contact diffusion layer (105) of the second buried well layer (102-2) is used as a member for transmitting a signal generated in the depletion layer of the silicon support substrate (101) when charged particles and light are detected to the MOS transistor element (114).

2. The semiconductor image sensor device according to claim 1, wherein: The first conductivity type is P type, and the first impurity concentration of the silicon support substrate (101) is a doping concentration of 1×10 12 cm -3 ~1×10 14 cm -3 The second impurity concentration of the third buried well layer (103) is 110 to 150 eV with an ion implantation energy of 1×10 12 cm -2 ~5×10 13 cm -2 The third impurity concentration of the fourth buried well layer (104) is determined by ion implantation energy of 360 to 400 eV and a dose of 1×10 12 cm -2 ~5×10 13 cm -2 The fourth impurity concentration of the back diffusion layer (106) is higher than the third impurity concentration. The second conductivity type is N type, and the first impurity concentration of the first buried well layer (102-1) and the second buried well layer (102-2) is 280 to 320 eV with an ion implantation energy of 0.5×10 12 cm -2 ~5×10 13 cm -2 The second impurity concentration of the contact diffusion layer (105) is determined by the energy of 10 to 50 KeV and the dose of 1×10 15 cm -2 ~1×10 16 cm -2 The range determines the concentration.

3. The semiconductor image sensor device according to claim 1, wherein: The thickness of the silicon support substrate (101) is 700-800 μm, the thickness of the insulating layer (107) is 10-200 nm, and the thickness of the SOI layer (110) is 10-1000 nm.

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