Method for forming a silicon surface lead structure

Abstract

The present invention relates to a method for forming a silicon surface lead structure, which can form an insulated lead structure on the surface of an ordinary silicon wafer. The method comprises: providing a substrate, wherein the substrate material is low-resistance silicon, and the substrate is sequentially formed along a first direction parallel to the substrate surface into a first isolation region, a lead region, and a second isolation region; forming a first oxide layer covering the top surface of the substrate; removing a portion of the first oxide layer and a portion of the thickness of the substrate material below it to form an isolation trench; forming a second oxide layer covering the sidewalls of the isolation trench; isotropically etching the bottom surface of the isolation trench in a gaseous state to form an extended trench; and oxidizing the extended trench using a wet oxygen process to form a fourth oxide layer covering the surface of the extended trench. The fourth oxide layer connects two adjacent sidewalls of the extended trench and, together with the second oxide layer, forms a lead isolation structure. The present invention can reduce device cost while improving device performance.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for forming a silicon surface lead structure. Background Art

[0002] Micro-electro-mechanical systems (MEMS) are a technology that integrates micromechanical and electronic components and is widely used in various sensors and actuators. Ensuring the effective input and output of electrical signals is crucial in the design and manufacture of MEMS devices. Common solutions currently include using metal or low-resistance silicon as conductors, isolated by insulating materials such as silicon oxide. While these solutions are widely used in MEMS device manufacturing, they pose challenges such as introducing thermal stress and increasing production costs. Consequently, it is necessary to develop a new lead structure to reduce device cost and improve performance. Summary of the Invention

[0003] The technical problem solved by the embodiments of the present application is to provide a method for forming a silicon surface lead structure, which can reduce device cost while improving device performance.

[0004] To solve the above problems, an embodiment of the present application provides a method for forming a silicon surface lead structure, comprising the following steps: providing a substrate, wherein the material of the substrate is low-resistance silicon, and the substrate is sequentially composed of a first isolation region, a lead region and a second isolation region along a first direction parallel to the substrate surface; forming a first oxide layer covering the top surface of the substrate; removing part of the first oxide layer and part of the thickness of the substrate material thereunder, and forming isolation trenches in the first isolation region and the second isolation region respectively; forming a second oxide layer, wherein the second oxide layer covers the side walls of the isolation trench; isotropically corroding the bottom surface of the isolation trench in a gaseous state to form an extended trench below the isolation trench, wherein one side wall of the extended trench extends to the lead region; oxidizing the extended trench using a wet oxygen process to form a fourth oxide layer covering the surface of the extended trench, wherein the fourth oxide layer connects two adjacent side walls of the extended trench and forms a lead isolation structure together with the second oxide layer.

[0005] Optionally, in the step of providing a substrate, the resistivity of the low-resistance silicon is less than 0.02Ω·cm.

[0006] Optionally, the step of removing part of the first oxide layer and part of the thickness of the substrate material thereunder to form isolation trenches in the first isolation region and the second isolation region, respectively, further includes: removing part of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer; using the patterned first oxide layer as a mask, removing part of the thickness of the substrate material to form an isolation trench surrounded by the remaining substrate.

[0007] Optionally, in the step of removing part of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer, an inductively coupled plasma process is used to remove part of the first oxide layer located in the first isolation region and the second isolation region; in the step of using the patterned first oxide layer as a mask to remove part of the thickness of the substrate material to form an isolation channel surrounded by the remaining substrate, a deep reactive ion etching process is used to remove part of the thickness of the substrate material.

[0008] Optionally, the step of forming a second oxide layer, which covers the side walls of the isolation trench, further includes: using a thermal oxidation process to form a second oxide layer covering the side walls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench; and using an inductively coupled plasma process to remove the third oxide layer to expose the bottom surface of the isolation trench.

[0009] Optionally, in the step of forming a second oxide layer covering the sidewalls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench by using a thermal oxidation process, the thickness of the second oxide layer and the third oxide layer is 0.1 micron to 1 micron.

[0010] Optionally, in the step of isotropically etching the bottom surface of the isolation trench in the gaseous state to form an extended trench below the isolation trench, the distance between two adjacent sidewalls of the extended trench is 2 microns to 6 microns.

[0011] Optionally, in the step of isotropically etching the bottom surface of the isolation trench and forming an extended trench below the isolation trench, XeF2 gas is used to etch the bottom surface of the isolation trench.

[0012] Optionally, in the step of oxidizing the extended channel using a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the fourth oxide layer and the second oxide layer are interconnected to form a lead isolation structure, which insulates and isolates a portion of the thickness of the base material on the upper part of the lead area, thereby forming a lead structure and a lead isolation structure surrounding the lead structure on the silicon surface.

[0013] Optionally, after the step of oxidizing the extended trench using a wet oxygen process to form a fourth oxide layer covering the surface of the extended trench, the method further includes: removing the first oxide layer on the surface of the lead region to expose the underlying substrate material.

[0014] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0015] The method for forming a silicon surface lead structure provided in an embodiment of the present application utilizes an etching process and a thermal oxidation process to form interconnected oxide layers in the lead area, providing good electrical isolation and mechanical support for the lead structure. In addition, the thermal stress of the oxide layer and the lead structure are matched with each other, which can reduce thermal stress problems caused by temperature fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0017] Figures 1-9 This is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a silicon surface wire junction provided by the present invention. DETAILED DESCRIPTION

[0018] As known from the background art, the existing use of metal or low-resistance silicon as conductive wires has problems such as introducing thermal stress and increasing production costs.

[0019] Specifically, if metal is used as a conductor, the mismatch in thermal expansion coefficients between the metal and silicon-based materials can cause thermal stress in the device when the temperature changes. This thermal stress can affect the device's structural stability and long-term reliability. Furthermore, the deposition process for metal conductors not only increases production costs but also increases process complexity.

[0020] On the other hand, if low-resistance silicon is used as the conductor, such as SOI (Silicon on Insulator) silicon wafers, low-resistance silicon is used in the device layer and processed into conductors. Although the thermal expansion coefficient mismatch problem of metal conductors can be solved to a certain extent, this method will significantly increase the cost of the silicon wafer.

[0021] To solve the above technical problems, an embodiment of the present invention provides a method for forming a silicon surface lead structure, comprising the following steps:

[0022] Providing a substrate, wherein the substrate is made of low-resistance silicon, and the substrate is sequentially divided into a first isolation region, a lead region, and a second isolation region along a first direction parallel to a surface of the substrate;

[0023] forming a first oxide layer covering the top surface of the substrate;

[0024] removing a portion of the first oxide layer and a portion of the thickness of the substrate material thereunder to form isolation trenches in the first isolation region and the second isolation region respectively;

[0025] forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench;

[0026] Gaseously etching the bottom surface of the isolation trench to form an extended trench below the isolation trench, wherein a sidewall of the extended trench extends to the lead region;

[0027] The extended channel is oxidized by a wet oxygen process to form a fourth oxide layer connecting two adjacent side walls of the extended channel.

[0028] The method for forming a silicon surface lead structure provided in this embodiment uses an etching process and a thermal oxidation process to form an interconnected oxide layer in the lead area, providing good electrical isolation and mechanical support for the lead structure. The thermal stress of the oxide layer and the lead structure are matched with each other, which can reduce the thermal stress problem caused by temperature fluctuations.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 9 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a silicon surface lead structure provided by the present invention.

[0031] refer to Figure 1 , providing a substrate 110, wherein the material of the substrate 110 is low-resistance silicon, and the substrate 110 is sequentially divided into a first isolation region 102a, a lead region 101 and a second isolation region 102b along a first direction parallel to the substrate surface.

[0032] The material of the substrate 110 is low-resistance silicon. Low-resistance silicon is a silicon material with a relatively low resistivity. The resistivity of low-resistance silicon is generally less than 0.02Ω·cm. In some embodiments, it can be further less than 0.01Ω·cm. Specifically, the resistivity of low-resistance silicon can range from 0.001Ω·cm to 0.005Ω·cm. Low-resistance silicon can be obtained by doping, that is, introducing impurity atoms into the silicon lattice to change its conductivity. In some embodiments, the substrate 110 is a low-resistance silicon wafer, which is a silicon wafer made of low-resistance silicon material and has a relatively low resistivity.

[0033] Since low-resistance silicon has a low resistivity, it can be used to form lead structures to ensure that electrical signals can be effectively transmitted; and since the thermal expansion coefficient of low-resistance silicon matches that of other silicon-based materials, the semiconductor devices subsequently manufactured will not produce thermal stress problems when the temperature fluctuates.

[0034] The substrate 110 can be further divided into a lead region 101 and a first isolation region 102a and a second isolation region 102b located on either side of the lead region 101. The lead structure to be formed later is located in the lead region 101, and the isolation structures formed on either side of the lead structure are located in the first isolation region 102a and the second isolation region 102b, respectively. The isolation structures can be silicon oxide layers of a certain thickness to provide electrical isolation for the leads.

[0035] refer to Figure 2 , forming a first oxide layer 120 covering the top surface of the substrate 110 .

[0036] In some embodiments, the first oxide layer 120 is a silicon oxide layer, and the silicon oxide layer can completely cover the top surface of the substrate 110 .

[0037] As a specific example, a plasma enhanced chemical vapor deposition (PECVD) process may be used to grow silicon dioxide on the top surface of the substrate 110 to form the first oxide layer 120 having a thickness of approximately 1 micron to 3 microns.

[0038] refer to Figure 3 and Figure 4 , a portion of the first oxide layer 120 and a portion of the thickness of the substrate material thereunder are removed, and isolation trenches 130a and 130b are formed in the first isolation region 102a and the second isolation region 102b, respectively.

[0039] In some embodiments, this step may further include:

[0040] refer to Figure 3 , removing portions of the first oxide layer 120 located in the first isolation region 102 a and the second isolation region 102 b to expose the top surface of the substrate 110 on both sides of the lead region 101 to form a patterned first oxide layer 121 .

[0041] The patterned first oxide layer 121 is formed with openings that expose the top surface of the substrate 110. The openings are respectively located in the first isolation region 102a and the second isolation region 102b and adjacent to the lead region 101, thereby exposing the substrate material on both sides of the lead region 101.

[0042] As an example, a photolithography and etching process may be used to form the patterned first oxide layer 121. The specific steps are as follows:

[0043] forming a patterned layer (not shown) on the first oxide layer 120 , wherein the patterned layer exposes a portion of the first oxide layer 120 ;

[0044] The pattern layer is used as a mask to etch the first oxide layer 120 exposed by the pattern layer, and the remaining first oxide layer material after etching serves as the patterned first oxide layer 121 .

[0045] In this embodiment, the graphic layer can be a graphic photoresist layer. After the photoresist layer is formed, a dry etching process is used to etch the first oxide layer 120 located below the graphic layer opening along the graphic layer opening. During the etching process, the part of the first oxide layer material not covered by the photoresist will be removed, while the part of the first oxide layer material covered by the photoresist will remain.

[0046] As a specific example, an inductively coupled plasma (ICP) process can be used to remove the first oxide layer material. ICP etching is a high-density plasma source etching technology with a high etching rate and high anisotropy. Under the action of high-density plasma, the exposed first oxide layer material is quickly and accurately removed until the underlying substrate material is exposed. Due to its high anisotropy, an almost perfect vertical sidewall can be formed after the ICP etching is completed.

[0047] After the etching is completed, the remaining photoresist is removed using an appropriate solvent or oxygen plasma treatment, leaving the patterned first oxide layer 121.

[0048] refer to Figure 4 Using the patterned first oxide layer 121 as a mask, a portion of the substrate material is removed to form isolation trenches 130 a and 130 b surrounded by the remaining substrate 111 .

[0049] In this step, a dry etching process can be used to remove a portion of the substrate material. After etching, the remaining substrate 111 forms a groove on each side of the lead area 101, namely, isolation trenches 130a and 130b. The isolation trenches 130a and 130b are prepared for the subsequent formation of isolation structures.

[0050] In some embodiments, the width of the isolation trenches 130a and 130b may be equal to or slightly smaller than the width of the lead region 101, for example, 5 microns to 20 microns; the depth of the isolation trenches 130a and 130b may be equal to or slightly smaller than their own width.

[0051] As a specific example, a deep reactive ion etching (DRIE) process can be used to etch the substrate material to form the isolation trenches 130a and 130b. DRIE is a plasma-based dry etching technology that uses a high-density plasma source to generate active ions and free radicals. These active molecules can selectively remove material from the silicon wafer. The DRIE process can form nearly vertical sidewalls on the substrate 110, facilitating the subsequent formation of fine device structures.

[0052] refer to Figure 5 and Figure 6 , forming a second oxide layer 131, which covers the sidewalls of the isolation trenches 130a and 130b.

[0053] In some embodiments, this step may further include:

[0054] refer to Figure 5 A second oxide layer 131 covering the sidewalls of the isolation trenches 130a and 130b and a third oxide layer 132 covering the bottom surfaces of the isolation trenches 130a and 130b are formed by a thermal oxidation process.

[0055] In this step, a thermal oxidation process is used to grow silicon oxide, thereby forming a silicon dioxide layer on the sidewalls and bottom surfaces of isolation trenches 130a and 130b. By controlling the parameters of the thermal oxidation process, the thickness of the generated silicon dioxide can be controlled to be between 0.1 microns and 1 micron. The thermal oxidation process uses oxygen or water vapor to react with silicon at high temperatures to form silicon dioxide. During the thermal oxidation process, some silicon material is consumed.

[0056] The second oxide layer 131 formed in this step can provide electrical isolation for the subsequently formed leads, improve mechanical stability, and protect the silicon structure shielded by the second oxide layer 131 from gaseous corrosion in subsequent steps.

[0057] refer to Figure 6 , the third oxide layer 132 is removed until the bottom surfaces of the isolation trenches 130 a and 130 b are exposed.

[0058] In this step, a dry etching process can be used to remove the third oxide layer 132 located at the bottom surface of the isolation trenches 130a and 130b, while retaining the second oxide layer 131 located at the sidewalls of the isolation trenches 130a and 130b. It will be understood that during the etching process, the second oxide layer 131 at the sidewalls of the isolation trenches 130a and 130b may also be slightly etched, but most of the thickness of the second oxide layer material will be retained.

[0059] As a specific example, an inductively coupled plasma (ICP) process can be used to remove silicon oxide used as an isolation layer material. ICP etching is a high-density plasma source etching technology with a high etching rate and a high degree of anisotropy. Under the action of high-density plasma, the exposed third oxide layer 132 is quickly and accurately removed until the substrate material under the third oxide layer 132 is exposed. Due to the high anisotropy, an almost perfect vertical sidewall can be formed after etching, and the oxide layer material outside the target portion can be retained to the maximum extent to serve as a protective layer in the subsequent gaseous etching step.

[0060] refer to Figure 7 The bottom surfaces of the isolation trenches 130 a and 130 b are isotropically etched in a gaseous state to form extended trenches 140 a and 140 b below the isolation trenches 130 a and 130 b . The sidewalls of the extended trenches 140 a and 140 b extend to the lead region 101 .

[0061] In this step, a gaseous etching process is used to etch the bottom surfaces of the exposed isolation trenches 130a and 130b. The gaseous etching process uses specific gas chemicals to react with the substrate material at the bottom surfaces of the isolation trenches 130a and 130b, removing a certain thickness of the substrate material in all directions, thereby forming corresponding extended trenches 140a and 140b below the isolation trenches 130a and 130b, respectively.

[0062] Specifically, in this embodiment, xenon difluoride (XeF2) gas is used to perform gaseous etching on the substrate 111 to form a gaseous etched substrate 112. The XeF2 gaseous etching process is highly selective to different materials, especially to silicon materials, with a good selectivity ratio between silicon and silicon dioxide. In addition, the gaseous etching process has an isotropic characteristic, and the XeF2 gaseous etching effect is uniform in all directions of the silicon material, not only in the direction perpendicular to the first direction ( Figure 7 A certain thickness of silicon material can be removed in the vertical direction) or in the direction parallel to the first direction ( Figure 7 A certain thickness of silicon material is removed (in the horizontal direction) to extend the sidewalls of the extended trenches 140a and 140b horizontally to the lead region 101. Gas etching can be used to remove the base material in a certain space below the lead region 101, leaving a support structure of a certain width below the lead region 101. This support structure can be used to support the lead structure above and will be completely oxidized in a subsequent step to provide electrical isolation for the lead structure above.

[0063] The width of the support structure, that is, the distance between two adjacent sidewalls of the extended channel, is d. In some embodiments, the distance d may range from 2 microns to 6 microns.

[0064] In some embodiments, the substrate material can be silicon with a specific crystal orientation, and a wet etching process can be used to etch the substrate material. The wet etching process is anisotropic and can selectively etch in the lateral direction (the first direction in the figure), thereby reducing the thickness of the support structure in the first direction. Specifically, DRIE can be used to first etch down to a certain thickness, and then the wet etching process can be performed after the sidewalls are exposed.

[0065] refer to Figure 8 The extended channels 140a and 140b are oxidized by a wet oxygen process to form a fourth oxide layer 141 covering the surfaces of the extended channels 140a and 140b. The fourth oxide layer 141 connects the two adjacent extended channel sidewalls and the second oxide layer 131 to form a lead isolation structure.

[0066] In this step, a wet oxygen process is used to grow silicon oxide on the surface of the extended trenches 140a and 140b, thereby forming a silicon dioxide layer on the sidewalls and bottom surfaces of the extended trenches 140a and 140b. In the wet oxygen process, oxygen and water vapor react with silicon atoms on the surfaces of the extended trenches 140a and 140b under high temperature conditions to form a uniform silicon dioxide layer. By introducing water vapor during the oxidation process, the wet oxygen process can accelerate the oxidation rate and improve the quality of the oxide film. While the wet oxygen process is used to generate silicon dioxide, a portion of the silicon material is also consumed. By controlling the parameters of the wet oxygen process, the thickness of the generated silicon dioxide layer can be controlled. In some embodiments, the thickness of the oxide layer formed by the wet oxygen process can be between 3 microns and 8 microns, thereby forming a fourth oxide layer 141 that covers the surface of the extended trench and connects the sidewalls of two adjacent extended trenches. The fourth oxide layer 141 can provide mechanical support and electrical isolation for the lead structure above. Specifically, the fourth oxide layer 141 and the second oxide layer 131 formed above are interconnected to form a lead isolation structure. The lead isolation structure insulates and isolates the base material on the upper part of the lead area 101, thereby forming a lead structure 150 and a lead isolation structure surrounding the lead structure 150 on the silicon surface.

[0067] In some embodiments, the support structure can be pretreated before the extended channels 140a and 140b are oxidized using a wet oxygen process. Specifically, the silicon material forming the support structure can be processed into porous silicon before the wet oxygen oxidation. In the subsequent oxidation step, the porous silicon is more easily oxidized into silicon oxide.

[0068] refer to Figure 9 , remove the first oxide layer on the surface of the lead area 101 until the underlying substrate material is exposed.

[0069] In this step, the oxide layer covering the surface of the lead area 101 is further removed to expose the low-resistance silicon underlying the substrate material, thereby exposing the top surface of the lead structure 150. The side and bottom surfaces of the lead structure 150 are respectively covered by the second oxide layer 131 and the fourth oxide layer 141, thereby achieving complete electrical isolation.

[0070] It can be seen that the method for forming a silicon surface lead structure provided in the embodiment of the present application utilizes an etching process and a thermal oxidation process to form mutually penetrating oxide layers in the lead area, providing good electrical isolation and mechanical support for the lead structure, and the thermal stress of the oxide layer and the lead structure match each other, which can reduce the thermal stress problem caused by temperature fluctuations.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similarities between the various embodiments can be referred to in conjunction with each other. For device embodiments, since they are generally similar to method embodiments, their description is relatively simple, and for relevant details, reference can be made to the description of the method embodiments.

[0072] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A method for forming a silicon surface lead structure, characterized in that: The following steps are involved: Providing a substrate, wherein the substrate is made of low-resistance silicon, and the substrate is sequentially divided into a first isolation region, a lead region, and a second isolation region along a first direction parallel to a surface of the substrate; forming a first oxide layer covering the top surface of the substrate; removing a portion of the first oxide layer and a portion of the thickness of the substrate material thereunder to form isolation trenches in the first isolation region and the second isolation region respectively; forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench; isotropically etching the bottom surface of the isolation trench in a gaseous state to form an extended trench below the isolation trench, wherein a sidewall of the extended trench extends to the lead region; The extended channel is oxidized by a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel. The fourth oxide layer communicates with two adjacent side walls of the extended channel and forms a lead isolation structure together with the second oxide layer.

2. The method for forming a silicon surface lead structure according to claim 1, wherein: In the step of providing a substrate, the resistivity of the low-resistance silicon is less than 0.02Ω·cm.

3. The method for forming a silicon surface lead structure according to claim 1, wherein: The step of removing a portion of the first oxide layer and a portion of the thickness of the substrate material thereunder to form isolation trenches in the first isolation region and the second isolation region further includes: removing portions of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer; Using the patterned first oxide layer as a mask, a portion of the substrate material is removed to form an isolation trench surrounded by the remaining substrate.

4. The method for forming a silicon surface lead structure according to claim 3, wherein: In the step of removing the portion of the first oxide layer located in the first isolation region and the second isolation region to expose the top surface of the substrate on both sides of the lead region to form a patterned first oxide layer, the portion of the first oxide layer located in the first isolation region and the second isolation region is removed using an inductively coupled plasma process; In the step of using the patterned first oxide layer as a mask to remove a portion of the thickness of the substrate material to form an isolation trench surrounded by the remaining substrate, a deep reactive ion etching process is used to remove a portion of the thickness of the substrate material.

5. The method for forming a silicon surface lead structure according to claim 1, wherein: The step of forming a second oxide layer, wherein the second oxide layer covers the sidewalls of the isolation trench, further comprises: forming a second oxide layer covering the sidewalls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench by a thermal oxidation process; The third oxide layer is removed by an inductively coupled plasma process until a bottom surface of the isolation trench is exposed.

6. The method for forming a silicon surface lead structure according to claim 5, wherein: In the step of forming a second oxide layer covering the sidewalls of the isolation trench and a third oxide layer covering the bottom surface of the isolation trench by using a thermal oxidation process, the thickness of the second oxide layer and the third oxide layer is 0.1 micron to 1 micron.

7. The method for forming a silicon surface lead structure according to claim 1, wherein: In the step of isotropically etching the bottom surface of the isolation trench in the gaseous state to form an extended trench below the isolation trench, the distance between two adjacent sidewalls of the extended trench is 2 microns to 6 microns.

8. The method for forming a silicon surface lead structure according to claim 1, wherein: The gaseous isotropic etching is performed on the bottom surface of the isolation trench. In the step of forming an extended trench below the isolation trench, XeF2 gas is used to etch the bottom surface of the isolation trench.

9. The method for forming a silicon surface lead structure according to claim 1, wherein: In the step of oxidizing the extended channel using a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the fourth oxide layer and the second oxide layer are interconnected to form a lead isolation structure. The lead isolation structure insulates and isolates a portion of the thickness of the base material on the upper part of the lead area, thereby forming a lead structure and a lead isolation structure surrounding the lead structure on the silicon surface.

10. The method for forming a silicon surface lead structure according to claim 1, wherein: After the step of oxidizing the extended channel by a wet oxygen process to form a fourth oxide layer covering the surface of the extended channel, the method further includes: The first oxide layer on the surface of the lead region is removed until the underlying substrate material is exposed.

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