Method, system and device for detecting internal defects of silicon-based LD-MOS (low-density metal oxide semiconductor) tube device and medium

Abstract

The invention discloses a method, a system, a device and a medium for detecting internal defects of a silicon-based LD-MOS (Low-Density Metal Oxide Semiconductor) transistor device, which comprises the following steps of: carrying out detailed regional test on a gate-source electrode and a gate-drain electrode of the silicon-based LD-MOS transistor device, and adjusting reverse bias voltage, filling pulse voltage, pulse width and test period to obtain the internal defects of the silicon-based LD-MOS transistor device. Capturing a transient capacitance signal of the silicon-based LD-MOS tube device; a voltage pulse excitation test is carried out in a variable temperature environment, capacitance transient response signal diagrams of the device at different temperatures are recorded, and signal processing is carried out on the capacitance transient response signal diagrams by utilizing Fourier transform to obtain a relationship between a Fourier coefficient of capacitance change at different frequencies and the temperature; therefore, key parameters such as a defect level and a capture cross section of a deep level trap in a silicon-based LD-MOS tube device can be accurately revealed; and meanwhile, the deep energy level transient Fourier spectrum is adopted to carry out regional testing on the silicon-based LD-MOS transistor device, so that more comprehensive information about internal defects of the device can be obtained, and the detection efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic device detection, and relates to a method, system, device and medium for detecting internal defects of a silicon-based LD-MOS tube device. Background Art

[0002] Since the silicon-based LD-MOS tube device forms a channel through two diffusion processes and has asymmetric characteristics, there are multiple pn structures or MOS structures inside the device. In the manufacturing process of silicon-based LD-MOS tube devices, it is easier to introduce unintentional doping defects or inherent deep energy level impurities. These impurities or defects will reduce the carrier lifetime inside the device, further leading to the degradation of the performance of the silicon-based LD-MOS device during use, such as reducing the channel carrier mobility, increasing the leakage current and changing the threshold voltage. At present, there is little in-depth analysis of the types and states of defects generated after the device is irradiated, and there are problems such as the inability to quickly detect and low detection efficiency. Summary of the invention

[0003] The purpose of the present invention is to solve the problem in the prior art that deep energy level traps inside silicon-based LD-MOS tube devices cannot be detected quickly and the detection efficiency is low, and to provide a method, system, device and medium for detecting internal defects of silicon-based LD-MOS tube devices.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A method for detecting internal defects of a silicon-based LD-MOS tube device, comprising:

[0006] Applying an external voltage to the silicon-based LD-MOS tube device to obtain a CV curve of the silicon-based LD-MOS tube device;

[0007] Based on the CV curve of silicon-based LD-MOS tube devices, the voltage range corresponding to the space charge region of the semiconductor device is analyzed to determine the reverse bias voltage Vr and the fill pulse voltage Vp;

[0008] In the constant temperature mode, based on the current temperature, the test period Tw and the pulse width Tp are determined according to the reverse bias voltage Vr and the fill pulse voltage Vp;

[0009] Based on the pulse cycle width and different test temperatures, the silicon-based LD-MOS tube device is excited by voltage pulses to obtain the deep energy level transient spectrum signal diagram;

[0010] Based on the deep energy level transient spectrum signal diagram, the signal peak is fitted at selected points to obtain the Arrhenius curve. According to the Arrhenius curve, the defect information existing in the detected device is obtained to obtain the currently measured defect type.

[0011] A further improvement of the present invention is:

[0012] Furthermore, an external voltage is applied to the silicon-based LD-MOS tube device to obtain the CV curve of the silicon-based LD-MOS tube device, specifically:

[0013] Install the LD-MOS device on the variable temperature test bench of the deep level transient spectrometer, ensure that the silicon-based lateral diffused metal oxide semiconductor device is connected to the deep level transient spectrometer and remains stable, and short-circuit the source of the LD-MOS device with the bulk end; when the gate of the LD-MOS device is connected to the high-level connector, the source of the LD-MOS device is connected to the low-level connector, and the drain is suspended, set the voltage scanning range to obtain the gate-source capacitance Cgs, and test the MOS structure on the source side of the LD-MOS device;

[0014] When the gate of the LD-MOS device is connected to a high-level connector, the drain of the LD-MOS device is connected to a low-level connector, and the source is left floating, the voltage scanning range is set to obtain the gate-drain capacitance Cgd, and the MOS structure on the drain side of the LD-MOS device is tested.

[0015] Furthermore, based on the CV curve of the LD-MOS tube device, the voltage range corresponding to the space charge region of the semiconductor device is analyzed, and the reverse bias voltage Vr and the fill pulse voltage Vp are determined. Specifically, based on the gate-source capacitance Cgs and the gate-drain capacitance Cgd curves, the doping types of the MOS structure corresponding to Cgs and Cgd are analyzed respectively, the voltage range corresponding to the space charge region is judged, and the values ​​of the reverse bias voltage Vr and the fill pulse voltage Vp are determined.

[0016] Further, according to the reverse bias voltage Vr and the fill pulse voltage Vp, the test period Tw and the pulse width Tp are determined, specifically:

[0017] The values ​​of reverse bias voltage Vr and fill pulse voltage Vp are fixed, pulse width Tp is set to default value in constant temperature mode, test cycle Tw is changed, and the optimal test cycle Tw is determined by the capacitance depletion relaxation state of transient capacitance in different test cycles;

[0018] Fix the reverse bias voltage Vr, fill pulse voltage Vp and test period Tw, change the pulse width Tp, observe whether the transient capacitance signal converges under different pulse widths, and determine the optimal pulse width Tp when there is no noise signal.

[0019] Furthermore, based on the pulse cycle width and different test temperatures, the LD-MOS tube device is excited by voltage pulses to obtain the deep energy level transient spectrum signal diagram, specifically:

[0020] For different wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the following tests are performed respectively:

[0021] After the temperature drops to the set lowest point, it starts to increase the temperature according to the set step length;

[0022] At each test temperature point, a voltage pulse is applied to the device under test, and the transient capacitance signal at each sampling temperature point is recorded;

[0023] The transient capacitance signal is subjected to Fourier transform, and the time domain signal is converted into a frequency domain signal, and the relationship between the Fourier coefficient of capacitance change at different frequencies and temperature is obtained, that is, the deep energy level transient spectrum signal diagram, in which each coefficient corresponds to a time constant.

[0024] Furthermore, based on the deep energy level transient spectrum signal diagram, the signal peak is fitted at selected points to obtain the Arrhenius curve, which is specifically:

[0025] For the two wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the specific methods include:

[0026] By fitting the deep energy level transient spectrum signal graph under different time constants, the Arrhenius diagram related to time constant and temperature is obtained, and the ordinate is ln(τ·v th ·N V,C ), the abscissa is 1000 / T, and the energy level and capture cross section of the defect are obtained based on the Arrhenius diagram fitting, specifically:

[0027]

[0028] Where τ is the time constant, v th is the emission rate of hot electrons or holes, N V,C is the effective state density in the valence band or conduction band, E a is the defect activation energy, k is the Boltzmann constant, T is the Kelvin temperature, γ is the entropy factor, and σ is the capture cross-sectional area.

[0029] Furthermore, the defect information existing in the detected device is obtained according to the Arrhenius curve, and the defect type currently measured is obtained, specifically: based on the positive peak and negative peak of the deep energy level transient spectrum signal diagram under different time constants, where the positive peak represents the majority carrier and the negative peak represents the minority carrier; combined with the MOS structure doping type tested by the two wiring tests of the gate-source capacitance Cgs and the gate-drain capacitance Cgd, when the doping type is p-type, the majority carrier is a hole and the minority carrier is an electron; when the doping type is n-type, the majority carrier is an electron and the minority carrier is a hole, so as to judge that the defect type currently measured is an electron trap (E i, i = 1, 2, 3 ...), or a hole trap (H i , i=1, 2, 3…); for n-channel LD-MOS tube devices, Cgs is p-type doped and Cgd is n-type doped.

[0030] A silicon-based LD-MOS tube device internal defect detection system, comprising:

[0031] An acquisition module, wherein the acquisition module applies an external voltage to the silicon-based LD-MOS tube device to acquire a CV curve of the silicon-based LD-MOS tube device;

[0032] An analysis module, which analyzes the voltage range corresponding to the space charge region of the semiconductor device based on the CV curve of the silicon-based LD-MOS tube device, and determines the reverse bias voltage Vr and the fill pulse voltage Vp;

[0033] A determination module, wherein the determination module determines a test period Tw and a pulse width Tp based on a current temperature, a reverse bias voltage Vr and a fill pulse voltage Vp in a constant temperature mode;

[0034] A voltage pulse excitation module, which performs voltage pulse excitation on silicon-based LD-MOS tube devices based on pulse cycle width and different test temperatures to obtain a deep energy level transient spectrum signal diagram;

[0035] A fitting module, based on the deep energy level transient spectrum signal diagram, performs point fitting on the signal peak to obtain an Arrhenius curve, obtains defect information existing in the detected device according to the Arrhenius curve, and obtains the currently measured defect type.

[0036] A terminal device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0037] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention performs detailed regional tests on the gate-source and gate-drain of a silicon-based LDMOS device, and captures the transient capacitance signal of the silicon-based LDMOS by adjusting the reverse bias, fill pulse voltage, pulse width and test cycle; performs voltage pulse excitation test in a variable temperature environment, records the capacitance transient response signal diagram of the device at different temperatures, performs signal processing on the signal by using Fourier transform, obtains the relationship between the Fourier coefficient of capacitance change at different frequencies and temperature, thereby accurately revealing the key parameters such as the defect energy level and capture cross section of the deep energy level trap in the silicon-based LDMOS device; and simultaneously uses deep energy level transient Fourier spectroscopy to perform regional tests on the silicon-based LDMOS device, thereby obtaining more comprehensive information on the internal defects of the device and improving the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a schematic flow chart of the internal defect detection method of the silicon-based LD-MOS tube device of the present invention;

[0042] Figure 2 Schematic diagram of gate-source capacitance Cgs and gate-drain capacitance Cgd of a silicon-based LD-MOS tube device;

[0043] Figure 3 Schematic diagram of deep energy level transient spectrum signals of gate-source and gate-drain of silicon-based LD-MOS tube devices at different temperatures;

[0044] Figure 4 A schematic diagram of the Arrhenius curve corresponding to the deep energy level transient spectrum signal diagram measured for the gate-source and gate-drain of a silicon-based LD-MOS tube device;

[0045] Figure 5 It is a schematic diagram of the structure of the internal defect detection system of the silicon-based LD-MOS tube device of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0050] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0051] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0053] See also Figure 1 The present invention discloses a method for detecting internal defects of a silicon-based LD-MOS tube device, comprising:

[0054] S101, applying an external voltage to the silicon-based LD-MOS tube device to obtain a CV curve of the silicon-based LD-MOS tube device;

[0055] Install the LD-MOS device on the variable temperature test bench of the deep level transient spectrometer, ensure that the silicon-based lateral diffused metal oxide semiconductor device is connected to the deep level transient spectrometer and remains stable, and short-circuit the source of the LD-MOS device with the bulk end; when the gate of the LD-MOS device is connected to the high-level connector, the source of the LD-MOS device is connected to the low-level connector, and the drain is suspended, set the voltage scanning range to obtain the gate-source capacitance Cgs, and test the MOS structure on the source side of the LD-MOS device;

[0056] When the gate of the LD-MOS device is connected to a high-level connector, the drain of the LD-MOS device is connected to a low-level connector, and the source is left floating, the voltage scanning range is set to obtain the gate-drain capacitance Cgd, and the MOS structure on the drain side of the LD-MOS device is tested.

[0057] S102, based on the CV curve of the silicon-based LD-MOS tube device, analyzing the voltage range corresponding to the space charge region of the semiconductor device, and determining the reverse bias voltage Vr and the fill pulse voltage Vp;

[0058] See also Figure 2 Based on the gate-source capacitance Cgs and gate-drain capacitance Cgd curves, the doping types of the MOS structure corresponding to Cgs and Cgd are analyzed respectively, the voltage range corresponding to the space charge region is judged, and the values ​​of the reverse bias voltage Vr and the fill pulse voltage Vp are determined.

[0059] S103, in a constant temperature mode, based on the current temperature, according to the reverse bias voltage Vr and the fill pulse voltage Vp, determine the test period Tw and the pulse width Tp;

[0060] The values ​​of reverse bias voltage Vr and fill pulse voltage Vp are fixed, pulse width Tp is set to default value in constant temperature mode, test cycle Tw is changed, and the optimal test cycle Tw is determined by the capacitance depletion relaxation state of transient capacitance in different test cycles;

[0061] Fix the reverse bias voltage Vr, fill pulse voltage Vp and test period Tw, change the pulse width Tp, observe whether the transient capacitance signal converges under different pulse widths, and determine the optimal pulse width Tp when there is no noise signal.

[0062] S104, based on the pulse cycle width and different test temperatures, voltage pulse excitation is performed on the silicon-based LD-MOS tube device to obtain a deep energy level transient spectrum signal diagram;

[0063] See also Figure 3 , Figure 3 H1 represents hole trap 1, and E1 represents electron trap 1. For different wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the following tests are performed respectively:

[0064] After setting the test parameters, set the test temperature scanning interval and the step length of adjacent sampling temperature points according to the temperature range that the device under test can withstand. The vacuum environment in the working chamber needs to reach at least 1×10 -5 Pa, the low temperature system starts to work;

[0065] After the temperature drops to the set lowest point, it starts to increase the temperature according to the set step length;

[0066] At each test temperature point, a voltage pulse is applied to the device under test, and the transient capacitance signal at each sampling temperature point is recorded;

[0067] The transient capacitance signal is subjected to Fourier transform, and the time domain signal is converted into a frequency domain signal, and the relationship between the Fourier coefficient of capacitance change at different frequencies and temperature is obtained, that is, the deep energy level transient spectrum signal diagram, in which each coefficient corresponds to a time constant.

[0068] S105, based on the deep energy level transient spectrum signal diagram, performing point fitting on the signal peak to obtain an Arrhenius curve, obtaining defect information existing in the detected device according to the Arrhenius curve, and obtaining the currently measured defect type.

[0069] See also Figure 4 , for the two wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the specific method includes: by selecting points for fitting the deep energy level transient spectrum signal diagram under different time constants, the Arrhenius diagram related to time constant and temperature is obtained, and the ordinate is ln(τ·v th ·N V,C ), the abscissa is 1000 / T, and the energy level and capture cross section of the defect are obtained based on the Arrhenius diagram fitting, specifically:

[0070]

[0071] Where τ is the time constant, ν th is the emission rate of hot electrons or holes, N V,C is the effective state density in the valence band or conduction band, E ais the defect activation energy, k is the Boltzmann constant, T is the Kelvin temperature, γ is the entropy factor, and σ is the capture cross-sectional area.

[0072] According to the Arrhenius curve, the defect information existing in the detected device is obtained, and the defect type currently measured is obtained, specifically: based on the positive peak and negative peak of the deep energy level transient spectrum signal diagram under different time constants, where the positive peak represents the majority carrier and the negative peak represents the minority carrier; combined with the MOS structure doping type tested by the two wiring tests of the gate-source capacitance Cgs and the gate-drain capacitance Cgd, when the doping type is p-type, the majority carrier is a hole and the minority carrier is an electron; when the doping type is n-type, the majority carrier is an electron and the minority carrier is a hole, so as to judge that the defect type currently measured is an electron trap (E i , i = 1, 2, 3 ...), or a hole trap (H i , i=1, 2, 3…); for n-channel LD-MOS tube devices, Cgs is p-type doped and Cgd is n-type doped.

[0073] See also Figure 5 The present invention discloses a silicon-based LD-MOS tube device internal defect detection system, comprising:

[0074] An acquisition module, wherein the acquisition module applies an external voltage to the silicon-based LD-MOS tube device to acquire a CV curve of the silicon-based LD-MOS tube device;

[0075] An analysis module, which analyzes the voltage range corresponding to the space charge region of the semiconductor device based on the CV curve of the silicon-based LD-MOS tube device, and determines the reverse bias voltage Vr and the fill pulse voltage Vp;

[0076] A determination module, wherein the determination module determines a test period Tw and a pulse width Tp based on a current temperature, a reverse bias voltage Vr and a fill pulse voltage Vp in a constant temperature mode;

[0077] A voltage pulse excitation module, which performs voltage pulse excitation on silicon-based LD-MOS tube devices based on pulse cycle width and different test temperatures to obtain a deep energy level transient spectrum signal diagram;

[0078] A fitting module, based on the deep energy level transient spectrum signal diagram, performs point fitting on the signal peak to obtain an Arrhenius curve, obtains defect information existing in the detected device according to the Arrhenius curve, and obtains the currently measured defect type.

[0079] A terminal device is provided in one embodiment of the present invention. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the above-mentioned method embodiments are implemented. Alternatively, when the processor executes the computer program, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0080] The computer program may be divided into one or more modules / units, and the one or more modules / units are stored in the memory and executed by the processor to accomplish the present invention.

[0081] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0082] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0083] The memory may be used to store the computer programs and / or modules, and the processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory.

[0084] If the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0085] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for detecting internal defects of a silicon-based LD-MOS tube device, characterized in that: include: Applying an external voltage to the silicon-based LD-MOS tube device to obtain a CV curve of the silicon-based LD-MOS tube device; Based on the CV curve of silicon-based LD-MOS tube devices, the voltage range corresponding to the space charge region of the semiconductor device is analyzed to determine the reverse bias voltage Vr and the fill pulse voltage Vp; In the constant temperature mode, based on the current temperature, the test period Tw and the pulse width Tp are determined according to the reverse bias voltage Vr and the fill pulse voltage Vp; Based on the pulse cycle width and different test temperatures, the silicon-based LD-MOS tube device is excited by voltage pulses to obtain the deep energy level transient spectrum signal diagram; Based on the deep energy level transient spectrum signal diagram, the signal peak is fitted at selected points to obtain the Arrhenius curve. According to the Arrhenius curve, the defect information existing in the detected device is obtained to obtain the currently measured defect type.

2. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 1, characterized in that: The external voltage is applied to the silicon-based LD-MOS tube device to obtain the CV curve of the silicon-based LD-MOS tube device, specifically: Install the LD-MOS device on the variable temperature test bench of the deep level transient spectrometer, ensure that the silicon-based lateral diffused metal oxide semiconductor device is connected to the deep level transient spectrometer and remains stable, and short-circuit the source of the LD-MOS device with the bulk end; when the gate of the LD-MOS device is connected to the high-level connector, the source of the LD-MOS device is connected to the low-level connector, and the drain is suspended, set the voltage scanning range to obtain the gate-source capacitance Cgs, and test the MOS structure on the source side of the LD-MOS device; When the gate of the LD-MOS device is connected to a high-level connector, the drain of the LD-MOS device is connected to a low-level connector, and the source is left floating, the voltage scanning range is set to obtain the gate-drain capacitance Cgd, and the MOS structure on the drain side of the LD-MOS device is tested.

3. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 2, characterized in that: The CV curve based on the silicon-based LD-MOS tube device is used to analyze the voltage range corresponding to the space charge region of the semiconductor device, and determine the reverse bias voltage Vr and the fill pulse voltage Vp. Specifically, based on the gate-source capacitance Cgs and the gate-drain capacitance Cgd curves, the doping types of the MOS structure corresponding to Cgs and Cgd are analyzed respectively, the voltage range corresponding to the space charge region is judged, and the values ​​of the reverse bias voltage Vr and the fill pulse voltage Vp are determined.

4. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 3, characterized in that: The test period Tw and the pulse width Tp are determined according to the reverse bias voltage Vr and the fill pulse voltage Vp, specifically: The values ​​of reverse bias voltage Vr and fill pulse voltage Vp are fixed, pulse width Tp is set to default value in constant temperature mode, test cycle Tw is changed, and the optimal test cycle Tw is determined by the capacitance depletion relaxation state of transient capacitance in different test cycles; Fix the reverse bias voltage Vr, fill pulse voltage Vp and test period Tw, change the pulse width Tp, observe whether the transient capacitance signal converges under different pulse widths, and determine the optimal pulse width Tp when there is no noise signal.

5. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 4, characterized in that: Based on the pulse cycle width and different test temperatures, the silicon-based LD-MOS tube device is excited by voltage pulses to obtain a deep energy level transient spectrum signal diagram, specifically: For different wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the following tests are performed respectively: After the temperature drops to the set lowest point, it starts to increase the temperature according to the set step length; At each test temperature point, a voltage pulse is applied to the device under test, and the transient capacitance signal at each sampling temperature point is recorded; The transient capacitance signal is subjected to Fourier transform, and the time domain signal is converted into a frequency domain signal, and the relationship between the Fourier coefficient of capacitance change at different frequencies and temperature is obtained, that is, the deep energy level transient spectrum signal diagram, in which each coefficient corresponds to a time constant.

6. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 5, characterized in that: Based on the deep energy level transient spectrum signal diagram, the signal peak is fitted at selected points to obtain the Arrhenius curve, which is specifically: For the two wiring tests of gate-source capacitance Cgs and gate-drain capacitance Cgd, the specific methods include: By fitting the deep energy level transient spectrum signal graph under different time constants, the Arrhenius diagram related to time constant and temperature is obtained, and the ordinate is ln(τ·v th ·N V,C ), the abscissa is 1000 / T, and the energy level and capture cross section of the defect are obtained based on the Arrhenius diagram fitting, specifically: Where τ is the time constant, v th is the emission rate of hot electrons or holes, N V,C is the effective density of states in the valence band or conduction band, E a is the defect activation energy, k is the Boltzmann constant, T is the Kelvin temperature, γ is the entropy factor, and σ is the capture cross-sectional area.

7. The method for detecting internal defects of a silicon-based LD-MOS transistor device according to claim 6, characterized in that: The defect information existing in the detected device is obtained according to the Arrhenius curve, and the defect type currently measured is obtained, specifically: based on the positive peak and negative peak of the deep energy level transient spectrum signal diagram under different time constants, wherein the positive peak represents the majority carrier and the negative peak represents the minority carrier; combined with the MOS structure doping type tested by the two wiring tests of the gate-source capacitance Cgs and the gate-drain capacitance Cgd, when the doping type is p-type, the majority carrier is a hole and the minority carrier is an electron; when the doping type is n-type, the majority carrier is an electron and the minority carrier is a hole, thereby judging that the defect type currently measured is an electron trap (E i , i = 1, 2, 3 ...), or a hole trap (H i , i=1, 2, 3…); for n-channel LD-MOS tube devices, Cgs is p-type doped and Cgd is n-type doped.

8. A silicon-based LD-MOS tube device internal defect detection system, characterized in that: include: An acquisition module, wherein the acquisition module applies an external voltage to the silicon-based LD-MOS tube device to acquire a CV curve of the silicon-based LD-MOS tube device; An analysis module, which analyzes the voltage range corresponding to the space charge region of the semiconductor device based on the CV curve of the silicon-based LD-MOS tube device, and determines the reverse bias voltage Vr and the fill pulse voltage Vp; A determination module, wherein the determination module determines a test period Tw and a pulse width Tp based on a current temperature, a reverse bias voltage Vr and a fill pulse voltage Vp in a constant temperature mode; A voltage pulse excitation module, which performs voltage pulse excitation on silicon-based LD-MOS tube devices based on pulse cycle width and different test temperatures to obtain a deep energy level transient spectrum signal diagram; A fitting module, based on the deep energy level transient spectrum signal diagram, performs point fitting on the signal peak to obtain an Arrhenius curve, obtains defect information existing in the detected device according to the Arrhenius curve, and obtains the currently measured defect type.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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