High-heat dissipation chip aging test device

Abstract

The invention provides an aging test device for a high-heat dissipation chip, and the device comprises a metal pedestal which is a copper pedestal; the graphene heat dissipation layer is arranged on the top surface of the metal base, and the graphene heat dissipation layer is provided with a heat dissipation fin array; the number of the to-be-detected chips is plural, and the plurality of to-be-detected chips are adsorbed on the bottom surface of the metal base; an air passage is arranged inside the metal base, the air passage is communicated with a plurality of adsorption ports arranged on the bottom surface of the metal base, the plurality of adsorption ports are arranged in an array shape, and a chip to be detected is adsorbed in each of the plurality of adsorption ports; a temperature sensor probe is arranged in each adsorption port, and the temperature sensor probes are in contact with the correspondingly adsorbed chips to be detected so as to obtain the real-time temperature of the chips to be detected. The aging test device is high in heat dissipation efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of chip testing, and in particular relates to a high heat dissipation chip aging test device. Background Art

[0002] The process of chip testing is to place the packaged chip in various environments to test its electrical characteristics, such as power consumption, operating speed, voltage resistance, etc. After the test, the chip is divided into different grades according to its electrical characteristics. Special testing is to take out some chips from similar parameter specifications and varieties according to the technical parameters of the customer's special needs, and do targeted special tests to see if they can meet the customer's special needs, so as to decide whether to design a special chip for the customer. Products that pass the general test are labeled with specifications, models and factory date and packaged before they can be shipped. Chips that fail the test are defined as downgraded products or waste products depending on the parameters they meet.

[0003] The existing chip aging test device is simply connected to the heat sink through the chip, which leads to unstable connection, poor heat dissipation effect, and low detection efficiency because a single chip is tested each time. Therefore, it is urgent to provide a high heat dissipation chip aging test device. Summary of the invention

[0004] In view of the technical problems that the chip aging test device in the prior art is simply connected to the heat sink through the chip, resulting in unstable connection, poor heat dissipation effect, and low detection efficiency when a single chip is tested each time, a high heat dissipation chip aging test device is now provided to solve at least one of the above-mentioned technical problems.

[0005] In a preferred embodiment of the present invention, a high heat dissipation chip aging test device is provided, and the chip aging test device comprises:

[0006] A metal base, wherein the metal base is a copper base;

[0007] A graphene heat dissipation layer, wherein the graphene heat dissipation layer is disposed on the top surface of the metal base, and the graphene heat dissipation layer has a heat dissipation fin array;

[0008] The chip to be detected is a plurality of chips to be detected, and the plurality of chips to be detected are adsorbed on the bottom surface of the metal base; wherein,

[0009] An air channel is provided inside the metal base, and the air channel is connected to a plurality of adsorption ports provided on the bottom surface of the metal base, the plurality of adsorption ports are arranged in an array, and each of the plurality of adsorption ports is respectively adsorbed with a chip to be detected;

[0010] A temperature sensor probe is disposed inside each of the plurality of adsorption ports, and the temperature sensor probe contacts the corresponding adsorbed chip to be detected to obtain the real-time temperature of the chip to be detected.

[0011] Preferably, the temperature sensor probes are all connected to a signal processing device.

[0012] Preferably, the airway is connected to a vacuum micropump.

[0013] Preferably, the adsorption port has a diameter of 120 microns to 180 microns.

[0014] Compared with the prior art, the present invention can bring at least one of the following beneficial effects:

[0015] 1. A high heat dissipation chip aging test device of the present application is conducive to efficient heat dissipation of the chip during the aging test by setting a high thermal conductivity graphene heat dissipation layer on the top surface of the metal base. The design of the graphene heat dissipation layer with a heat dissipation fin array can further enhance the heat dissipation effect;

[0016] 2. A high heat dissipation chip aging test device of the present application is provided with an air duct inside a metal base, wherein the air duct is connected to a plurality of adsorption ports provided on the bottom surface of the metal base, the plurality of adsorption ports are arranged in an array, and each of the plurality of adsorption ports is respectively adsorbed with a chip to be tested, thereby realizing simultaneous fixation and testing of multiple chips and improving testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and their implementation methods.

[0018] Figure 1 A high heat dissipation chip aging test device in one embodiment of the present invention. DETAILED DESCRIPTION

[0019] Various aspects of the present invention are described in further detail below.

[0020] Unless otherwise defined or indicated, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein can be applied to the method of the present invention.

[0021] Unless otherwise clearly specified and limited, the "or" mentioned in the present invention includes the relationship of "and". The "and" is equivalent to the Boolean logic operator "AND", the "or" is equivalent to the Boolean logic operator "OR", and "AND" is a subset of "OR".

[0022] It is to be understood that although the terms "first", "second", etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element may be referred to as the second element without departing from the teachings of the present invention.

[0023] In the present invention, the terms "consisting mainly of" and "consisting of" are included in the terms "containing", "including" or "comprising".

[0024] Unless otherwise clearly specified and limited, the terms "connected", "connected" and "connection" in the present invention should be understood in a broad sense, for example, it can be a fixed connection, or it can be connected through an intermediary medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0025] For example, if an element (or component) is referred to as being on, coupled to, or connected to another element, the element may be directly formed on, coupled to, or connected to the other element, or there may be one or more intervening elements between them. In contrast, if the expressions "directly on," "directly coupled to," and "directly connected to" are used herein, then no intervening elements are indicated. Other words used to describe the relationship between elements should be similarly interpreted, such as "between" and "directly between," "attached" and "directly attached," "adjacent" and "directly adjacent," and the like.

[0026] It should also be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The words "inner" and "outer" used refer to directions toward or away from the geometric center of a particular component, respectively. It can be understood that these terms are used here to describe the relationship of one element, layer or region relative to another element, layer or region as shown in the drawings. In addition to the orientations described in the drawings, these terms should also include other orientations of the device.

[0027] Other aspects of the present invention will be apparent to those skilled in the art in view of the disclosure herein.

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0029] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated. For example, the thickness of the components in the drawings may be exaggerated for the sake of clarity.

[0030] Example

[0031] As attached Figure 1 As shown, the present invention realizes a high heat dissipation chip aging test device to solve at least one of the above-mentioned technical problems.

[0032] In a preferred embodiment of the present invention, a high heat dissipation chip aging test device is provided, and the chip aging test device comprises:

[0033] A metal base 1, wherein the metal base 1 is a copper base;

[0034] A graphene heat dissipation layer 2, wherein the graphene heat dissipation layer 2 is disposed on the top surface of the metal base 1, and the graphene heat dissipation layer 2 is provided with a heat dissipation fin array 3;

[0035] The chip to be detected 8 is a plurality of chips to be detected, and the plurality of chips to be detected 8 are adsorbed on the bottom surface of the metal base 1; wherein,

[0036] An air channel 4 is provided inside the metal base 1, and the air channel 4 is connected to a plurality of adsorption ports provided on the bottom surface of the metal base 1, and the plurality of adsorption ports are arranged in an array, and each of the plurality of adsorption ports is respectively adsorbed with a chip to be detected 8;

[0037] A temperature sensor probe 5 is disposed inside each of the plurality of adsorption ports. The temperature sensor probe 5 contacts the corresponding adsorbed chip 8 to be detected to obtain the real-time temperature of the chip to be detected.

[0038] Preferably, the temperature sensor probes 5 are all connected to a signal processing device 6 .

[0039] Preferably, the air channel 4 is connected to the vacuum micro pump 7 .

[0040] Preferably, the adsorption port has a diameter of 120 microns to 180 microns.

[0041] A high heat dissipation chip aging test device of the present application is beneficial to the efficient heat dissipation of the chip in the aging test by setting a high thermal conductivity graphene heat dissipation layer on the top surface of the metal base, and the design of the graphene heat dissipation layer with a heat dissipation fin array can further enhance the heat dissipation effect; by setting an air channel inside the metal base, the air channel is connected to a plurality of adsorption ports set on the bottom surface of the metal base, and the plurality of adsorption ports are arranged in an array, and each of the plurality of adsorption ports is respectively adsorbed with a chip to be tested, it can achieve simultaneous fixation and testing of multiple chips, thereby improving the detection efficiency.

[0042] Based on this application, it should be understood by those skilled in the art that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0043] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

[0044] All documents mentioned in the present invention are cited as references in this application, just as each document is cited as reference separately. In addition, it should be understood that after reading the above content of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the claims attached to this application.

Claims

1. A high heat dissipation chip aging test device, characterized in that: The chip aging test device comprises: A metal base, wherein the metal base is a copper base; A graphene heat dissipation layer, wherein the graphene heat dissipation layer is disposed on the top surface of the metal base, and the graphene heat dissipation layer has a heat dissipation fin array; The chip to be detected is a plurality of chips to be detected, and the plurality of chips to be detected are adsorbed on the bottom surface of the metal base; wherein, An air channel is provided inside the metal base, and the air channel is connected to a plurality of adsorption ports provided on the bottom surface of the metal base, the plurality of adsorption ports are arranged in an array, and each of the plurality of adsorption ports is respectively adsorbed with a chip to be detected; A temperature sensor probe is disposed inside each of the plurality of adsorption ports, and the temperature sensor probe contacts the corresponding adsorbed chip to be detected to obtain the real-time temperature of the chip to be detected. Preferably, the temperature sensor probes are all connected to a signal processing device.

2. A high heat dissipation chip aging test device as claimed in claim 1, characterized in that: The temperature sensor probes are all connected to a signal processing device.

3. A high heat dissipation chip aging test device as claimed in claim 2, characterized in that: The airway is connected to a vacuum micro pump.

4. A high heat dissipation chip aging test device as claimed in claim 1, characterized in that: The adsorption port has a diameter of 120 microns to 180 microns.

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