Method for verifying cache validity of master device and computing device

Abstract

The invention provides a method for verifying cache validity and a computing device, the method is applied to verification of cache validity of a master device during data transmission between the master device and a slave device of a high-speed serial bus, and the method comprises the following steps: the master device opens a first cache to map a first continuous memory allocation area; the slave device maps a second cache of a second continuous memory allocation area; the master device writes first data into the mapped first continuous memory allocation area; the master device writes first data into a second continuous memory allocation area of the slave device in a first mode; the master device informs the slave device of the data write-in message and the first data in a second mode; data received from the device is used as second data; the slave device reads data in the second continuous memory allocation area as third data; and comparing the second data with the third data, and if different, verifying that the cache of the master device is valid. According to the technical scheme, the cache validity can be verified, the hardware use cost is reduced, and the data transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a method for verifying the validity of a master device cache and a computing device. Background Art

[0002] Cache is a high-speed memory. The working principle of cache is based on the principle of program locality, that is, the program will repeatedly access certain data or instructions during execution, so the cache will pre-load these hot data or instructions into the cache. When the processor needs to access these data or instructions, it can directly obtain them from the cache, which greatly speeds up the access speed. The setting of cache is one of the important factors for all modern computer systems to achieve high performance. As a primary memory, if the cache can effectively cache commonly used data, then the cache is effective, so it is extremely important to verify the effectiveness of the cache.

[0003] Therefore, a technical solution is needed that can verify the cache effectiveness, reduce the hardware usage cost, and improve the data transmission efficiency. Summary of the invention

[0004] The present invention aims to provide a method and a computing device for verifying the validity of a master device cache, which can verify the validity of the cache, reduce the cost of hardware use, and improve data transmission efficiency.

[0005] According to one aspect of the present invention, a method for verifying the validity of a master device cache is provided, the method being applied to verifying the validity of a master device cache during data transmission between a master device and a slave device of a high-speed serial bus, the method comprising:

[0006] The master device automatically loads the driver of the slave device when it is powered on, and the slave device automatically loads the mailbox driver when it is powered on;

[0007] The master device opens a first cache mapping to a first continuous memory allocation area;

[0008] The slave device maps a second cache of the second continuous memory allocation area;

[0009] The master device writes first data to the mapped first continuous memory allocation area, and the first data is actually written into the first cache;

[0010] The master device writes the first data to the second continuous memory allocation area of ​​the slave device in a first manner;

[0011] The master device writes data into a message and notifies the slave device of the first data in a second manner;

[0012] The slave device receives the first data sent by the master device in a second manner as second data;

[0013] The slave device reads the first data on the second continuous memory allocation area as the third data;

[0014] The second data and the third data are compared, and if the second data are different from the third data, it is verified that the cache of the master device is valid.

[0015] According to some embodiments, the slave device driver and the mailbox driver run in the kernel layer of the master device and the slave device respectively;

[0016] The application layer of the master device executes opening a first cache to map a first continuous memory allocation area, writing first data to the mapped first continuous memory allocation area, writing the first data to a second continuous memory allocation area of ​​the slave device in a first manner, and notifying the slave device of a data write message and the first data in a second manner;

[0017] The application layer of the slave device executes a second cache mapping a second continuous memory allocation area, receives the first data sent by the master device in a second manner as second data, reads the first data on the second continuous memory allocation area as third data, and compares the second data and the third data.

[0018] According to some embodiments, the first mode is high-speed serial bus direct access memory transmission, and the second mode is mailbox channel message transmission.

[0019] According to some embodiments, the work performed by the driver of the slave device includes:

[0020] The master device cache mapping memory interface is encapsulated in a control function, and the control function has an interface command of a corresponding type.

[0021] According to some embodiments, the work performed by the driver of the slave device further includes:

[0022] The master device cache mapping memory interface is encapsulated in the control function, and the control function has a corresponding type of interface command.

[0023] According to some embodiments, the work performed by the driver of the slave device further includes:

[0024] A high-speed serial bus direct access memory transmission interface is encapsulated in the control function, the high-speed serial bus direct access memory transmission interface is used for the host device to transmit data through direct memory access, and the control function has a corresponding type of interface command.

[0025] According to some embodiments, the work performed by the driver of the slave device further includes:

[0026] A sending mailbox message interface is encapsulated in the control function, and the sending mailbox message interface is used for the master device to send messages and data through a mailbox. The control function has an interface command of a corresponding type.

[0027] According to some embodiments, the work performed by the mailbox driver of the slave device includes:

[0028] The interface of mapping the second continuous memory allocation area from the device cache is encapsulated in a control function, and the control function has an interface command of a corresponding type.

[0029] According to some embodiments, the work performed by the mailbox driver of the slave device further includes:

[0030] The receiving and forwarding mailbox message interface is encapsulated in the control function, and the receiving and forwarding mailbox message interface is used for the slave device to receive the message sent by the master device mailbox, and the control function has an interface command of a corresponding type.

[0031] According to another aspect of the present invention, there is provided a computing device, comprising:

[0032] Processor; and

[0033] A memory stores a computer program, and when the computer program is executed by the processor, the method described in any one of the above items is implemented.

[0034] According to an embodiment of the present invention, the master device calls the master device cache mapping memory instruction, writes data to the mapped first continuous memory allocation area, and writes the data to the second continuous memory allocation area of ​​the slave device at the same time, and the master device notifies the slave device of the message of data writing and the content of the data; the slave device calls the slave device cache mapping memory instruction, receives the message of data writing and the content of the data, reads the data on the second continuous memory allocation area of ​​the slave device, compares the received data with the data on the second continuous memory allocation area, and if the two data are different, verifies that the cache of the master device is effective. Through the present invention, it is possible to verify the effectiveness of the cache, reduce the cost of hardware use, and improve the efficiency of data transmission, without the need to use simulation instruments to add cache test methods.

[0035] According to some embodiments, after the master device turns on the cache and the mapping of the continuous memory allocation area, it writes data to the mapped first continuous memory allocation area. The actual data is written into the cache, while the data written into the continuous memory allocation area of ​​the slave device is the actual write data. The data content sent by the master device to the slave device is the data in the system memory, not the written data. By comparing the two data, it can be effectively verified that the written data exists in the cache and the cache is effective.

[0036] According to some embodiments, the present invention simplifies the troubleshooting process. When a system problem occurs, the comparison mechanism of the present invention can more easily determine whether the problem lies in the cache or other parts, thereby speeding up the problem-solving process.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0039] Figure 1 A flow chart of a method for verifying the validity of a master device cache according to an example embodiment is shown.

[0040] Figure 2 A schematic diagram of a master and slave device according to an example embodiment is shown.

[0041] Figure 3 A schematic diagram of the operation of master and slave devices according to an example embodiment is shown.

[0042] Figure 4 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0044] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0045] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0046] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0047] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0048] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0049] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0050] In the existing technology, some hardware can directly access the data in the cache. The verification of the effectiveness of the cache generally requires additional PCIe (PCIe high-speed peripheral interface device) devices to build a test environment, which increases the hardware investment cost. The introduction of more hardware components increases the complexity of the system, easily introduces new failure points, and makes problem diagnosis more difficult. There may be compatibility issues between different PCIe devices, especially when they come from different manufacturers or use different standards. Integrating these devices into existing systems may also face challenges.

[0051] To this end, the present invention proposes a method for verifying the validity of a master device cache, which can verify the cache validity, reduce hardware usage costs, and improve data transmission efficiency.

[0052] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0053] Figure 1 A flow chart of a method for verifying the validity of a master device cache according to an example embodiment is shown.

[0054] See also Figure 1 The method of the present invention is a technology to test and verify whether the cache is effective through continuous memory allocation area (CMA memory), mailbox (Mailbox) and high-speed serial bus direct access memory (PCIe DMA) transmission. The working content and timing of the master and slave devices can be seen in Figure 3 .

[0055] In S101, the master device automatically loads the driver of the slave device when the master device is powered on.

[0056] According to some embodiments, the slave device driver encapsulates the master device's cache mapping memory interface in a control function, and the control function has a corresponding type of interface command; encapsulates the master device's cache mapping memory interface in the control function, and the control function has a corresponding type of interface command; encapsulates a high-speed serial bus direct access memory transmission interface in the control function, and the high-speed serial bus direct access memory transmission interface is used by the master device to transmit data through direct memory access, and the control function has a corresponding type of interface command; encapsulates a send mailbox message interface in the control function, and the send mailbox message interface is used by the master device to send messages and data through a mailbox, and the control function has a corresponding type of interface command.

[0057] The master device cache mapping memory opening instruction is used to control the master device to open the master device cache and open the mapping of the first continuous memory allocation area. The master device cache mapping memory closing instruction is used to control the master device to close the master device cache and close the mapping of the first continuous memory allocation area. The high-speed serial bus direct access memory transmission instruction is used for the terminal to transmit data of the direct memory access storage. The send mailbox message instruction is used for the terminal to send a message through the master device mailbox.

[0058] Most functions of the driver are encapsulated in the control function (ioctl function), which is a member function of the struct fileoperations structure. In order to distinguish each function, an instruction code type is defined for each function. In this way, when the application calls ioctl, different types can be passed in to achieve different functions.

[0059] The interface for opening cache mapping of the CMA memory of the host device (host device) is encapsulated in ioctl, and the ioctl interface command type is 100, that is, the host device opens cache mapping memory instruction is host_type100; the interface for closing cache mapping of the CMA memory of the host device is encapsulated in ioctl, and the ioctl interface command type is 101, that is, the host device closes cache mapping memory instruction is host_type101; the PCIe DMA transmission interface is encapsulated in ioctl, and the ioctl interface command type is 102, that is, the high-speed serial bus directly accesses memory transmission instruction is host_type102; the high-speed serial bus (PCIe) Mailbox message sending interface is encapsulated in ioctl, and the ioctl interface command type is 103, that is, the mailbox message sending instruction is host_type103.

[0060] In S103, the master device opens a first cache mapping a first continuous memory allocation area.

[0061] According to some embodiments, the application program of the master device is located at the application layer of the master device; the slave device driver of the master device and the first continuous memory allocation area are located at the kernel layer of the master device.

[0062] The master device application interacts with the slave device application. When the master device application is executed, it first opens the PCIe ep driver device file and obtains the encapsulation instruction in the ioctl function.

[0063] Call the ioctl interface command host_type100 to enable the cache of the master device and enable the mapping of the CMA memory of the master device.

[0064] At S105, the slave device maps a second cache of the second continuous memory allocation area.

[0065] When the slave device is powered on, the application program of the slave device automatically loads the mailbox driver. The application program of the slave device is located in the application layer of the slave device, and the mailbox driver of the slave device and the second continuous memory allocation area are located in the kernel layer of the slave device.

[0066] The slave device mailbox driver encapsulates the slave device cache mapping interface of the second continuous memory allocation area in a control function, and the control function has a corresponding type of interface command; encapsulates the receive and forward mailbox message interface in the control function, and the receive and forward mailbox message interface is used for the slave device to receive messages sent by the master device mailbox, and the control function has a corresponding type of interface command.

[0067] The slave device close cache mapping memory instruction is used to control the slave device to close the slave device cache and close the mapping of the second continuous memory allocation area, and the receive and forward mailbox message instruction is used for the slave device to receive the message sent by the master device mailbox.

[0068] The interface of the CMA memory cache mapping of the slave device (slave device) is encapsulated in ioctl, and the ioctl interface command type is 100, that is, the slave device cache mapping memory instruction is slave_type100; the instruction to receive the mailbox message of the master device and send it to the application layer of the slave device is encapsulated in ioctl, and the ioctl interface command type is 101, that is, the instruction to receive and forward the mailbox message is slave_type101.

[0069] Call the ioctl interface command slave_type100 to close the cache of the slave device and the mapping of the slave device CMA memory.

[0070] In S107, the master device writes first data to the mapped first continuous memory allocation area, and the first data is actually written into the first cache.

[0071] After the master device enables cache and CMA memory mapping, the data written to the CMA memory is actually written to the cache.

[0072] In S109, the master device writes the first data to the second continuous memory allocation area of ​​the slave device in a first manner.

[0073] The first method is high-speed serial bus direct access memory transmission (PCIe DMA transmission).

[0074] According to some embodiments, PCIe DMA (Direct Memory Access) transfer refers to the process of directly transferring data between a device and system memory via a PCIe (Peripheral Component Interconnect Express) bus. DMA allows external devices (such as graphics cards, network adapters, or other I / O devices) to directly read or write to memory without the need for central processing unit (CPU) intervention. This direct access can significantly improve data transfer efficiency, reduce CPU burden, and reduce overall system latency.

[0075] In PCIe DMA operation, the device (Endpoint, EP) can directly request access to the memory and complete the data read or write operation through the DMA controller. This process is very useful for application scenarios such as packet processing, image rendering, and other applications that require large amounts of data transfer.

[0076] For example, in a typical PCIe network adapter, when a data packet is received, the adapter can write the data packet directly to the system's memory through the DMA mechanism without the CPU having to copy the data from it. Similarly, when sending data, the adapter can also read the data directly from the memory and send it out.

[0077] It should be noted that in order to ensure data consistency and security, the system usually adopts certain protection measures when implementing DMA operations, such as using IOMMU (Input-Output Memory Management Unit) to manage the device's access rights to memory and provide address translation and protection functions. This can prevent data corruption or security vulnerabilities caused by DMA devices due to errors or malicious behavior.

[0078] In S111, the master device notifies the slave device of the data write message and the first data in a second manner.

[0079] The second method is mailbox channel message transmission.

[0080] According to some embodiments, Mailbox transmission is a mechanism commonly used for communication between different processors or devices. Under this mechanism, two or more entities (such as a CPU and an I / O device, or two different processor cores) share a set of registers or memory areas, which are called "mailboxes". These mailboxes can be used to store messages or status information so that the entities can notify each other or transmit simple control information.

[0081] In PCIe devices, the Mailbox mechanism can be used to achieve synchronization and communication between the master device and the device. In this way, the master device can send instructions or data to the device, and the device can report its status or results to the master device after completing certain tasks.

[0082] For example, in a GPU (graphics processing unit) computing environment, the CPU may send a signal to the GPU through the Mailbox mechanism to start executing a kernel, or the GPU may inform the CPU of the completion status of the calculation through the Mailbox after completing the calculation. This communication method helps to simplify the programming model and allows different types of processors to work together.

[0083] In short, Mailbox transmission provides a lightweight and efficient communication method, which is particularly suitable for occasions that require frequent small data volume interactions. In this way, system overhead can be reduced and the response speed and efficiency of the entire system can be improved.

[0084] In S113, the slave device receives the first data sent by the master device in a second manner as second data.

[0085] The mailbox of the slave device waits for the message sent from the mailbox of the master device. The message includes the data write message and the specific content of the data. Because the cache of the master device is turned on, the written data is not written to the CMA memory of the master device, so the data content sent is the data on the DDR memory of the master device.

[0086] In S115, the slave device reads the first data on the second continuous memory allocation area as third data.

[0087] In S117, the second data and the third data are compared, and if the second data is different from the third data, it is verified that the cache of the master device is valid.

[0088] The data content received from the device mailbox is the data on the master device memory DDR, and the data in the slave device CMA memory is the actual written data. The two data are compared. If the two data are different, it is verified that the data is written into the master device cache and the master device cache is effective.

[0089] Figure 2 A schematic diagram of a master and slave device according to an example embodiment is shown.

[0090] See also Figure 2 , the master device (PCIe host device) and the slave device (PCIe slave device) are connected through the PCIe interface.

[0091] According to some embodiments, the application of the master device is located in the application layer of the master device; the slave device driver of the master device and the first continuous memory allocation area are located in the kernel layer of the master device. The application of the slave device is located in the application layer of the slave device, and the mailbox driver of the slave device and the second continuous memory allocation area are located in the kernel layer of the slave device.

[0092] The data transmission of the method of the present invention is through the PCIe interface and the Mailbox, and the validity of the Cache can be verified at the software level, which reduces the use of hardware and saves the cost of hardware use.

[0093] Figure 4 A block diagram of a computing device is shown according to an exemplary embodiment.

[0094] like Figure 4As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0095] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0096] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 can read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0097] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0098] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0099] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0100] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0101] An embodiment of the present invention further provides a computer program product, which includes a computer program. The computer program is operable to enable a computer to execute part or all of the steps of any one of the methods described in the above method embodiments.

[0102] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0103] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0104] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0105] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0106] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0108] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A method for verifying the validity of a master device cache, the method being applied to verifying the validity of a master device cache during data transmission between a master device and a slave device of a high-speed serial bus, the method comprising: The master device automatically loads the driver of the slave device when it is powered on, and the slave device automatically loads the mailbox driver when it is powered on; The master device opens a first cache mapping to a first continuous memory allocation area; The slave device maps a second cache of the second continuous memory allocation area; The master device writes first data to the mapped first continuous memory allocation area, and the first data is actually written into the first cache; The master device writes the first data to the second continuous memory allocation area of ​​the slave device in a first manner; The master device writes data into a message and notifies the slave device of the first data in a second manner; The slave device receives the first data sent by the master device in a second manner as second data; The slave device reads the first data on the second continuous memory allocation area as the third data; The second data and the third data are compared, and if the second data are different from the third data, it is verified that the cache of the master device is valid.

2. The method according to claim 1, characterized in that The driver of the slave device and the mailbox driver run in the kernel layer of the master device and the slave device respectively; The application layer of the master device executes opening a first cache to map a first continuous memory allocation area, writing first data to the mapped first continuous memory allocation area, writing the first data to a second continuous memory allocation area of ​​the slave device in a first manner, and notifying the slave device of a data write message and the first data in a second manner; The application layer of the slave device executes a second cache mapping a second continuous memory allocation area, receives the first data sent by the master device in a second manner as second data, reads the first data on the second continuous memory allocation area as third data, and compares the second data and the third data.

3. The method according to claim 1, characterized in that The first mode is high-speed serial bus direct access memory transmission, and the second mode is mailbox channel message transmission.

4. The method according to claim 3, characterized in that The work performed by the driver of the slave device includes: The master device cache mapping memory interface is encapsulated in a control function, and the control function has an interface command of a corresponding type.

5. The method according to claim 3, characterized in that: The work performed by the driver of the slave device also includes: The master device cache mapping memory interface is encapsulated in the control function, and the control function has a corresponding type of interface command.

6. The method according to claim 3, characterized in that The work performed by the driver of the slave device also includes: A high-speed serial bus direct access memory transmission interface is encapsulated in the control function, the high-speed serial bus direct access memory transmission interface is used for the host device to transmit data through direct memory access, and the control function has a corresponding type of interface command.

7. The method according to claim 3, characterized in that The work performed by the driver of the slave device also includes: A sending mailbox message interface is encapsulated in the control function, and the sending mailbox message interface is used for the master device to send messages and data through a mailbox. The control function has an interface command of a corresponding type.

8. The method according to claim 3, characterized in that The work performed by the mailbox driver of the slave device includes: The interface of mapping the second continuous memory allocation area from the device cache is encapsulated in a control function, and the control function has an interface command of a corresponding type.

9. The method according to claim 8, characterized in that The work performed by the mailbox driver of the slave device also includes: The receiving and forwarding mailbox message interface is encapsulated in the control function, and the receiving and forwarding mailbox message interface is used for the slave device to receive the message sent by the master device mailbox, and the control function has an interface command of a corresponding type.

10. A computing device, characterized in that include: processor; as well as A memory storing a computer program, wherein when the computer program is executed by the processor, the method according to any one of claims 1 to 9 is implemented.

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