Defect identification method and device for epitaxial silicon wafer and manufacturing method

Abstract

The invention provides a defect identification method and device for an epitaxial silicon wafer and a manufacturing method, and belongs to the technical field of semiconductor manufacturing. The defect identification method of the epitaxial silicon wafer comprises the following steps: testing a Nano value of a substrate silicon wafer; putting the substrate silicon wafer into epitaxial growth equipment for epitaxial growth to obtain an epitaxial silicon wafer; dividing the surface of the epitaxial silicon wafer into a plurality of areas, and obtaining a Nano value of each area; determining the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region; if the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold value and the Nano change value of the existing region is greater than a second threshold value, matching the defect position of the epitaxial silicon wafer with the position of a support rod of epitaxial growth equipment; and if so, judging that the epitaxial silicon wafer has the pin print Pin Nano defect. According to the invention, the generation of the Pin Nano defect can be detected in time in the epitaxial growth process, and the waste of production resources is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a defect identification method and device for an epitaxial silicon wafer, and a manufacturing method. Background Art

[0002] Epitaxial growth refers to the process of growing a single crystal thin film (the crystal direction is consistent with the substrate crystal direction) on a single crystal silicon substrate through epitaxy technology. The entire production process of epitaxial wafers includes five major processes: crystal growth (pulling silicon crystal rods from polysilicon materials) → molding (slicing and grinding) → polishing (double-sided polishing) → cleaning (removing surface particles, metal ions and organic matter) → epitaxy (vapor deposition). Epitaxy is the last important process, which can improve the crystal properties, native defects, resistivity and flatness of the polished wafer.

[0003] like Figure 1 As shown, the epitaxial growth equipment generally includes: an upper quartz bell jar 1, a lower quartz bell jar 2, an air inlet, an exhaust port, a halogen lamp 3, and a mounting component 4. In the reaction chamber enclosed by the upper quartz bell jar 1 and the lower quartz bell jar 2, a base 6 for placing a silicon wafer, a base support rod 7, and a silicon wafer support rod are provided. After the silicon wafer 8 is input into the reaction chamber and placed on the base 6 in the reaction chamber, the upper heating module arranged on the upper side of the base 6 and the lower heating module arranged on the lower side of the base 6 heat the silicon wafer 8, and the raw material gas is supplied 5 to the surface of the silicon wafer 8, thereby performing vapor phase epitaxial growth, and the epitaxial wafer obtained by vapor phase epitaxial growth is output outside the reaction chamber. During the growth process, the base support rod 7 plays the role of fixing the base 6 and driving the base 6 to rotate, so that the epitaxial growth can be carried out evenly on the base 6.

[0004] During the epitaxial growth process, pin nano defects may occur on silicon wafers due to various factors. If they are not discovered in time, not only will a large number of products be scrapped, but the production rhythm of the products will also be affected. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a defect identification method and device for epitaxial silicon wafers, and a manufacturing method, which can timely detect the generation of Pin Nano defects during the epitaxial growth process and reduce the waste of production resources.

[0006] In order to achieve the above object, the technical solution adopted in the embodiment of the present invention is:

[0007] A defect identification method for an epitaxial silicon wafer, comprising:

[0008] Test the Nano value of the substrate silicon wafer;

[0009] Placing the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer;

[0010] Dividing the surface of the epitaxial silicon wafer into a plurality of regions, and obtaining the Nano value of each region;

[0011] Determine the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region;

[0012] If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing region is greater than a second threshold, matching the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth device;

[0013] If the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer.

[0014] In some embodiments, the method further comprises any of the following:

[0015] If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano change values ​​of all regions are not greater than a second threshold, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect;

[0016] If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existence area is greater than a second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect.

[0017] In some embodiments, the Nano area percentage of the epitaxial silicon wafer is A / N, wherein N is the number of regions into which the epitaxial silicon wafer is divided, and A is the number of regions having a Nano value greater than a third threshold;

[0018] The Nano change value of each area is the difference between the Nano value of the epitaxial silicon wafer in that area and the Nano value of the substrate silicon wafer in that area.

[0019] In some embodiments, if the defect position of the epitaxial silicon wafer matches the position of the support rod, determining that a Pin Nano defect occurs in the epitaxial silicon wafer includes:

[0020] If the angle corresponding to the defect position of the epitaxial silicon wafer is 0°, 120° or 240°, it is determined that a Pin Nano defect occurs in the epitaxial silicon wafer.

[0021] In some embodiments, after determining that the epitaxial silicon wafer has a Pin Nano defect, the method further includes:

[0022] A shutdown instruction is generated to stop the production state of the epitaxial growth equipment.

[0023] In some embodiments, the first threshold is 95% and the second threshold is 2.

[0024] In some embodiments, the third threshold is 18 nm.

[0025] The embodiment of the present invention further provides a defect identification device for an epitaxial silicon wafer, comprising:

[0026] Test module, used to test the Nano value of the substrate silicon wafer;

[0027] An epitaxial growth module, used for placing the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer;

[0028] An acquisition module, used to divide the surface of the epitaxial silicon wafer into multiple regions and obtain the Nano value of each region;

[0029] A calculation module, used to determine the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region;

[0030] A processing module is used to match the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth equipment if the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing area is greater than a second threshold; if the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer.

[0031] In some embodiments, the processing module is further configured to perform any of the following:

[0032] If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano change values ​​of all regions are not greater than a second threshold, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect;

[0033] If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existence area is greater than a second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect.

[0034] The embodiment of the present invention further provides a method for manufacturing an epitaxial silicon wafer, the method comprising:

[0035] Using an epitaxial growth device to form an epitaxial layer on a surface of a substrate silicon wafer to obtain an epitaxial silicon wafer;

[0036] The defects of the epitaxial silicon wafer are detected according to the above-mentioned defect identification method to determine the defects of the epitaxial silicon wafer.

[0037] The beneficial effects of the present invention are:

[0038] In this embodiment, the Nano values ​​of the substrate silicon wafer and the epitaxial silicon wafer are obtained, and it is determined whether the epitaxial silicon wafer currently being produced has a Pin Nano defect based on the obtained Nano values. This embodiment can efficiently and timely identify Pin Nano defects, and can avoid misjudgment and missed judgment. In this way, when it is determined that a Pin Nano defect occurs in an epitaxial silicon wafer, a shutdown instruction can be generated to stop the subsequent epitaxial production state of the epitaxial growth equipment, without the need for a long lag period in the relevant scheme, thereby avoiding the production of more epitaxial silicon wafers with a risk of Pin Nano defects, thereby reducing the waste of production resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram showing the structure of an existing epitaxial growth device;

[0040] Figure 2 A schematic diagram showing the structure of an epitaxial furnace;

[0041] Figure 3 A schematic diagram showing a flow chart of a defect identification method for an epitaxial silicon wafer according to an embodiment of the present invention;

[0042] Figure 4 A schematic diagram showing how an epitaxial silicon wafer is divided into a plurality of regions according to an embodiment of the present invention;

[0043] Figure 5 It indicates the percentage of Nano area in different size regions of epitaxial silicon wafer;

[0044] Figure 6 Schematic diagram showing suspected Pin Nano defects in epitaxial silicon wafers;

[0045] Figure 7 Schematic diagram showing the presence of Pin Nano defects in epitaxial silicon wafers;

[0046] Figure 8 Schematic diagram showing the presence of non-Pin Nano defects in epitaxial silicon wafers;

[0047] Fig. 9 A schematic diagram showing the position of the support rods of the epitaxial growth equipment on the base;

[0048] Fig.10 A schematic diagram showing the structure of a defect identification device for an epitaxial silicon wafer according to an embodiment of the present invention.

[0049] Reference numerals

[0050] 1Upper quartz bell jar

[0051] 2 Lower quartz bell jar

[0052] 3 Halogen lamps

[0053] 4. Install the components

[0054] 5. Process Gas

[0055] 6 Base

[0056] 7 Base support rod

[0057] 8 Silicon wafer DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0059] Figure 2 The schematic diagram of the structure of the epitaxial furnace shows that during epitaxial growth, the transfer blades in the front-end module ② transfer the silicon wafer from the loading port ① to the load lock unit ③, which is then evacuated and backfilled with nitrogen. The transfer manipulator in the transfer unit ④ transfers the silicon wafer in the load lock unit ③ through the transfer unit ④ into the process reaction chamber ⑤ for epitaxial growth. After the growth is completed, the silicon wafer returns along the original route.

[0060] Currently, when performing defect detection, the nano-topography image of the epitaxial silicon wafer is obtained, and the Pin Nano defects of the epitaxial silicon wafer are identified through the image-viewing card control method. However, the image-viewing card control method is inefficient, time-consuming, and prone to misjudgment and missed judgment problems.

[0061] The present invention provides a defect identification method and device for an epitaxial silicon wafer, and a manufacturing method, which can timely detect the generation of Pin Nano defects during the epitaxial growth process and reduce the waste of production resources.

[0062] The embodiment of the present invention provides a defect identification method for an epitaxial silicon wafer, such as Figure 3 As shown, including:

[0063] Step 101: Testing the Nano value of the substrate silicon wafer;

[0064] Among them, Nano refers to the nanomorphology of the silicon wafer surface, which describes the local shape of the wafer at a spatial wavelength of 0.2-20mm.

[0065] Step 102: placing the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer;

[0066] Step 103: Divide the surface of the epitaxial silicon wafer into a plurality of regions, and obtain the Nano value of each region;

[0067] In this embodiment, Figure 4 As shown, the surface of the epitaxial silicon wafer can be divided into multiple fixed-size regions, for example, the surface of the epitaxial silicon wafer can be divided into multiple 0.5mm*0.5mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 2mm*2mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 5mm*5mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 10mm*10mm regions. A Nano value is tested for each region, and the larger the Nano value, the worse the quality of the epitaxial silicon wafer.

[0068] Step 104: determining the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region;

[0069] In some embodiments, the Nano area percentage of the epitaxial silicon wafer is A / N, wherein N is the number of regions into which the epitaxial silicon wafer is divided, and A is the number of regions whose Nano values ​​are greater than a third threshold; the Nano change value of each region is the difference between the Nano value of the epitaxial silicon wafer in that region and the Nano value of the substrate silicon wafer in that region.

[0070] Figure 5 It represents the Nano area percentage of epitaxial silicon wafer in regions of different sizes, where the ordinate represents the Nano area percentage and the abscissa represents the threshold value, in nm.

[0071] The value of the third threshold is related to the size of the region. In some embodiments, when the size of each region is 10mm*10mm, the value of the third threshold may be 18nm. For example, the surface of the epitaxial silicon wafer is divided into 706 regions of 10mm*10mm, of which 700 regions have a Nano value greater than 18nm, and the Nano area percentage is 700 / 706=99.15%.

[0072] Step 105: if the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing region is greater than a second threshold, matching the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth device;

[0073] If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano variation values ​​of all regions are not greater than a second threshold, it can be determined that no Pin Nano defect occurs in the epitaxial silicon wafer.

[0074] In some embodiments, the first threshold may be 95%, and the second threshold may be 2. Of course, the values ​​of the first threshold and the second threshold are not limited thereto, and may be adjusted according to actual needs.

[0075] For example, if the surface of an epitaxial silicon wafer is divided into multiple 10mm*10mm areas, if there is no area with a Nano change value greater than 2, and the proportion of areas with Nano values ​​greater than 18nm is less than 95%, it means that there is no Pin Nano defect in the epitaxial silicon wafer, and the epitaxial furnace can be produced normally. Figure 6 As shown, although there are white marks suspected to be Pin Nano on the epitaxial silicon wafer (shown in the red frame in the figure), there is no area with a Nano change value greater than 2, and the proportion of areas with Nano values ​​greater than 18nm is less than 95%, indicating that the product quality of the epitaxial silicon wafer is qualified.

[0076] Step 106: If the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer, such as Figure 7 Shown in the red box.

[0077] If the Nano area percentage of the epitaxial silicon wafer is greater than the first threshold and the Nano change value of the existing area is greater than the second threshold, it means that there is a defect on the epitaxial silicon wafer, but it is not necessarily a Pin Nano defect. If the defect position of the epitaxial silicon wafer matches the position of the support rod, it is judged that the epitaxial silicon wafer has a pin-printed Pin Nano defect. For example, if the angle corresponding to the defect position of the epitaxial silicon wafer is 0°, 120° or 240°, it is judged that the epitaxial silicon wafer has a Pin Nano defect. If the Nano area percentage of the epitaxial silicon wafer is greater than the first threshold and the Nano change value of the existing area is greater than the second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a PinNano defect.

[0078] In a specific example, the surface of the epitaxial silicon wafer is divided into multiple 10mm*10mm areas. If there is an area with a Nano change value greater than 2 and the proportion of areas with Nano values ​​greater than 18nm is greater than 95%, it means that the epitaxial silicon wafer has defects, but not necessarily Pin Nano defects; Figure 8 As shown, although there are areas where the Nano change value is greater than 2 and the area with a Nano value greater than 18nm accounts for more than 95%, it is not a Pin Nano defect.

[0079] Fig. 9 The schematic diagram shows the position of the support pin (lift pin) of the epitaxial growth equipment on the base, where the blue dot represents the lift pin. The setting angles of the three lift pins are 0°, 120°, and 240° respectively. The defect position of the epitaxial silicon wafer is matched with the position angles of the three lift pins. If the angle corresponding to the defect position is any one of 0°, 120°, and 240°, it means that the epitaxial silicon wafer has a Pin Nano defect. Figure 7 As shown, the area with a Nano change value greater than 2 and a Nano value greater than 18nm accounts for more than 95%, and the angle corresponding to the defect position is 0°, indicating that a Pin Nano defect occurs in the epitaxial silicon wafer. After determining that the epitaxial silicon wafer has a Pin Nano defect, a shutdown command needs to be generated to stop the production status of the epitaxial growth equipment to prevent more epitaxial silicon wafers with a risk of Pin Nano defects from being produced, resulting in a waste of production resources.

[0080] In this embodiment, the Nano values ​​of the substrate silicon wafer and the epitaxial silicon wafer are obtained, and it is determined whether the epitaxial silicon wafer currently being produced has a Pin Nano defect based on the obtained Nano values. This embodiment can efficiently and timely identify Pin Nano defects, and can avoid misjudgment and missed judgment. In this way, when it is determined that a Pin Nano defect occurs in an epitaxial silicon wafer, a shutdown instruction can be generated to stop the subsequent epitaxial production state of the epitaxial growth equipment, without the need for a long lag period in the relevant scheme, thereby avoiding the production of more epitaxial silicon wafers with a risk of Pin Nano defects, thereby reducing the waste of production resources.

[0081] The embodiment of the present invention also provides a defect identification device for epitaxial silicon wafers, such as Fig.10 As shown, including:

[0082] The testing module 21 is used to test the Nano value of the substrate silicon wafer;

[0083] The epitaxial growth module 22 is used to place the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer;

[0084] An acquisition module 23, used to divide the surface of the epitaxial silicon wafer into multiple regions and obtain the Nano value of each region;

[0085] In this embodiment, Figure 4As shown, the surface of the epitaxial silicon wafer can be divided into multiple fixed-size regions, for example, the surface of the epitaxial silicon wafer can be divided into multiple 0.5mm*0.5mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 2mm*2mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 5mm*5mm regions, or the surface of the epitaxial silicon wafer can be divided into multiple 10mm*10mm regions. A Nano value is tested for each region, and the larger the Nano value, the worse the quality of the epitaxial silicon wafer.

[0086] A calculation module 24, used to determine the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region;

[0087] In some embodiments, the Nano area percentage of the epitaxial silicon wafer is A / N, wherein N is the number of regions into which the epitaxial silicon wafer is divided, and A is the number of regions whose Nano values ​​are greater than a third threshold; the Nano change value of each region is the difference between the Nano value of the epitaxial silicon wafer in that region and the Nano value of the substrate silicon wafer in that region.

[0088] The processing module 25 is used to match the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth equipment if the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing area is greater than a second threshold; if the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer.

[0089] After determining that the epitaxial silicon wafer has a Pin Nano defect, a shutdown instruction needs to be generated to stop the production state of the epitaxial growth equipment to prevent more epitaxial silicon wafers with a risk of Pin Nano defects from being produced, resulting in a waste of production resources.

[0090] In this embodiment, the Nano values ​​of the substrate silicon wafer and the epitaxial silicon wafer are obtained, and it is determined whether the epitaxial silicon wafer currently being produced has a Pin Nano defect based on the obtained Nano values. This embodiment can efficiently and timely identify Pin Nano defects, and can avoid misjudgment and missed judgment. In this way, when it is determined that a Pin Nano defect occurs in an epitaxial silicon wafer, a shutdown instruction can be generated to stop the subsequent epitaxial production state of the epitaxial growth equipment, without the need for a long lag period in the relevant scheme, thereby avoiding the production of more epitaxial silicon wafers with a risk of Pin Nano defects, thereby reducing the waste of production resources.

[0091] In some embodiments, the processing module 25 is further configured to perform any of the following:

[0092] If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano change values ​​of all regions are not greater than a second threshold, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect;

[0093] If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existence area is greater than a second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect.

[0094] The embodiment of the present invention further provides a method for manufacturing an epitaxial silicon wafer, the method comprising:

[0095] Using an epitaxial growth device to form an epitaxial layer on a surface of a substrate silicon wafer to obtain an epitaxial silicon wafer;

[0096] The defects of the epitaxial silicon wafer are detected according to the above-mentioned defect identification method to determine the defects of the epitaxial silicon wafer.

[0097] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.

[0098] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0099] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0100] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0101] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A defect identification method for epitaxial silicon wafer, characterized in that: include: Test the Nano value of the substrate silicon wafer; Placing the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer; Dividing the surface of the epitaxial silicon wafer into a plurality of regions, and obtaining the Nano value of each region; Determine the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region; If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing region is greater than a second threshold, matching the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth device; If the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer.

2. The defect identification method of epitaxial silicon wafer according to claim 1, characterized in that: The method further comprises any of the following: If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano change values ​​of all regions are not greater than a second threshold, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect; If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existence area is greater than a second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect.

3. The defect identification method of epitaxial silicon wafer according to claim 1, characterized in that: The Nano area percentage of the epitaxial silicon wafer is A / N, wherein N is the number of regions into which the epitaxial silicon wafer is divided, and A is the number of regions whose Nano values ​​are greater than a third threshold value; The Nano change value of each area is the difference between the Nano value of the epitaxial silicon wafer in that area and the Nano value of the substrate silicon wafer in that area.

4. The defect identification method of epitaxial silicon wafer according to claim 1, characterized in that: If the defect position of the epitaxial silicon wafer matches the position of the support rod, determining that the epitaxial silicon wafer has a Pin Nano defect includes: If the angle corresponding to the defect position of the epitaxial silicon wafer is 0°, 120° or 240°, it is determined that a Pin Nano defect occurs in the epitaxial silicon wafer.

5. The defect identification method of epitaxial silicon wafer according to claim 1, characterized in that: After determining that the epitaxial silicon wafer has a Pin Nano defect, the method further includes: A shutdown instruction is generated to stop the production state of the epitaxial growth equipment.

6. The defect identification method of epitaxial silicon wafer according to claim 1, characterized in that: The first threshold is 95%, and the second threshold is 2.

7. The defect identification method of epitaxial silicon wafer according to claim 3, characterized in that: The third threshold is 18 nm.

8. A defect identification device for epitaxial silicon wafers, characterized in that: include: Test module, used to test the Nano value of the substrate silicon wafer; An epitaxial growth module, used for placing the substrate silicon wafer into an epitaxial growth device for epitaxial growth to obtain an epitaxial silicon wafer; An acquisition module, used to divide the surface of the epitaxial silicon wafer into multiple regions and obtain the Nano value of each region; A calculation module, used to determine the Nano area percentage of the epitaxial silicon wafer and the Nano change value of each region according to the Nano value of each region; A processing module is used to match the defect position of the epitaxial silicon wafer with the position of the support rod of the epitaxial growth equipment if the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existing area is greater than a second threshold; if the defect position of the epitaxial silicon wafer matches the position of the support rod, it is determined that a pin-printed Pin Nano defect occurs in the epitaxial silicon wafer.

9. The defect identification device for epitaxial silicon wafer according to claim 8, characterized in that: The processing module is further configured to perform any of the following: If the Nano area percentage of the epitaxial silicon wafer is not greater than a first threshold and the Nano change values ​​of all regions are not greater than a second threshold, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect; If the Nano area percentage of the epitaxial silicon wafer is greater than a first threshold and the Nano change value of the existence area is greater than a second threshold, but the defect position of the epitaxial silicon wafer does not match the position of the support rod, it is determined that the epitaxial silicon wafer does not have a Pin Nano defect.

10. A method for manufacturing an epitaxial silicon wafer, characterized in that: The method comprises: Using an epitaxial growth device to form an epitaxial layer on a surface of a substrate silicon wafer to obtain an epitaxial silicon wafer; The defect identification method according to any one of claims 1 to 7 detects defects of the epitaxial silicon wafer to determine the defects of the epitaxial silicon wafer.

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