Digital small Q-switching circuit

Abstract

The invention discloses a small digital Q-switching circuit, which comprises a set feedback circuit, a primary booster circuit, a voltage doubling circuit, a pulse driving circuit and a high-voltage MOS switching circuit, and is characterized in that the set feedback circuit outputs a signal voltage FB to the primary booster circuit by performing operation processing on a received set voltage value and a high-voltage feedback value; the primary booster circuit is connected with the voltage doubling circuit, a high-voltage direct-current signal is output after voltage doubling and boosting, the high-voltage direct-current signal of the voltage doubling circuit is input into the high-voltage MOS switching circuit, and meanwhile, the voltage doubling circuit transmits a high-voltage feedback value VFB to the set feedback circuit; and after an external TTL control signal is input into the pulse driving circuit, a pulse control signal is output to the high-voltage MOS switching circuit. The high voltage output by the circuit is fast in rising edge and stable in work; higher voltage output can be obtained, and the pulse amplitude adjusting range is large; cost is low, and laser electro-optical conversion efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of lasers, and in particular relates to a digital small Q-switching circuit. Background Art

[0002] Nowadays, the application of laser technology is becoming more and more common. In the field of solid-state pulsed lasers, electro-optical Q-switching is one of the important technical units. The Q value mutation of the laser resonant cavity is achieved by adding or subtracting the voltage at both ends of the electro-optical crystal. The phase delay of the linearly polarized light passing through the crystal is changed, thereby compressing the continuous laser energy to produce high peak power and narrow pulse width laser pulses. That is, by Q-switching, the laser pulse width is compressed, the peak power of the laser is increased, or it is used to output lasers of different frequencies.

[0003] On the one hand, when adjusting the Q-switched high-voltage output, existing similar products basically rely on tools such as screwdrivers to rotate the potentiometer and adjust the size of the sampling resistor on the circuit (i.e., adjust the feedback voltage) to change the amplitude of the output high voltage. This method is difficult to operate in most usage environments and has poor usage conditions. Moreover, it is impossible to determine the range of the current output high voltage amplitude. In view of this situation, the digital Q-switched module circuit designed by this patent can simply and conveniently correct the output amplitude of the Q-switched module through the host device, and can timely and effectively understand the current module output amplitude and other parameters through the setting value of the host computer. It can effectively reduce the production and subsequent maintenance costs of the equipment used.

[0004] On the other hand, Q-switching technology is mainly divided into two categories: active Q-switching and passive Q-switching. The output of narrow pulse width laser is mainly achieved by active Q-switching. Active Q-switching is further divided into acousto-optic Q-switching, electro-optic Q-switching and rotating mirror Q-switching. Among them, electro-optic Q-switching is the main means to generate narrow pulse width and high peak power laser. Electro-optic Q-switching has the advantages of high switching speed, stable pulse output, high control accuracy and low intracavity loss.

[0005] Conventional methods for generating electro-optical Q-switched high voltage include, but are not limited to: a pulse voltage device method, a series avalanche tube method, a series switch MOS tube method, and the like.

[0006] Pulse transformer method: This method has a slow switching rate for Q modulation, with a high voltage rising edge of about 40ns. At the same time, the quality of the output high voltage is greatly affected by magnetic materials, ambient temperature and other conditions. However, this method has a simple hardware circuit, high boost efficiency, and a wide adjustable range of output voltage.

[0007] Series avalanche tube method: This method requires dozens or even dozens of avalanche tubes to be connected in series at the same time, which requires the consistency of the performance of the avalanche tubes to be very good. In addition, the damage rate of avalanche tubes is relatively high, which makes the market selection of components more difficult. However, the depressurization speed of this method is extremely fast, which can be less than 10ns.

[0008] Series switch MOS tube method: This method requires multiple drivers to drive different MOS tubes to work simultaneously. The synchronization time control is difficult and it is easy to cause overvoltage damage to a single MOS tube. However, this method can adapt to different voltage requirements by connecting different numbers of high-voltage MOS tubes in series, and it has strong adaptability. The switching speed is about 20ns, which is moderate, and the repetition frequency is high.

[0009] In addition, when adjusting the Q-switched high-voltage output, existing similar products basically rely on rotating the potentiometer to adjust the size of the sampling resistor on the circuit (i.e., adjusting the feedback voltage) to change the amplitude of the output high voltage. This method is difficult to operate in most usage environments and has poor usage conditions. Moreover, it is impossible to determine the range of the current output high voltage amplitude. In view of this situation, the digital Q-switched module circuit designed by this patent can simply and conveniently correct the output amplitude of the Q-switched module through the host device, and can timely and effectively understand the output amplitude and other parameters of the current module through the setting value of the host computer. It can effectively reduce the production and subsequent maintenance costs of the equipment used.

[0010] At present, the common electro-optical Q-switching switch drivers mainly use mechanical operations such as adjusting potentiometers to adjust the output high voltage. The voltage change is achieved by mechanically rotating the potentiometer gear. Most of them are large in size, difficult to operate and difficult to implement in the production, commissioning and maintenance of laser equipment. In addition, most products on the market are greatly affected by the ambient temperature. Qualified products need to be screened, the production cost is high, and it is not conducive to production commissioning and later maintenance after the equipment is assembled. Summary of the invention

[0011] In view of the deficiencies in the prior art, the present invention provides an output circuit of an electro-optical Q-switched driver which can be adjusted by digital means such as a host computer, and has the advantages of digitally adjustable output voltage, stable voltage output, high environmental adaptability and small size.

[0012] The present invention achieves this object through the following technical solutions:

[0013] A digital small Q-switching circuit includes a setting feedback circuit, a primary boost circuit, a voltage doubling circuit, a pulse drive circuit and a high-voltage MOS switch circuit. The setting feedback circuit outputs a signal voltage FB to the primary boost circuit by processing the received setting voltage value and the high-voltage feedback value through calculation. The primary boost circuit is connected to the voltage doubling circuit. The voltage doubling circuit outputs a high-voltage DC signal after boosting. The high-voltage DC signal of the voltage doubling circuit is input to the high-voltage MOS switch circuit. At the same time, the voltage doubling circuit transmits the high-voltage feedback value VFB to the setting feedback circuit. An external TTL control signal is input to the pulse drive circuit, and then a pulse control signal is output to the high-voltage MOS switch circuit.

[0014] Furthermore, the setting feedback circuit includes an ARM chip and a comparison amplifier. The ARM chip converts the voltage instruction of the host computer into a voltage setting value Vset. In the setting feedback circuit, the high-voltage feedback value VFB is connected to the comparison amplifier U3 through the resistor R12. The comparison amplifier U3 and the resistor R15 form a follower circuit. The voltage setting value Vset and the high-voltage feedback value VFB are connected to the comparison amplifier U3 through the resistors R16 and R19 for comparison. The comparison amplifier U3 and the capacitors C11, C12 and the resistor R21 form an integration circuit, so that the signal voltage FB output by the comparison amplifier U3 changes linearly.

[0015] Furthermore, in the primary boost circuit, the comparison op amp output signal voltage FB is transmitted to the PWM signal generator of the primary boost circuit, and the output PWM signal is input to the G pole of the MOS tube U1 through the current limiting resistor R3, the D pole of the MOS tube U1 is connected to the primary of the transformer and the VCC power supply in sequence, the S pole of the MOS tube U1 is connected to the parallel current limiting resistors R8 and R9 and then to the ground, filtering is performed between the VCC power supply and the ground through a parallel capacitor group, the current detection end of the PWM signal generator is connected to the high level end of the current limiting resistors R8 and R9 through the resistor R5, and the secondary of the transformer is connected to the voltage doubling circuit.

[0016] Furthermore, in the pulse driving circuit, the external TTL signal is input to the optocoupler U7 via Q+ and Q-, the output voltage of the optocoupler U7 is connected to the G pole of the MOS tube U5, the D pole of the MOS tube U5 outputs the pulse control signal Dri, and capacitors C24 and C19 are respectively arranged between the optocoupler U7 and the MOS tube U5 and at the output end of the circuit pulse control signal to block the DC signal.

[0017] Furthermore, in the high-voltage MOS switch circuit, the input high-voltage DC signal is connected to one end of the capacitor C15 via the resistor R11, the other end of the capacitor C15 is connected to the pulse signal output end, and a plurality of high-voltage MOS tube unit circuits are connected in series between the connection side of the resistor R11 and the capacitor C15 and the ground, and each high-voltage MOS tube unit circuit is respectively connected to the pulse control signal Dri.

[0018] Furthermore, in the high-voltage MOS tube unit circuit, a voltage stabilizing diode and a parallel resistor are connected between the G pole and the S pole of the MOS tube in the high-voltage MOS tube unit circuit to protect the G pole of the MOS tube, and the D pole and the S pole of the MOS tube are voltage-balanced with two series resistors.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The electro-optical Q-switching circuit solution for solid-state lasers provided by the present invention can adjust the output high voltage through digital means such as a host computer, and the operation is simple and convenient, and the volume is small and the reliability is high. It can effectively reduce the production debugging and later guarantee work of the laser. The high voltage output of the circuit of the present invention has a fast rising edge and stable operation; it can obtain a higher voltage output and a large pulse amplitude adjustment range; it has low cost and improves the electro-optical conversion efficiency of the laser. At the same time, it enhances the adaptability to the environment and greatly improves the qualified rate of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0022] Figure 1 It is a schematic diagram of the overall structure of the Q-switching circuit of the present invention;

[0023] Figure 2 This is a schematic diagram of the circuit structure of an ARM chip according to an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a feedback circuit structure is set for an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of a primary boost circuit according to an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the voltage doubling circuit structure according to an embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of the structure of a pulse drive circuit according to an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the structure of a high-voltage MOS switch circuit according to an embodiment of the present invention;

[0029] Figure 8 This is a voltage output reference waveform according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0031] The present invention discloses an embodiment of a digital small Q-switching circuit, the overall structure of which is as follows: Figure 1 As shown, it includes a setting feedback circuit, a primary voltage boost circuit, a voltage doubling circuit, a pulse drive circuit and a high-voltage MOS switch circuit.

[0032] Set the feedback circuit as Figure 3 As shown, it includes the ARM chip, comparison amplifier U3, voltage divider resistor and filter capacitor. In this embodiment, the ARM chip model is GD32F303, and the ARM chip circuit is as follows Figure 2 As shown. The voltage value instruction sent by the host computer is sent to the ARM chip for processing. After receiving the feedback signal, the ARM chip sends different set voltage values ​​Vset to the lower circuit according to the signal of different amplitudes to realize digital control. The set voltage value Vset is connected to the 2nd pin of the comparison amplifier U3 through the current limiting resistor R19 after the voltage division of the voltage divider resistors R23, R20 and the filter capacitor C20; the high-voltage feedback value VFB is connected to the 5th pin of the comparison amplifier U3 through the resistor R12. The comparison amplifier U3 and the resistor R15 form a follower circuit. The 6th pin of the comparison amplifier U3 is connected to one end of the resistors R15 and R13 respectively, and the other end of the resistor R15 is connected to the 7th pin of the comparison amplifier U3. The other end of the resistor R13 is grounded. After the ratio and follow-up calculation of the op amp, the high-voltage feedback value VFB is output from the 7th pin of the comparison amplifier U3 and connected to the 3rd pin of the comparison amplifier U3 through the resistor R16; the comparison amplifier U3 changes the voltage output value FB of the 1st pin in real time by comparing the difference between the set value input at the 2nd pin and the feedback value input at the 3rd pin. Capacitors C21, C22 and resistor R21 form an integrating capacitor to control the linear change of the signal voltage FB output by the comparison amplifier U3 and eliminate the sudden change of voltage. Capacitor C21 is connected to resistor R21, and the other end of capacitor C21 is respectively connected to resistor R19, pin 2 of the comparison amplifier U3 and one end of capacitor C22, and the other end of resistor R21 is respectively connected to pin 1 of the comparison amplifier U3 and the other end of capacitor C22. Capacitors C17 and C16 are filter capacitors, one end of capacitor C17 is respectively connected to resistor R16 and pin 3 of the comparison amplifier U3, and the other end is grounded; one end of capacitor C16 is respectively connected to the 3.3V circuit power supply and pin 8 of the comparison amplifier U3, and the other end is grounded.

[0033] Primary boost circuit such as Figure 4 As shown, it includes a PWM generator U2 (model UC2845), a MOS tube U1, a transformer T1, current limiting resistors R8, R9 and capacitors and resistors in the peripheral PWM generator circuit. The VCC power supply as the input voltage of the primary boost circuit is filtered by a parallel capacitor group composed of capacitors C7, C8, and C9. The PWM generator U2 outputs PWM signals with different duty cycles in real time according to the change of the signal voltage value FB output by the set feedback circuit. The PWM signal is transmitted to the G pole of the MOS tube U1 through the current limiting resistor R3 to control the on and off of the MOS tube U1. When the MOS tube U1 is turned on, the primary side of the transformer T1 is charged, and the secondary side of the transformer T1 is boosted to output the voltage to the voltage doubling circuit. The current limiting resistors R8 and R9 are connected in parallel to control the maximum current when the primary side of the transformer T1 is charged. While limiting the charging current of the primary side of the transformer T1, it also increases the power of the current limiting resistor to prevent the resistor from being damaged during high-frequency output. The resistor R6 and the capacitor C10 control the frequency of the output signal of the PWM generator. The specific circuit structure is as follows:

[0034] The signal voltage FB output by the feedback circuit is set to be connected to the resistor R6, one end of the capacitor C10 and the pin 2 of the PWM generator U2, the pin 1 of the PWM generator U2 is connected to the other end of the resistor R6 and the capacitor C10, the pin 7 of the PWM generator U2 is connected to the power supply VCC and one end of the capacitor C14, and the pin 5 of the PWM generator U2 is connected to the other end of C14 and grounded. The VCC power supply is connected to one end of the filter capacitor group composed of three parallel capacitors and the D pole of the MOS tube U1. The primary of the transformer T1 is provided between the D pole of the MOS tube U1 and the filter capacitor group, and the secondary of the transformer T1 provides power for the voltage doubler circuit.

[0035] The PWM signal is output from the 6th pin of the PWM generator U2, and connected to the G pole of the MOS tube U1 through the current limiting resistor R3. The 3rd pin of the PWM generator U2 is respectively connected to one end of the capacitor C12 and the resistor R5. The 8th pin of the PWM generator U2 is respectively connected to one end of the resistor R7 and the capacitor C11. The 4th pin of the PWM generator U2 is respectively connected to one end of the capacitor C13 and the other end of the resistor R7. The S pole of the MOS tube U1 is connected to the other end of R5 and one end of the resistors R8 and R9. The other end of the filter capacitor group is respectively connected to the other ends of the resistors R8, R9, the capacitors C11, C12, and C13, and the ground terminal connected to the 5th pin of the PWM generator U2.

[0036] Voltage doubler circuit Figure 5As shown, it includes capacitors C1-C6, diodes D1-D5 and voltage-dividing resistors R1, R2, and R4. The secondary side of the transformer T1 of the primary boost circuit is connected to the voltage doubler circuit as a power source, and the voltage is boosted through the set capacitor and diode combination unit. The capacitors C1-C5 and the diodes D1-D5 form a 5-fold voltage doubler circuit. Because the diodes have rectification and guidance, the voltage is stored in the respective parallel capacitors, and then connected in series according to the principle of polarity addition to output the required high voltage. The output voltage of the primary boost circuit is introduced into the voltage doubler circuit through the anode of the diode D5, and is output after being boosted five times (the voltage doubler circuit is not limited to the 5-fold voltage in this example, and is selected according to the specific situation).

[0037] C6 is a filter capacitor, which is connected between the output high voltage and the ground to filter and reduce noise of the output high voltage. Resistors R1, R2, and R4 are voltage divider resistors, which feed back the collected voltage feedback value VFB to the set feedback circuit in a closed loop to keep the output high voltage in a controllable state. The high-voltage output end of the voltage doubler circuit is respectively connected to one end of the resistor R1 and one end of the capacitor C6, the other end of R1 is connected to one end of the resistor R4, the other end of the capacitor C6 is connected to one end of the resistor R2 and grounded, and the other ends of the resistors R2 and R4 are connected and output the high-voltage feedback value VFB.

[0038] Pulse drive circuit such as Figure 6 As shown, it includes an optocoupler U7, a MOS tube U5, a correction capacitor C24 and other peripheral capacitors and resistors. The external TTL control signal is connected to the circuit through Q+ and Q-. When the TTL control signal is at a high level, the secondary of the optocoupler U7 is turned on, and the output signal of the 5-pin of the optocoupler U7 is differentiated by the correction capacitor C24 to control the conduction of the MOS tube U5. Similarly, when the MOS tube U5 is turned on, the pulse control signal Dri is output through the capacitor C19 to drive the subsequent circuit. Capacitors C24 and C19 are used to block DC signals, limit the output signal pulse width, and prevent the MOS tube U5 from being turned on for too long and burning the circuit. Therefore, the capacitance of capacitors C24 and C19 should not be too large. This embodiment uses 104 capacitors. The specific circuit structure is as follows:

[0039] The external TTL control signal is connected to the circuit through Q+ and Q-. The Q+ input end is connected to one end of C23 and R25 respectively, and the other ends of C23 and R25 are connected to pin 1 of the optocoupler U7. The Q- input end is connected to pin 3 of the optocoupler U7. Pin 6 of the optocoupler U7 is connected to capacitor C18, one end of resistor R18 and the power supply VCC. The other end of capacitor C18 is grounded. The other end of resistor R18 is connected to one end of capacitor C19 and the D pole of MOS tube U5. Pin 5 of the optocoupler U7 is connected to one end of capacitor C24. The other end of capacitor C24 is connected to the G pole of MOS tube U5 and one end of resistor R26 respectively. Pin 4 of the optocoupler U7 is connected to the other end of resistor R26 and the S pole of MOS tube U5 and grounded. The other end of capacitor C19 outputs the pulse control signal Dri.

[0040] High voltage MOS switch circuit such as Figure 7 As shown, it includes multiple high-voltage MOS tube unit circuits connected in series. This embodiment uses 4 high-voltage MOS tube unit circuits connected in series. The high-voltage MOS tube unit circuit includes a high-voltage MOS tube. To ensure the consistency of the voltage borne by each MOS tube, the D pole and S pole of the MOS tube are equalized with two series resistors (such as resistors R14 and R17 connected in parallel at both ends of the MOS tube U4) to prevent the voltage at both ends of a single MOS tube from being too high. The MOS tube is a unipolar voltage control device, which not only has the self-shutdown capability but also has significant advantages such as low driving power, fast working speed, no secondary breakdown problem, and a wide safe working area. Each MOS tube is driven by a pulse transformer. In order for the MOS tube to be reliably triggered and turned on, the trigger pulse voltage should be higher than the turn-on voltage of the tube, but the G pole input voltage of the MOS tube should be controlled within the maximum input voltage value. Therefore, a voltage regulator diode ( Figure 7 The four parallel unit circuits Z1, Z2, Z3, and Z4) and the parallel resistor RR protect the G pole of the MOS tube. The voltage boosted by the voltage doubling circuit is connected to the high-voltage MOS switch circuit through the charging resistor R11. When the high voltage is turned on, one end of the capacitor C15 is grounded. According to the capacitor characteristics, the voltage across the capacitor changes slowly. Therefore, the voltage at the other end of the capacitor C15 is higher than the ground end, so the circuit outputs a pulse voltage.

[0041] One end of the output side of the pulse transformer is connected to the G pole, the cathode of the voltage-stabilizing diode and one end of the resistor RR respectively, and the other end of the output side is connected to the anode of the voltage-stabilizing diode, the other end of the resistor RR and the S pole respectively. One end of the input side of the pulse transformer is grounded, and the other end is connected to the pulse control signal dri. One end of the multiple parallel high-voltage MOS tube unit circuits is connected to the pulse control signal dri, and the other end is connected to one end of C15 and R11. The other end of R11 is connected to the output voltage boosted by the voltage doubling circuit. The other end of C15 is connected to one end of the resistor R10 and HV+ respectively, and the other end of R10 is connected to HV- and grounded. The final pulse voltage is output by HV+ and HV-.

[0042] The output voltage reference waveform of this embodiment is as follows: Figure 8 shown.

[0043] In this technical solution, the driving of the high-voltage MOS tubes is realized by respective pulse transformers, and a single-input multi-output pulse transformer can also be used to ensure synchronous driving of the series-connected high-voltage MOS.

[0044] The present invention has been described in detail above through embodiments, but the contents described are only exemplary embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. The protection scope of the present invention is defined by the claims. Anyone who utilizes the technical solution described in the present invention, or a technician in the field, inspired by the technical solution of the present invention, designs a similar technical solution within the essence and protection scope of the present invention to achieve the above technical effects, or makes equal changes and improvements to the scope of application, shall still belong to the scope of protection covered by the patent of the present invention. It should be noted that in order to make a clear statement, the description of some components and processes that have no direct and obvious connection with the scope of protection of the present invention but are known to those skilled in the art are omitted in the description of the present invention.

Claims

1. A digital small Q-switching circuit, characterized in that: It includes a setting feedback circuit, a primary boost circuit, a voltage doubling circuit, a pulse drive circuit and a high-voltage MOS switch circuit. The setting feedback circuit outputs a signal voltage FB to the primary boost circuit by calculating and processing the received setting voltage value and the high-voltage feedback value. The primary boost circuit is connected to the voltage doubling circuit. The voltage doubling circuit outputs a high-voltage DC signal after boosting. The high-voltage DC signal of the voltage doubling circuit is input to the high-voltage MOS switch circuit. At the same time, the voltage doubling circuit transmits the high-voltage feedback value VFB to the setting feedback circuit. An external TTL control signal is input to the pulse drive circuit, and then a pulse control signal is output to the high-voltage MOS switch circuit.

2. A digital small Q-switching circuit according to claim 1, characterized in that: The setting feedback circuit includes an ARM chip and a comparison amplifier. The ARM chip converts the voltage instruction of the host computer into a voltage setting value Vset. In the setting feedback circuit, the high-voltage feedback value VFB is connected to the comparison amplifier U3 through the resistor R12. The comparison amplifier U3 and the resistor R15 form a follower circuit. The voltage setting value Vset and the high-voltage feedback value VFB are connected to the comparison amplifier U3 through the resistors R16 and R19 for comparison. The comparison amplifier U3 and the capacitors C11, C12 and the resistor R21 form an integration circuit, so that the signal voltage FB output by the comparison amplifier U3 changes linearly.

3. A digital small Q-switching circuit according to claim 1, characterized in that: In the primary boost circuit, the comparison op amp output signal voltage FB is transmitted to the PWM signal generator of the primary boost circuit, and the output PWM signal is input to the G pole of the MOS tube U1 through the current limiting resistor R3, the D pole of the MOS tube U1 is connected to the primary of the transformer and the VCC power supply in sequence, the S pole of the MOS tube U1 is connected to the parallel current limiting resistors R8 and R9 and then to the ground, and filtering is performed between the VCC power supply and the ground through a parallel capacitor group, the current detection end of the PWM signal generator is connected to the high level end of the current limiting resistors R8 and R9 through the resistor R5, and the secondary of the transformer is connected to the voltage doubling circuit.

4. A digital small Q-switching circuit according to claim 1, characterized in that: In the pulse driving circuit, the external TTL signal is input to the optocoupler U7 via Q+ and Q-, the output voltage of the optocoupler U7 is connected to the G pole of the MOS tube U5, the D pole of the MOS tube U5 outputs the pulse control signal Dri, and capacitors C24 and C19 are respectively arranged between the optocoupler U7 and the MOS tube U5 and at the output end of the circuit pulse control signal to block the DC signal.

5. A digital small Q-switching circuit according to claim 1, characterized in that: In the high-voltage MOS switch circuit, the input high-voltage DC signal is connected to one end of the capacitor C15 via the resistor R11, and the other end of the capacitor C15 is connected to the pulse signal output end. A plurality of high-voltage MOS tube unit circuits are connected in series between the connection side of the resistor R11 and the capacitor C15 and the ground, and each high-voltage MOS tube unit circuit is respectively connected to the pulse control signal Dri.

6. A digital small Q-switching circuit according to claim 5, characterized in that: In the high-voltage MOS tube unit circuit, a voltage stabilizing diode and a parallel resistor are connected between the G pole and the S pole of the MOS tube in the high-voltage MOS tube unit circuit to protect the G pole of the MOS tube, and the D pole and the S pole of the MOS tube are voltage-balanced with two series resistors.

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