Resonator and preparation method thereof

Abstract

The invention provides a resonator and a preparation method thereof, and relates to the technical field of resonators, the resonator comprises a substrate, a first electrode layer, a first piezoelectric layer and a second electrode layer, the first electrode layer, the first piezoelectric layer and the second electrode layer are sequentially stacked to the substrate, and the first electrode layer, the first piezoelectric layer and the second electrode layer form a first overlapping area in the stacking direction; a capacitor stacking layer located outside the first overlapping area is arranged on the first piezoelectric layer, a passivation layer is arranged above the second electrode layer, and the passivation layer extends above the capacitor stacking layer. Therefore, the capacitor can be integrated in the resonator, and the capacitor can be directly integrated on a chip, so that the performance of the resonator and the filter is improved. And the passivation layer and the capacitor stacking layer are mutually independent, so that the material thickness of the dielectric layer in the capacitor stacking layer can be optimized according to the performance and can also be flexibly varied according to the requirement.

Description

Technical Field

[0001] The present application relates to the technical field of resonators, and in particular to a resonator and a method for preparing the same. Background Art

[0002] With the rapid development of wireless communication technology, there are more and more devices that send and receive information at higher frequency bands, and the requirements for RF front-end circuits are becoming more and more stringent, so the market demand for high-performance filters is increasing. Bulk acoustic wave filters are gradually becoming the mainstream of the market due to their high quality factor, good out-of-band suppression, and high rectangular coefficient.

[0003] BAW filters are composed of multiple resonators cascaded in a specific circuit. High-performance filters require high-performance resonators with high quality factors. High quality factors can make filters have smaller insertion loss and steeper roll-off characteristics, and have better filtering performance. In summary, it is very important to prepare resonators with high stability and excellent performance.

[0004] Due to the limitation of the electromechanical coupling coefficient of the resonator material, the bandwidth of the BAW filter is relatively small. In practical applications, passive devices such as capacitors or inductors are usually added as matching circuits or to increase the bandwidth of the filter, adjust the filtering characteristics, etc. Surface mount capacitors are widely used in various electronic products such as mobile phones, computers, tablet computers, televisions, digital cameras, audio equipment, automotive electronics, etc. However, when used in filters, they need to be connected to the resonator filter circuit, which requires additional routing, and their size is larger than that of the resonator, which reduces the filter performance and cannot reduce the area, greatly limiting the performance of the thin film BAW filter. Summary of the invention

[0005] The purpose of the present application is to provide a resonator and a method for preparing the same in view of the deficiencies in the above-mentioned prior art.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] According to one aspect of an embodiment of the present application, a resonator is provided, comprising a substrate and a first electrode layer, a first piezoelectric layer, and a second electrode layer stacked sequentially on the substrate, wherein the first electrode layer, the first piezoelectric layer, and the second electrode layer form a first overlapping region along a stacking direction, a capacitor stacking layer located outside the first overlapping region is arranged on the first piezoelectric layer, a passivation layer is arranged above the second electrode layer, and the passivation layer extends above the capacitor stacking layer.

[0008] Optionally, the capacitor stack layer includes a lower electrode, a dielectric layer and an upper electrode stacked in sequence on the first piezoelectric layer; the resonator also includes a first lead-out portion and a second lead-out portion, the first lead-out portion passes through the passivation layer and contacts the lower electrode, the second lead-out portion passes through the passivation layer and contacts the upper electrode, and the first lead-out portion and the second lead-out portion do not overlap in the stacking direction.

[0009] Optionally, the lower electrode and the upper electrode have a second overlapping region in the stacking direction, and the first lead-out portion and the second lead-out portion are both located outside the second overlapping region.

[0010] Optionally, the capacitor stacking layer includes multiple upper electrodes and a lower electrode and a dielectric layer stacked sequentially on the first piezoelectric layer. The multiple upper electrodes are arranged on the side of the dielectric layer away from the lower electrode, and the multiple upper electrodes are spaced apart from each other. The multiple upper electrodes cooperate with the lower electrodes to form multiple capacitors.

[0011] Optionally, the resonator further includes a third lead-out portion and a plurality of fourth lead-out portions, the third lead-out portion penetrates the passivation layer and contacts the lower electrode, and the plurality of fourth lead-out portions respectively penetrate the passivation layer and contact the plurality of upper electrodes one by one.

[0012] Optionally, the resonator further includes a plurality of fourth lead-out portions, and the plurality of fourth lead-out portions respectively penetrate the passivation layer and respectively contact the plurality of upper electrodes one by one.

[0013] Optionally, an insulating layer is provided between the first piezoelectric layer and the capacitor stack layer.

[0014] Optionally, a mass load layer is provided between the first piezoelectric layer and the second electrode layer and is located in the first overlapping region.

[0015] Optionally, a second piezoelectric layer is arranged between the substrate and the first electrode layer.

[0016] Optionally, a first cavity and a second cavity are further provided between the substrate and the first piezoelectric layer, the first cavity is at least partially located in the first overlapping region, and the second cavity is located directly below the capacitor stack layer.

[0017] Optionally, the second cavity is filled with an oxide layer.

[0018] Another aspect of the present invention provides a method for preparing a resonator, the method comprising:

[0019] sequentially forming a stacked second piezoelectric layer, a first electrode layer and a first piezoelectric layer on a substrate;

[0020] forming a mass loading layer on the first piezoelectric layer;

[0021] forming a second electrode layer on the mass load layer and forming a lower electrode on the first piezoelectric layer, wherein the second electrode layer and the lower electrode are spaced apart;

[0022] forming a dielectric layer on the lower electrode;

[0023] forming at least one upper electrode on the dielectric layer, wherein the lower electrode, the dielectric layer and the at least one upper electrode form a capacitor stack layer;

[0024] A passivation layer is formed on the second electrode layer, and the passivation layer extends above the capacitor stacking layer.

[0025] The beneficial effects of this application include:

[0026] The present application provides a resonator and a preparation method thereof, wherein the resonator comprises a substrate and a first electrode layer, a first piezoelectric layer and a second electrode layer sequentially stacked on the substrate, wherein the first electrode layer, the first piezoelectric layer and the second electrode layer form a first overlapping region along the stacking direction, and a capacitor stacking layer located outside the first overlapping region is arranged on the first piezoelectric layer, and a passivation layer is arranged above the second electrode layer, and the passivation layer extends above the capacitor stacking layer. In this way, the capacitor can be integrated inside the resonator, and the capacitor can be directly integrated on the chip. Compared with the external capacitor, the area is smaller and no additional lead-out path is required to avoid the corresponding electrical parasitics, thereby improving the performance of the resonator and the filter. In addition, the passivation layer and the capacitor stacking layer are independent of each other, so the material thickness of the dielectric layer inside the capacitor stacking layer can be not limited by the passivation requirements of the device, so the material thickness of the dielectric layer inside the capacitor stacking layer can be optimized according to the performance, can be flexible and changeable according to the requirements, and can also be fine-tuned for the integrated capacitor to achieve the capacitance value, thereby overcoming the defects in the process integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 One of the state schematic diagrams of a resonator preparation method provided in an embodiment of the present application;

[0029] Figure 2 A second state diagram of a resonator preparation method provided in an embodiment of the present application;

[0030] Figure 3 A third state diagram of a resonator preparation method provided in an embodiment of the present application;

[0031] Figure 4 A fourth state diagram of a resonator preparation method provided in an embodiment of the present application;

[0032] Figure 5 A fifth state diagram of a resonator preparation method provided in an embodiment of the present application;

[0033] Figure 6 A sixth state diagram of a resonator preparation method provided in an embodiment of the present application;

[0034] Figure 7 A seventh state diagram of a resonator preparation method provided in an embodiment of the present application;

[0035] Figure 8 One of the structural schematic diagrams of a resonator provided in an embodiment of the present application;

[0036] Fig. 9 A second structural schematic diagram of a resonator provided in an embodiment of the present application;

[0037] Fig.10 A third structural schematic diagram of a resonator provided in an embodiment of the present application;

[0038] Fig.11 A fourth structural schematic diagram of a resonator provided in an embodiment of the present application;

[0039] Fig.12 A fifth structural diagram of a resonator provided in an embodiment of the present application;

[0040] Fig.13 This is a sixth structural schematic diagram of a resonator provided in an embodiment of the present application.

[0041] Icon: 101-substrate; 102-sacrificial layer; 103-second piezoelectric layer; 104-first electrode layer; 105-first piezoelectric layer; 106-electrode lead hole; 107-mass load layer; 108-first metal layer; 109-second electrode layer; 110-second metal layer; 111-lower electrode; 112-dielectric layer; 113-upper electrode; 114-capacitor stacking layer; 115-passivation layer; 116-first lead part; 117-second lead part; 118-sixth lead part; 119-fifth lead part; 120-first cavity; 121-insulating layer; 122-second cavity; 123-third lead part; 124-fourth lead part. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0046] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0047] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] In one aspect of an embodiment of the present application, a resonator is provided, referring to Figures 8 to 13Any of the drawings includes a substrate 101 and a piezoelectric stack layer disposed on the substrate 101, wherein the piezoelectric stack layer includes a first electrode layer 104, a first piezoelectric layer 105, and a second electrode layer 109 sequentially stacked on the substrate 101, so that after an electrical signal is applied to the first electrode layer 104 and the second electrode layer 109, the first piezoelectric layer 105 is used to realize the mutual conversion of electrical energy and mechanical energy. It should be known that the stacking direction in this application is Figures 8 to 13 The vertical direction of any one of the frames, or the thickness direction of the substrate 101 .

[0049] Continue to refer to Figures 8 to 13 In any of the pictures, the first electrode layer 104, the first piezoelectric layer 105 and the second electrode layer 109 form a first overlapping region along the stacking direction. Usually, the first overlapping region also serves as an effective resonance region or an effective working region of the resonator.

[0050] To optimize the performance of the resonator, such as Figures 8 to 13 In any of the figures, a capacitor stacking layer 114 is provided on the first piezoelectric layer 105, so that the capacitor can be integrated inside the resonator, and the capacitor can be directly integrated on the chip. Compared with the external capacitor, the area is smaller and no additional lead-out path is required, thereby avoiding the corresponding electrical parasitics, thereby improving the performance of the resonator and the filter.

[0051] When integrating the capacitor stack layer 114, the capacitor stack layer 114 and the first overlapping region can be made as independent of each other as possible. Therefore, the capacitor stack layer 114 can be located outside the first overlapping region. For example, there is no first electrode layer 104 directly below the capacitor stack layer 114. In other words, the capacitor stack layer 114 and the first electrode layer 104 do not intersect in the stacking direction. This ensures that the capacitor stack layer 114 integrated on the chip does not affect the first overlapping region of the resonator.

[0052] On this basis, if Figures 8 to 13 In any of the drawings, a passivation layer 115 may be provided above the entire device (on the side facing away from the substrate 101) to provide passivation protection for other basic levels of the resonator. Specifically, the passivation layer 115 may be located above the second electrode layer 109, and the passivation layer 115 also extends above the capacitor stack layer 114 and the first piezoelectric layer 105. It should be particularly noted here that in the present application, the passivation layer 115 and the capacitor stack layer 114 are independent of each other. Therefore, the material thickness of the dielectric layer 112 inside the capacitor stack layer 114 may not be limited by the device's passivation requirements, so the material thickness of the dielectric layer 112 inside the capacitor stack layer 114 can be optimized based on performance or can be flexible and varied based on demand.

[0053] The capacitor stack layer 114 mentioned above should refer to a structure that can have capacitor characteristics, and its specific structure can be reasonably selected and set according to actual needs. Of course, for ease of understanding, this application will describe some examples in conjunction with the accompanying drawings.

[0054] Example 1

[0055] Please refer to Figure 8 , the capacitor stacking layer 114 is located outside the first overlapping region, specifically, it can be located on the right side of the first overlapping region. The capacitor stacking layer 114 includes a lower electrode 111, a dielectric layer 112 and an upper electrode 113, wherein the lower electrode 111 is located on the upper surface of the first piezoelectric layer 105, the dielectric layer 112 is located above the lower electrode 111, and the upper electrode 113 is located above the dielectric layer 112, thereby forming a single capacitor structure through the lower electrode 111, the dielectric layer 112 and the upper electrode 113.

[0056] In order to smoothly lead out the lower electrode 111 and the upper electrode 113 of the capacitor stack layer 114, continue to refer to Figure 8 The resonator further includes a first lead-out portion 116 and a second lead-out portion 117, wherein the first lead-out portion 116 penetrates the passivation layer 115 and contacts the lower electrode 111, and the second lead-out portion 117 penetrates the passivation layer 115 and contacts the upper electrode 113, so that the capacitor stack structure can be connected to the circuit through the first lead-out portion 116 and the second lead-out portion 117. And the first lead-out portion 116 and the second lead-out portion 117 do not overlap in the stacking direction, in other words, the portion of the lower electrode 111 that contacts the first lead-out portion 116 and the portion of the upper electrode 113 that contacts the second lead-out portion 117 are displaced in the stacking direction to form a non-intersecting state, so that the upper electrode 113 and the lower electrode 111 can be more conveniently led out.

[0057] The lower electrode 111 and the upper electrode 113 of the capacitor stack layer 114 will form a second overlapping area in the stacking direction to meet the capacitor setting requirements. On this basis, the performance of the capacitor stack layer 114 can be optimized, for example, the first lead portion 116 and the second lead portion 117 are both located outside the second overlapping area, so that the first lead portion 116 can be avoided from being directly opposite to the upper electrode 113, and the second lead portion 117 can be avoided from being directly opposite to the lower electrode 111, thereby improving the parasitic capacitance that may be formed between the first lead portion 116 and the upper electrode 113, and the second lead portion 117 and the lower electrode 111 are the same.

[0058] Example 2

[0059] Please refer to Fig. 9 or Fig.11, the capacitor stacking layer 114 is located outside the first overlapping area, specifically, it can be located on the right side of the first overlapping area. The capacitor stacking layer 114 includes a lower electrode 111, a dielectric layer 112 and a plurality of upper electrodes 113, wherein the lower electrode 111 is stacked on the first piezoelectric layer 105, the dielectric layer 112 is stacked on the lower electrode 111, and the plurality of upper electrodes 113 are laid flat on the surface of the dielectric layer 112 on the side away from the lower electrode 111, and the plurality of upper electrodes 113 are spaced apart from each other. Each upper electrode 113 has a portion that is directly opposite to the lower electrode 111, so that an upper electrode 113 can cooperate with the lower electrode 111 to form a capacitor. Similarly, the plurality of upper electrodes 113 can cooperate with the lower electrode 111 to form a plurality of capacitors respectively. Specifically, for example Fig. 9 or Fig.11 In the figure, the capacitor stack layer 114 includes a lower electrode 111, a dielectric layer 112 and two upper electrodes 113, wherein the lower electrode 111 is stacked on the first piezoelectric layer 105, the dielectric layer 112 is stacked on the lower electrode 111, the two upper electrodes 113 are laid flat on the dielectric layer 112, and the two upper electrodes 113 are arranged at intervals on the left and right. The upper electrode 113 on the left cooperates with the lower electrode 111 below to form a capacitor, and the upper electrode 113 on the right cooperates with the lower electrode 111 below to form another capacitor.

[0060] In order to meet different capacitor connection requirements, the lower electrode 111 may be selectively led out or not led out, which will be described below in conjunction with the accompanying drawings:

[0061] For example, refer to Fig. 9 As shown, the lower electrode 111 can be led out, specifically: the resonator also includes a third lead-out portion 123 and a plurality of fourth lead-out portions 124, wherein the third lead-out portion 123 penetrates the passivation layer 115 and contacts the lower electrode 111, and the plurality of fourth lead-out portions 124 penetrate the passivation layer 115 and contact the plurality of upper electrodes 113 one by one. In this way, the lower electrode 111 can be led out through the third lead-out portion 123, and each upper electrode 113 can be led out through a fourth lead-out portion 124. In this way, when the capacitor stack layer 114 is connected to the circuit, the lower electrode 111 and at least a portion of the upper electrode 113 can be flexibly selected to be connected according to demand. For example, when a capacitor needs to be connected, the lower electrode 111 and an upper electrode 113 can be connected, and when two capacitors need to be connected, the lower electrode 111 and the two upper electrodes 113 can be connected to the circuit. In addition, it should be understood that when the lower electrode 111 is also led out, the capacitor connected to the circuit can be connected in a variety of connection forms such as series or parallel.

[0062] For example, refer to Fig.11As shown, the lower electrode 111 may not be led out. Specifically, the resonator further includes a plurality of fourth lead-out portions 124, wherein the plurality of fourth lead-out portions 124 respectively penetrate the passivation layer 115 and respectively contact the plurality of upper electrodes 113 one by one. In this way, the lower electrode 111 may not be led out, and each upper electrode 113 may be led out through a fourth lead-out portion 124. In this way, when the capacitor stack layer 114 is connected to the circuit, two of the capacitors can form a series relationship through the lower electrode 111, for example Fig.11 In the figure, the upper electrode 113 on the left and the lower electrode 111 form a capacitor, and the upper electrode 113 on the right and the lower electrode 111 form a capacitor. When connected to the circuit, they can be connected only through the two fourth lead-out parts 124 of the two capacitors, so that the two capacitors can form a series relationship.

[0063] When the capacitor stack layer 114 can form multiple capacitors, the series or parallel connection between different capacitors can be adjusted through external leads, thereby adjusting the capacitance value to meet the requirements of capacitance accuracy in the manufacturing process. Fig.10 As shown, two capacitors are shown, among which the capacitor on the right can be used as the main capacitor a, and the capacitor on the left can be used as the auxiliary capacitor b. In order to meet the capacitor accuracy requirements in the preparation process, in the subsequent packaging test, if the accuracy of the main capacitor a does not meet the requirements, the main capacitor a and the auxiliary capacitor b will be connected in series or in parallel through the connection of external leads, thereby adjusting the capacitance value.

[0064] Here, the capacitance value of the auxiliary capacitor is 10-30% of the capacitance value of the main capacitor, so that the adjustment range of the capacitance value can more easily meet actual needs.

[0065] In some possible implementations, an insulating layer 121 is disposed between the first piezoelectric layer 105 and the capacitor stack layer 114, so that the capacitor stack layer 114 can be isolated by the insulating layer 121 to improve the performance of the capacitor stack layer 114. Fig.12 In the embodiment, an insulating layer 121 is provided between the first piezoelectric layer 105 and the capacitor stack layer 114. It should be understood that Figures 9 to 11 In any identical or similar resonator, an insulating layer 121 may be disposed between the first piezoelectric layer 105 and the capacitor stack layer 114 to optimize the performance of the resonator.

[0066] In some possible implementations, such as Figures 8 to 13As shown, a mass load layer 107 located in the first overlapping region is provided between the first piezoelectric layer 105 and the second electrode layer 109. The frequency of the resonator can be adjusted by the mass load layer 107. When the mass load layer 107 is located between the first piezoelectric layer 105 and the second electrode layer 109, the material of the mass load layer 107 can be the same as that of the second electrode layer 109, thereby simplifying the preparation process.

[0067] In some possible implementations, such as Figures 8 to 13 As shown, a second piezoelectric layer 103 is provided between the substrate 101 and the first electrode layer 104 , and the second piezoelectric layer 103 can improve the quality of subsequent formation of the first electrode layer 104 .

[0068] In some possible implementations, such as Figures 8 to 13 As shown, there is a first cavity 120 between the substrate 101 and the first electrode layer 104, and the first cavity 120 is substantially located in the first overlapping region, so that the sound waves in the first overlapping region can be reflected by the first cavity 120, thereby improving the performance of the resonator. It should be known that when there is a first cavity 120 between the substrate 101 and the first electrode layer 104, the first overlapping region is formed by the cavity, the first electrode layer 104, the first piezoelectric layer 105 and the second electrode layer 109 along the stacking direction.

[0069] In some possible implementations, such as Fig.13 As shown, a second cavity 122 is further provided between the substrate 101 and the first piezoelectric layer 105, and the second cavity 122 is located directly below the capacitor stack layer 114. In this way, the second cavity 122 can isolate the influence of the capacitor area formed by the substrate 101 and the capacitor stack layer 114, thereby improving the performance of the capacitor formed by the capacitor stack layer 114.

[0070] In some possible implementations, an oxide layer is filled in the second cavity 122 , so that the second cavity 122 can be filled with the oxide layer to improve the support strength under the capacitor stack layer 114 , especially for a multi-capacitor structure, which helps to improve process stability.

[0071] In some possible implementations, such as Figures 8 to 13 As shown, in order to facilitate the lead-out of the first electrode layer 104, a fifth lead-out portion 119 composed of the first metal layer 108 and the second metal layer 110 may be provided, and the fifth lead-out portion 119 passes through the passivation layer 115 and the first piezoelectric layer 105 and contacts the first electrode layer 104. Similarly, in order to facilitate the lead-out of the second electrode layer 109, a sixth lead-out portion 118 formed by the second metal layer 110 may be provided, and the sixth lead-out portion 118 passes through the passivation layer 115 and contacts the second electrode layer 109.

[0072] Another aspect of the present invention provides a method for preparing a resonator, the method comprising:

[0073] S10 : forming a stacked second piezoelectric layer 103 , a first electrode layer 104 and a first piezoelectric layer 105 in sequence on the substrate 101 .

[0074] like Figure 1 As shown, after the second piezoelectric layer 103 is formed on the substrate 101 , a metal layer is deposited on the second piezoelectric layer 103 , and the first electrode layer 104 is formed after the metal layer is patterned, and then the first piezoelectric layer 105 is formed on the first electrode layer 104 .

[0075] It is understandable that when it is necessary to form the first cavity 120 and / or the second cavity 122, the first cavity 120 and / or the second cavity 122 can be formed on the substrate 101 by etching, and then the sacrificial layer 102 (oxide layer) is filled in the first cavity 120 and / or the second cavity 122 to make the surface of the substrate 101 smooth, which can facilitate the convenience of subsequent layers.

[0076] In order to facilitate the extraction of the first electrode layer 104 , the first piezoelectric layer 105 may be etched to form an electrode extraction hole 106 penetrating the first piezoelectric layer 105 .

[0077] S20 : ​​forming a mass load layer 107 on the first piezoelectric layer 105 .

[0078] like Figure 2 As shown, a mass load layer 107 is formed on the first piezoelectric layer 105 by deposition and patterning, and is generally located in the first overlapping region. Correspondingly, in order to simplify the process, the mass load layer 107 can be made of metal, so that the mass load layer 107 and the first metal layer 108 can be formed by depositing a whole metal layer and patterning, wherein the first metal layer 108 is located in the electrode lead-out hole 106.

[0079] S30: forming a second electrode layer 109 on the mass load layer 107 and forming a lower electrode 111 on the first piezoelectric layer 105, wherein the second electrode layer 109 and the lower electrode 111 are spaced apart from each other.

[0080] like Figure 3 As shown, a whole layer of metal is deposited on the mass load layer 107, so as to form a second electrode layer 109, a lower electrode 111 on the first piezoelectric layer 105 and a second metal layer 110 on the first metal layer 108 respectively after patterning, and the three are spaced apart from each other.

[0081] S40 : forming a dielectric layer 112 on the lower electrode 111 .

[0082] like Figure 4 As shown, a dielectric layer 112 is formed on the lower electrode 111 to facilitate the construction of a dielectric of a capacitor.

[0083] S50 : forming at least one upper electrode 113 on the dielectric layer 112 , wherein the lower electrode 111 , the dielectric layer 112 and the at least one upper electrode 113 form a capacitor stack layer 114 .

[0084] like Figure 5 As shown, an upper electrode 113 is formed on the dielectric layer 112, wherein the lower electrode 111, the dielectric layer 112 and the upper electrode 113 form a capacitor stacking layer 114. Of course, when multiple capacitors need to be constructed, multiple upper electrodes 113 can be formed.

[0085] S60 : forming a passivation layer 115 on the second electrode layer 109 , and the passivation layer 115 extends above the capacitor stack layer 114 .

[0086] like Figure 6 As shown, in Figure 5 A passivation layer 115 is deposited on the device to provide passivation protection. In order to facilitate the extraction of the required electrodes, a first extraction portion 116, a second extraction portion 117, a third extraction portion 123, a fourth extraction portion 124, a fifth extraction portion 119 and a sixth extraction portion 118 can be provided according to the requirements of the above-mentioned different resonators.

[0087] like Figure 7 As shown, a release hole connected to the sacrificial layer 102 is finally formed to form the first cavity 120 and / or the second cavity 122 .

[0088] It should be understood that the method for preparing a resonator can be used to prepare the aforementioned resonator.

[0089] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A resonator, characterized in that: It includes a substrate and a first electrode layer, a first piezoelectric layer and a second electrode layer stacked sequentially on the substrate, the first electrode layer, the first piezoelectric layer and the second electrode layer form a first overlapping area along the stacking direction, a capacitor stacking layer located outside the first overlapping area is arranged on the first piezoelectric layer, a passivation layer is arranged above the second electrode layer, and the passivation layer extends above the capacitor stacking layer.

2. The resonator according to claim 1, characterized in that The capacitor stack layer comprises a lower electrode, a dielectric layer and an upper electrode sequentially stacked on the first piezoelectric layer; The resonator further includes a first lead portion and a second lead portion, the first lead portion penetrates the passivation layer and contacts the lower electrode, the second lead portion penetrates the passivation layer and contacts the upper electrode, and the first lead portion and the second lead portion do not overlap in the stacking direction.

3. The resonator according to claim 2, characterized in that The lower electrode and the upper electrode have a second overlapping region in the stacking direction, and the first lead-out portion and the second lead-out portion are both located outside the second overlapping region.

4. The resonator according to claim 1, characterized in that The capacitor stacking layer includes multiple upper electrodes and a lower electrode and a dielectric layer stacked sequentially on the first piezoelectric layer. The multiple upper electrodes are arranged on the side of the dielectric layer away from the lower electrode, and the multiple upper electrodes are arranged at intervals from each other. The multiple upper electrodes cooperate with the lower electrodes to form multiple capacitors.

5. The resonator according to claim 4, characterized in that The resonator further includes a third lead-out portion and a plurality of fourth lead-out portions, wherein the third lead-out portion penetrates the passivation layer and contacts the lower electrode, and the plurality of fourth lead-out portions respectively penetrate the passivation layer and contact the plurality of upper electrodes one by one.

6. The resonator according to claim 4, characterized in that The resonator further includes a plurality of fourth lead-out portions, each of which penetrates through the passivation layer and contacts the plurality of upper electrodes one by one.

7. The resonator according to any one of claims 1 to 6, characterized in that An insulating layer is provided between the first piezoelectric layer and the capacitor stack layer; and / or, a mass load layer located in the first overlapping region is provided between the first piezoelectric layer and the second electrode layer; And / or, a second piezoelectric layer is arranged between the substrate and the first electrode layer.

8. The resonator according to any one of claims 1 to 6, characterized in that A first cavity and a second cavity are further provided between the substrate and the first piezoelectric layer. The first cavity is at least partially located in the first overlapping region, and the second cavity is located directly below the capacitor stack layer.

9. The resonator according to claim 8, characterized in that The second cavity is filled with an oxide layer.

10. A method for preparing a resonator, characterized in that: The method comprises: sequentially forming a stacked second piezoelectric layer, a first electrode layer and a first piezoelectric layer on a substrate; forming a mass loading layer on the first piezoelectric layer; forming a second electrode layer on the mass load layer and forming a lower electrode on the first piezoelectric layer, wherein the second electrode layer and the lower electrode are spaced apart; forming a dielectric layer on the lower electrode; forming at least one upper electrode on the dielectric layer, wherein the lower electrode, the dielectric layer and the at least one upper electrode form a capacitor stack layer; A passivation layer is formed on the second electrode layer, and the passivation layer extends above the capacitor stack layer.

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