Protection circuit for relieving negative capacitance effect, control method thereof and electronic equipment

Abstract

The invention relates to a protection circuit for relieving a negative capacitance effect and a control method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the circuit comprises a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor, the suppression circuit is configured as follows: the input end is connected with the second end of the first field effect transistor, the first output end is grounded, and the second output end is used for outputting a second electric signal with target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor; the second field effect transistor is configured as follows: the control end is used for connecting the second output end of the suppression circuit; and the adjusting assembly is connected with the suppression circuit and is used for adjusting the inductance value and / or capacitance value of the suppression circuit, so that the suppression circuit outputs a second electric signal with the target frequency. And the influence of an interference signal generated by a negative capacitance effect on a subsequent MOSFET is suppressed.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a negative capacitance effect protection circuit, a control method thereof, and an electronic device. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of the most widely used semiconductor devices. According to the type of conductive channel, it is mainly divided into N-type MOSFET (NMOS) and P-type MOSFET (PMOS). The PN junction is the most basic component and also the most important structure.

[0003] When the voltage across the junction changes, the amount of charge accumulated in the barrier region at the PN junction boundary changes, resulting in a capacitive effect. Typically, when a PN junction is reverse-biased, as the reverse voltage increases, the space charge region (depletion layer) widens, and the capacitance decreases. However, when the reverse voltage reaches a certain value, the capacitance actually begins to increase, exhibiting a "negative capacitance" effect. This causes voltage and current fluctuations in the circuit, impacting the MOSFET's switching speed, leading to signal transmission delays or distortion, and reducing circuit stability.

[0004] In summary, a reasonable design or optimization method is urgently needed to reduce the adverse effects of the negative capacitance effect and ensure the stability and reliability of the circuit. Summary of the Invention

[0005] Based on this, it is necessary to address the technical problems in the prior art and provide a negative capacitance effect protection circuit and its control method, as well as an electronic device, which can at least reduce the adverse effects of the negative capacitance effect on MOSFET devices.

[0006] In the first aspect, the present application provides a protection circuit for alleviating the negative capacitance effect, comprising: a first field effect transistor is configured as: a first end is used to connect to a DC power supply, and a second end is used to output a first electrical signal; a suppression circuit is configured as: an input end is connected to the second end of the first field effect transistor, a first output end is grounded, and a second output end is used to output a second electrical signal with a target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor; a second field effect transistor is configured as: a control end is used to connect to the second output end of the suppression circuit; an adjustment component is connected to the suppression circuit, for adjusting the inductance value and / or capacitance value of the suppression circuit, so that the suppression circuit outputs a second electrical signal with a target frequency.

[0007] In the protection circuit provided in the above embodiment, the first field-effect transistor is configured such that its first terminal is connected to a DC power supply and its second terminal is used to output a first electrical signal. The second field-effect transistor is configured such that its control terminal is connected to the second output terminal of the suppression circuit. Whether it is an NMOS or PMOS transistor, there are two back-to-back PN junctions between the first and second terminals. Regardless of the voltage polarity between the first and second terminals, one of the PN junctions is always in a reverse biased state. When the control terminal voltage is low, there is no conductive channel between the first and second terminals, and the device is non-conductive. When the control terminal voltage is high, a conductive channel is formed. Therefore, the frequency of the signal received by the control terminal directly affects its performance. However, the interference signal generated by the negative capacitance effect will mix with the useful signal, causing distortion of the first electrical signal output by the first field-effect transistor. The interference signal will reduce the interference signal of the second field-effect transistor, causing output signal distortion, reducing the signal-to-noise ratio, triggering parasitic effects, and potentially causing it to enter a nonlinear operating region, generating undesirable harmonics and intermodulation products.

[0008] The suppression circuit is configured as follows: an input terminal connected to the second terminal of a first field-effect transistor, a first output terminal connected to ground, and a second output terminal configured to output a second electrical signal having a target frequency; the target frequency is associated with the negative capacitance effect of the first field-effect transistor; and a regulating component connected to the suppression circuit. When the first electrical signal enters the suppression circuit, the regulating component adjusts the inductance and / or capacitance of the suppression circuit. Through the synergistic effect of the inductance and capacitance, a filtering effect is achieved on signals of a specific frequency within the first electrical signal, causing the suppression circuit to output the second electrical signal having the target frequency.

[0009] In some embodiments, the suppression circuit includes: a first inductive element, a capacitive element, and a second inductive element. The first inductive element is configured such that its first end constitutes an input of the suppression circuit and is connected to the second end of the first field-effect transistor; the capacitive element is configured such that its first end is connected to the second end of the first inductive element and its second end constitutes a first output of the suppression circuit; and the second inductive element is configured such that its first end is connected to the first end of the capacitive element and its second end constitutes a second output of the suppression circuit and is connected to the control end of the second field-effect transistor.

[0010] In some embodiments, the protection circuit also includes a bidirectional protection component, which is configured as follows: the first end is connected to the input end of the suppression circuit and the second end of the first field effect transistor, and the second end is connected to the second output end of the suppression circuit and the control end of the second field effect transistor, for performing bidirectional current limiting protection on the suppression circuit.

[0011] In some embodiments, the bidirectional protection component includes a first voltage-stabilizing diode and a second voltage-stabilizing diode; the cathode of the first voltage-stabilizing diode is connected to the cathode of the second voltage-stabilizing diode; the anode of the first voltage-stabilizing diode constitutes the first end of the bidirectional protection component, and the anode of the second voltage-stabilizing diode constitutes the second end of the bidirectional protection component; the breakdown voltage of the first voltage-stabilizing diode and the second voltage-stabilizing diode is less than the breakdown voltage of the first inductive element and the second inductive element.

[0012] In some embodiments, the conductive channel types of the first field effect transistor and the second field effect transistor are the same or different.

[0013] In some embodiments, the protection circuit further includes a first resistor, which is configured such that: a first end is connected to the second end of the first field effect transistor, and a second end is connected to the first end of the bidirectional protection component.

[0014] In some embodiments, the protection circuit further includes a second resistor, and the second resistor is configured such that: a first end is connected to the second end of the bidirectional protection component, and a second end is connected to the control end of the second field effect transistor.

[0015] In a second aspect, the present application also provides a protection circuit control method for alleviating the negative capacitance effect. The protection circuit for alleviating the negative capacitance effect includes a first field effect transistor, a suppression circuit, a second field effect transistor, and a regulating component. The first field effect transistor is configured as follows: the first end is used to connect to a DC power supply, and the second end is used to output a first electrical signal; the suppression circuit is configured as follows: the input end is connected to the second end of the first field effect transistor, and the first output end is grounded; the second field effect transistor is configured as follows: the control end is used to connect to the second output end of the suppression circuit; the regulating component is connected to the suppression circuit; the method includes:

[0016] The inductance and / or capacitance of the suppression circuit are adjusted so that the suppression circuit outputs a second electrical signal having a target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor.

[0017] Introducing a suppression circuit between the first and second FETs effectively eliminates interference signals generated by the negative capacitance effect of the first FET, improving the purity and accuracy of the output signal and reducing interference with the second FET, thereby ensuring proper circuit operation. This method enhances circuit stability and is suitable for applications requiring high signal output quality and stability.

[0018] In some embodiments, the suppression circuit includes a first inductive element, a capacitive element, and a second inductive element. The first inductive element is configured such that: a first end constitutes an input end of the suppression circuit and is connected to the second end of the first field-effect transistor; the capacitive element is configured such that: a first end is connected to the second end of the first inductive element, and a second end constitutes a first output end of the suppression circuit; the second inductive element is configured such that: a first end is connected to the first end of the capacitive element, and a second end constitutes a second output end of the suppression circuit and is connected to the control end of the second field-effect transistor;

[0019] Adjust the inductance and / or capacitance of the suppression circuit, including:

[0020] The inductance value of the first inductive element / the second inductive element is adjusted, and / or the capacitance value of the capacitive element is adjusted.

[0021] In a third aspect, the present application also provides an electronic device, comprising any of the above protection circuits or a protection circuit controlled by any of the above protection circuit control methods for alleviating the negative capacitance effect.

[0022] This electronic device effectively avoids the subsequent impact of interference signals generated by the negative capacitance effect of the PN junction on the device by introducing a protection circuit with a suppression circuit and a bidirectional protection component. In the protection circuit, by adjusting the inductance value of the first inductive element / second inductive element and the capacitance value of the capacitive element, the passage of signals of a specific frequency is restricted, thereby achieving the purpose of filtering out interference signals. A bidirectional protection component is connected in parallel at both ends of the suppression circuit to prevent the voltage step caused by the negative capacitance effect or the transient current in the pulse response time domain from being too large, which would burn out the first inductive element / second inductive element in the suppression circuit. This protection circuit control method for alleviating the negative capacitance effect ensures the stable operation of the electronic device. It can be widely used in power discrete devices, power management chips, mixed signal chips, image sensors, RF chips, microcontrollers and other fields. The introduction of this protection circuit and control method for alleviating the negative capacitance effect can enhance the competitiveness of the company's products and further expand the company's technological leadership and brand influence.

[0023] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1a This is an example diagram of the structure of a PN junction;

[0026] Figure 1b This is an example diagram of the energy band of a PN junction;

[0027] Figure 2 Schematic diagram of the circuit principle of a protection circuit for alleviating negative capacitance effect provided in one embodiment;

[0028] Figure 3 1 is a circuit diagram of a protection circuit for alleviating negative capacitance effect provided in one embodiment;

[0029] Figure 4 Schematic diagram of a circuit scenario of a protection circuit for alleviating negative capacitance effect provided in one embodiment.

[0030] Description of reference numerals:

[0031] 20. First field effect transistor; 30. Suppression circuit; 31. First inductive element; 32. Capacitive element; 33. Second inductive element; 40. Bidirectional protection component; 41. First Zener diode; 42. Second Zener diode. DETAILED DESCRIPTION

[0032] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0034] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0035] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0036] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0037] In the basic unit of PN junction, when P-type semiconductor and N-type semiconductor are combined, due to the difference in carrier concentration, the electrons in N-type semiconductor will diffuse into the low-concentration P-type semiconductor, and the holes in P-type semiconductor will diffuse into the low-concentration N-type semiconductor, leaving a gap on both sides of the interface. Figure 1a The thin ion layer is the space charge region. The direction of the built-in electric field is the same as the direction of the diffusion current. This process eventually reaches a dynamic equilibrium. When a reverse bias is applied to the PN junction, the built-in electric field is enhanced, the barrier that hinders carrier diffusion becomes higher, and the space charge region becomes wider, resulting in the following: Figure 1b At this time, when the reverse bias voltage is too large, the PN junction produces the negative capacitance effect as described above.

[0038] In the prior art, the capacitance of the PN junction is usually adjusted by controlling the area and thickness of the PN junction. However, this will sacrifice the current handling capability of the PN junction or increase resistance and reduce response speed.

[0039] Therefore, this application incorporates a suppression circuit between the two MOSFETs. When the PN junction generates a negative capacitance effect, the suppression circuit adjusts the values ​​of the inductor and capacitor to allow only signals of a specific frequency to pass through the circuit, suppressing the interference signal generated by the negative capacitance effect. At the same time, a bidirectional protection component is introduced to prevent excessive transient current from burning out the corresponding components within the suppression circuit when a voltage step or pulse response is generated by the negative capacitance effect.

[0040] In order to illustrate the above technical solutions of the present application, specific embodiments are provided below.

[0041] See also Figure 2In some embodiments of the present application, a protection circuit for mitigating the negative capacitance effect is provided, comprising: a first field effect transistor 20 configured as: a first end for connecting to a DC power supply, and a second end for outputting a first electrical signal; a suppression circuit 30 configured as: an input end connected to the second end of the first field effect transistor 20, a first output end grounded, and a second output end for outputting a second electrical signal having a target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor 20; a second field effect transistor 50 configured as: a control end for connecting to the second output end of the suppression circuit 30; and an adjustment component connected to the suppression circuit 30, for adjusting the inductance value and / or capacitance value of the suppression circuit 30, so that the suppression circuit 30 outputs the second electrical signal having the target frequency.

[0042] See also Figure 3 In some embodiments, the suppression circuit 30 includes a first inductive element 31, a capacitive element 32, and a second inductive element 33. The first inductive element 31 is configured such that its first end constitutes the input of the suppression circuit 30 and is connected to the second end of the first field-effect transistor 20. The capacitive element 32 is configured such that its first end is connected to the second end of the first inductive element 31 and its second end constitutes the first output of the suppression circuit 30. The second inductive element 33 is configured such that its first end is connected to the first end of the capacitive element 32 and its second end constitutes the second output of the suppression circuit 30 and is connected to the control end of the second field-effect transistor 50.

[0043] Please continue reading Figure 3 In some embodiments, the protection circuit further includes a bidirectional protection component 40, which is configured as follows: a first end connected to the input end of the suppression circuit 30 and the second end of the first field effect transistor 20, and a second end connected to the second output end of the suppression circuit 30 and the control end of the second field effect transistor 50, for performing bidirectional current limiting protection on the suppression circuit 30.

[0044] In the protection circuit provided in the above embodiment, the first field-effect transistor 20 is configured such that its first terminal is connected to a DC power supply and its second terminal is configured to output a first electrical signal. The second field-effect transistor 50 is configured such that its control terminal is connected to the second output terminal of the suppression circuit 30. The suppression circuit 30 is configured such that its input terminal is connected to the second terminal of the first field-effect transistor 20, its first output terminal is connected to ground, and its second output terminal is configured to output a second electrical signal having a target frequency; the target frequency is related to the negative capacitance effect of the first field-effect transistor 20. A regulating component is connected to the suppression circuit 30.

[0045] For example, see Figure 3When the first electrical signal enters the suppression circuit 30, it is mixed with interference signals generated by the negative capacitance effect of the first field-effect transistor 20. The inductance and reactance of the first and second inductive elements 31 and 33 are proportional to the signal frequency; that is, the higher the frequency, the greater the impedance, making it difficult for high-frequency signals to pass through. Conversely, the capacitance and reactance of the capacitive element 32 are inversely proportional to the signal frequency, the opposite of the inductive element. The adjustment component adjusts the inductance values ​​of the first and second inductive elements 31 and 33 and / or the capacitance value of the capacitive element 32 of the suppression circuit 30 to selectively filter the first electrical signal, improving signal distortion. This allows the suppression circuit 30 to output a second electrical signal at the target frequency, improving the purity and accuracy of the output signal and reducing interference with the second field-effect transistor.

[0046] For example, when designing an LC filter, in addition to determining the values ​​of the inductive and capacitive components based on the desired signal frequency range and input signal waveform, various factors should be considered, including impedance matching, stability, cost, and volume, to ensure optimal overall circuit performance. Only in this way can we better meet actual application needs and improve product quality and competitiveness.

[0047] Please continue reading Figure 3 In some embodiments, the bidirectional protection component 40 includes a first Zener diode 41 and a second Zener diode 42; the cathode of the first Zener diode 41 is connected to the cathode of the second Zener diode 42; the anode of the first Zener diode 41 constitutes the first end of the bidirectional protection component 40, and the anode of the second Zener diode 42 constitutes the second end of the bidirectional protection component 40; the breakdown voltage of the first Zener diode 41 and the second Zener diode 42 is less than the breakdown voltage of the first inductive element 31 and the second inductive element 33.

[0048] Please continue reading Figure 3 In some embodiments, the anode of the first Zener diode 41 constitutes the first end of the bidirectional protection component 40, and the anode of the second Zener diode 42 constitutes the second end of the bidirectional protection component 40; the bidirectional protection component 40 is configured as follows: the first end is connected to the input end of the suppression circuit 30 and the second end of the first field effect transistor 20, and the second end is connected to the second output end of the suppression circuit 30 and the control end of the second field effect transistor 50.

[0049] For example, the anode of the first Zener diode 41 constitutes the first terminal of the bidirectional protection component 40, and the first terminal is connected to the input terminal of the suppression circuit 30 and the second terminal of the first field-effect transistor 20. The anode of the second Zener diode 42 constitutes the second terminal of the bidirectional protection component 40, and the second terminal is connected to the second output terminal of the suppression circuit 30 and the control terminal of the second field-effect transistor 50. The first Zener diode 41 and the second Zener diode 42 are connected in anti-series connection.

[0050] Under normal circumstances, one Zener diode in the bidirectional protection component 40 is always turned on and the other is turned off. Currents less than the preset value will only flow through the suppression circuit 30, and the bidirectional protection component 40 will not affect its normal filtering function. When the PN junction in the first field-effect transistor 20 generates a time-domain transient current with a voltage step or pulse response due to the negative capacitance effect, the Zener diode has a slightly lower breakdown voltage than the first inductive element 31 and the second inductive element 33, so the Zener diode breaks down first and turns on. At this time, the excessive time-domain transient current flows through the bidirectional protection component 40 instead of the inductive elements, effectively preventing the first inductive element 31 and the second inductive element 33 from being burned by the instantaneous excessive current.

[0051] See also Figure 4 The conductive channel types of the first field effect transistor 20 and the second field effect transistor 50 are the same or different.

[0052] For example, the second field-effect transistor 50 can be either a PMOS or an NMOS. Regardless of whether the first field-effect transistor 20 is an NMOS or a PMOS, there are two back-to-back PN junctions between the first and second terminals. Regardless of the voltage polarity between the first and second terminals, one of the PN junctions is always in a reverse biased state. Therefore, there is always a risk of generating a negative capacitance effect. When the first field-effect transistor 20 is a PMOS, the source terminal is the first terminal in this application, and the drain terminal is the second terminal in this application. When the first field-effect transistor 20 is an NMOS, the drain terminal is the first terminal in this application, and the source terminal is the second terminal in this application.

[0053] For example, the protection circuit, starting with the first field-effect transistor, further includes a first conductive plug, a first metal conductive layer, a metal wire, a second metal conductive layer, and a second conductive plug. The first conductive plug is configured such that its first end is connected to the second end of the first field-effect transistor 20 and its second end is connected to the first metal conductive layer. The second conductive plug is configured such that its first end is connected to the control terminal of the second field-effect transistor 50 and its second end is connected to the second conductive metal layer.

[0054] For example, the materials of the first conductive plug, the first metal conductive layer, the metal wire, the second metal conductive layer, and the second conductive plug include but are not limited to gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), and other metal materials or any combination thereof.

[0055] In some embodiments, the protection circuit further includes a first resistor (not shown), which is configured such that: a first end is connected to the second end of the first field effect transistor 20 , and a second end is connected to the first end of the bidirectional protection component 40 .

[0056] In some embodiments, the protection circuit further includes a second resistor (not shown), which is configured such that: a first end is connected to the second end of the bidirectional protection component 40 , and a second end is connected to the control end of the second field effect transistor 50 .

[0057] For example, when the bidirectional protection component 40 is turned on, the instantaneous current flowing through the first resistor / the second resistor is limited and reduced, thereby preventing excessive heat in the circuit from causing component overload or burnout.

[0058] Please continue reading Figure 3 In some embodiments, the present application further provides a method for controlling a protection circuit for mitigating a negative capacitance effect. The protection circuit for mitigating a negative capacitance effect includes a first field effect transistor 20, a suppression circuit 30, a second field effect transistor 50, and a regulating component. The first field effect transistor 20 is configured such that: a first end is connected to a DC power supply, and a second end is used to output a first electrical signal; the suppression circuit 30 is configured such that: an input end is connected to the second end of the first field effect transistor 20, and a first output end is grounded; the second field effect transistor 50 is configured such that: a control end is connected to the second output end of the suppression circuit 30; the regulating component is connected to the suppression circuit 30; the method includes:

[0059] The inductance and / or capacitance of the suppression circuit 30 is adjusted so that the suppression circuit 30 outputs a second electrical signal having a target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor 20 .

[0060] Please continue reading Figure 3 The suppression circuit 30 includes a first inductive element 31, a capacitive element 32, and a second inductive element 33. The first inductive element 31 is configured such that its first end constitutes the input end of the suppression circuit 30 and is connected to the second end of the first field effect transistor 20. The capacitive element 32 is configured such that its first end is connected to the second end of the first inductive element 31, and its second end constitutes the first output end of the suppression circuit 30. The second inductive element 33 is configured such that its first end is connected to the first end of the capacitive element 32, and its second end constitutes the second output end of the suppression circuit 30 and is connected to the control end of the second field effect transistor.

[0061] Adjusting the inductance and / or capacitance of the suppression circuit 30 includes:

[0062] The inductance of the first inductive element 31 / the second inductive element 33 is adjusted, and / or the capacitance of the capacitive element 32 is adjusted.

[0063] The effect of the protection circuit controlled by the control method is consistent with that described above and will not be elaborated here.

[0064] In a third aspect, the present application also provides an electronic device, comprising any of the above protection circuits or a protection circuit controlled by any of the above protection circuit control methods for alleviating the negative capacitance effect.

[0065] The protection circuit and control method thereof, and the electronic device for alleviating the negative capacitance effect in the embodiments of the present application have the following unexpected technical effects:

[0066] By adjusting the inductance of the first and second inductive elements, as well as the capacitance of the capacitive element, in the suppression circuit, this protection circuit effectively limits the transmission of signals at specific frequencies, eliminating interference signals generated by the negative capacitance effect of field-effect transistors (FETs), ensuring the purity and accuracy of the output signal, reducing interference with subsequent components, ensuring normal circuit operation, and enhancing circuit stability. This design principle, based on the theory of signal filtering and interference suppression, achieves selective transmission of signals at specific frequencies through the synergistic effect of inductance and capacitance, thereby improving signal quality and stability.

[0067] In addition, the use of parallel bidirectional protection components at both ends of the suppression circuit can effectively prevent the voltage step caused by the negative capacitance effect or the excessive transient current in the pulse response time domain, avoiding damage to the first inductive element and the second inductive element in the suppression circuit, and ensuring the stability and reliability of the suppression circuit when facing sudden voltage changes caused by the negative capacitance effect.

[0068] Based on the theoretical description above, this protection circuit design combines the principles of signal filtering, interference suppression, and circuit protection to improve signal quality while ensuring the reliable operation of the entire circuit system, demonstrating its superior performance and reliability in demanding environments. This protection circuit is suitable for power discrete devices, power management chips, mixed-signal chips, image sensors, RF chips, microcontrollers, and other fields. It lays a solid foundation for further technological innovation and market expansion, enhancing the company's product competitiveness and expanding its technological leadership and brand influence.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0070] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A protection circuit for alleviating negative capacitance effect, characterized in that: include: A first field effect transistor is configured such that: a first end is used for connecting to a DC power supply, and a second end is used for outputting a first electrical signal; The suppression circuit is configured as follows: an input end is connected to the second end of the first field effect transistor, a first output end is grounded, and a second output end is used to output a second electrical signal with a target frequency; The target frequency is associated with the negative capacitance effect of the first field effect transistor; The second field effect transistor is configured as follows: a control end is used to connect the second output end of the suppression circuit; The regulating component is connected to the suppression circuit and is used to adjust the inductance value and / or capacitance value of the suppression circuit so that the suppression circuit outputs a second electrical signal with a target frequency.

2. The protection circuit according to claim 1, characterized in that: The suppression circuit comprises: A first inductive element is configured as follows: a first end constituting an input end of the suppression circuit and connected to a second end of the first field effect transistor; a capacitive element, configured such that: a first end is connected to a second end of the first inductive element, and a second end constitutes a first output end of the suppression circuit; The second inductive element is configured as follows: a first end is connected to the first end of the capacitive element, and a second end constitutes a second output end of the suppression circuit and is connected to the control end of the second field effect transistor.

3. The protection circuit according to claim 2, characterized in that: Also includes: The bidirectional protection component is configured as follows: the first end is connected to the input end of the suppression circuit and the second end of the first field effect transistor, and the second end is connected to the second output end of the suppression circuit and the control end of the second field effect transistor, for performing bidirectional current limiting protection on the suppression circuit.

4. The protection circuit according to claim 3, characterized in that: The bidirectional protection component includes a first voltage stabilizing diode and a second voltage stabilizing diode; The cathode of the first voltage zener diode is connected to the cathode of the second voltage zener diode; The anode of the first voltage stabilizing diode constitutes the first end of the bidirectional protection component, and the anode of the second voltage stabilizing diode constitutes the second end of the bidirectional protection component; The breakdown voltages of the first Zener diode and the second Zener diode are smaller than the breakdown voltages of the first inductive element and the second inductive element.

5. The protection circuit according to claim 1, characterized in that: The conductive channel types of the first field effect transistor and the second field effect transistor are the same or different.

6. The protection circuit according to any one of claims 1 to 5, characterized in that: Also included is a resistor, the resistor comprising at least one of the following features, A first resistor, configured to: have a first end connected to the second end of the first field effect transistor, and a second end connected to the first end of the bidirectional protection component; The second resistor is configured as follows: a first end is connected to the second end of the bidirectional protection component, and a second end is connected to the control end of the second field effect transistor.

7. A protection circuit control method for alleviating negative capacitance effect, characterized in that: The protection circuit for alleviating the negative capacitance effect comprises a first field effect transistor, a suppression circuit, a second field effect transistor and a regulating component, wherein the first field effect transistor is configured as follows: a first end is used to connect a DC power supply, and a second end is used to output a first electrical signal; the suppression circuit is configured as follows: an input end is connected to the second end of the first field effect transistor, and a first output end is grounded; the second field effect transistor is configured as follows: a control end is used to connect the second output end of the suppression circuit; the regulating component is connected to the suppression circuit; the method comprises: The inductance value and / or the capacitance value of the suppression circuit are adjusted so that the suppression circuit outputs a second electrical signal having a target frequency; the target frequency is associated with the negative capacitance effect of the first field effect transistor.

8. The control method according to claim 7, characterized in that: The suppression circuit includes a first inductive element, a capacitive element and a second inductive element. The first inductive element is configured as follows: a first end of the first inductive element constitutes an input end of the suppression circuit and is connected to a second end of the first field effect tube; the capacitive element is configured as follows: a first end of the first inductive element is connected to a second end of the first inductive element, and a second end of the second inductive element constitutes a first output end of the suppression circuit; the second inductive element is configured as follows: a first end of the first inductive element is connected to a first end of the capacitive element, and a second end of the second inductive element constitutes a second output end of the suppression circuit and is connected to a control end of the second field effect tube; The adjusting the inductance value and / or capacitance value of the suppression circuit comprises: Adjusting the inductance of the first inductive element / the second inductive element, and / or The capacitance value of the capacitive element is adjusted.

9. The control method according to claim 7, characterized in that: The protection circuit for mitigating the negative capacitance effect further includes a bidirectional protection component, wherein the bidirectional protection component is configured as follows: a first end is connected to an input end of the suppression circuit and a second end of the first field effect transistor, and a second end is connected to a second output end of the suppression circuit and a control end of the second field effect transistor; the method includes: The bidirectional protection component shunts the time-domain transient current on the suppression circuit; the time-domain transient current is caused by a voltage step or pulse response generated by a negative capacitance effect.

10. An electronic device, characterized in that: A protection circuit comprising any one of claims 1 to 6; or A protection circuit controlled by the protection circuit control method for alleviating negative capacitance effect as described in any one of claims 7 to 9.

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