Sampling delay dynamic adjustment method, terminal equipment and storage medium

Abstract

The invention relates to the technical field of delay configuration, and discloses a sampling delay dynamic adjustment method, terminal equipment and a storage medium, and the sampling delay dynamic adjustment method comprises the steps: receiving a plurality of test messages sent by a second chip based on the initial delay time of a first chip, and recording the wrong receiving times of all test messages; judging whether to reconfigure the sampling time of the first chip or not according to the wrong receiving times; if the sampling time is reconfigured, receiving the plurality of test messages sent by the second chip again based on the current preset delay time, and recording the current wrong receiving times; and judging whether the current preset delay time meets a preset condition or not according to the current wrong receiving times, and adjusting the current preset delay time to the optimal delay time of the first chip when the current preset delay time meets the preset condition. According to the sampling delay dynamic adjustment method, the optimal delay time of the RGMII port is dynamically adjusted under the condition that adverse influence factors change, and the purpose that the RGMII port can continuously and stably work is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of delay configuration, and in particular to a sampling delay dynamic adjustment method, a terminal device and a storage medium. Background Art

[0002] The RGMII interface is an Ethernet circuit interface between the CPU chip and the PHY chip. Considering that there is always jitter on the rising and falling edges of the clock and data levels in electronic circuits, in practice, the CPU chip and the PHY chip delay the RGMII interface sampling time. Due to changes in environmental temperature, humidity, electromagnetic interference, aging of electronic devices, power supply fluctuations and other factors, the jitter characteristics of the rising and falling edges of the level will be affected. The best delayed sampling time in a certain period will become unstable under the influence of various changing factors. Therefore, whether it is the default delayed sampling time or the measurement method to find the best delayed sampling time in a certain period, it cannot guarantee that the RGMII interface will work continuously and stably under all-weather conditions throughout the year. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a method for dynamically adjusting a sampling delay, a terminal device, and a storage medium to dynamically adjust the optimal delay time of the RGMII interface.

[0004] In a first aspect, an embodiment of the present application provides a method for dynamically adjusting a sampling delay, the method comprising:

[0005] receiving a plurality of test messages sent by the second chip based on the initial delay time configured for the first chip, and recording the number of erroneous receptions of all the test messages according to the reception result of each of the test messages;

[0006] Determining whether to reconfigure the sampling time of the first chip according to the number of erroneous receptions;

[0007] If the sampling time is reconfigured, the multiple test messages sent by the second chip are received again based on the current preset delay time;

[0008] According to the reception result of each of the test messages based on the current preset delay time, record the current number of erroneous receptions;

[0009] According to the current number of erroneous receptions, it is determined whether the current preset delay time satisfies a preset condition, and if so, it is adjusted to be the optimal delay time of the first chip.

[0010] In a first possible embodiment of the first aspect, the method for dynamically adjusting the sampling delay further includes:

[0011] If the current preset delay time does not meet the preset condition, the multiple test messages are received again based on the next preset delay time until the optimal delay time is determined.

[0012] In a second possible embodiment of the first aspect, the test message includes a source address, a destination address, a message type, and test data, and data bits of the test data are expressed as high-low alternating transitions.

[0013] In a third possible embodiment of the first aspect, recording, according to a reception result of each of the test messages, a number of erroneous receptions of all the test messages includes:

[0014] Calculating a first check value according to the test data in the test message, and comparing the calculated first check value with a second check value carried in the test message to determine whether the test message is correctly received;

[0015] The test messages that are erroneously received are counted to determine the number of erroneous receptions.

[0016] In a fourth possible embodiment of the first aspect, judging whether to reconfigure the sampling time of the first chip according to the number of erroneous reception times includes:

[0017] If the number of erroneous receptions is greater than zero, determining to reconfigure the sampling time;

[0018] If the number of erroneous reception times is equal to zero, it is determined that there is no need to reconfigure the sampling time.

[0019] In a fifth possible embodiment of the first aspect, judging, according to the current number of erroneous receptions, whether the current preset delay time satisfies a preset condition includes:

[0020] If the number of erroneous receptions is greater than zero, it is determined that the current preset delay time does not meet the preset condition;

[0021] If the number of erroneous reception times is equal to zero, it is determined that the current preset delay time meets the preset condition, and the current preset delay time is used as the optimal delay time.

[0022] In a sixth possible embodiment of the first aspect, when the system clock is 125Mhz, the preset delay time has a value range of 0.5ns-3.5ns.

[0023] In a sixth possible embodiment of the first aspect, when the first chip is a CPU chip, the second chip is a PHY chip;

[0024] When the first chip is a PHY chip, the second chip is a CPU chip.

[0025] In a second aspect, an embodiment of the present application provides a terminal device, the terminal device comprising a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement the above-mentioned method for dynamic adjustment of sampling delay.

[0026] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which, when executed on a processor, implements any of the above-mentioned methods for dynamically adjusting the sampling delay.

[0027] The embodiments of the present application have the following beneficial effects:

[0028] The dynamic adjustment method of the sampling delay of the present embodiment includes: receiving multiple test messages sent by the second chip based on the initial delay time configured by the first chip, and recording the number of erroneous receptions of all test messages according to the reception result of each test message; judging whether to reconfigure the sampling time of the first chip according to the number of erroneous receptions; if the sampling time is reconfigured, re-receiving multiple test messages sent by the second chip based on the current preset delay time; recording the current number of erroneous receptions according to the reception result of each test message based on the current preset delay time; judging whether the current preset delay time meets the preset conditions according to the current number of erroneous receptions, and adjusting it to the optimal delay time of the first chip when it meets the conditions. The present application realizes real-time monitoring of the working status of the RGMII port, so as to adjust the optimal delay time parameters of the RGMII port accordingly when various factors such as ambient temperature, humidity, electromagnetic interference, aging of electronic devices themselves, power supply fluctuations, etc. change, while maintaining the normal operation of the CPU chip and the PHY chip, so as to achieve the purpose of the RGMII port being able to work stably all year round and in all weather conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A first flow chart of the method for dynamically adjusting sampling delay in an embodiment of the present application is shown;

[0031] Figure 2 A second flow chart of the method for dynamically adjusting sampling delay according to an embodiment of the present application is shown;

[0032] Figure 3 A third flow chart of the method for dynamically adjusting sampling delay in an embodiment of the present application is shown;

[0033] Figure 4 A fourth flow chart of the method for dynamically adjusting sampling delay according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0035] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0036] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0037] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. Terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0038] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] Figure 1 A flow chart of a method for dynamically adjusting a sampling delay according to an embodiment of the present application is shown. Exemplarily, the method for dynamically adjusting a sampling delay includes the following steps:

[0040] S110: receiving a plurality of test messages sent by the second chip based on the initial delay time configured for the first chip, and recording the number of erroneous receptions of all the test messages according to a reception result of each of the test messages.

[0041] In one embodiment, the test message includes a source address, a destination address, a message type, and test data, and the data bits of the test data are displayed as high-low alternating transitions.

[0042] Specifically, the source address is the media access control address (MAC address) of the sender of the test message, which includes six bytes and is actually the MAC address of the second chip. The destination address is the MAC address of the receiver of the test message, and the message type is the type of the test message. The message type includes two bytes to distinguish the test message from other data messages. For example, the value of the message type can be 0xAA55. The test data is 64 bytes of test data, and the value of each byte is hexadecimal 0xF0 (i.e. binary 11110000B). Because the RGMII interface transmits 4 bits of data (data composed of binary bits) each time, the setting of the test data can allow the four-bit data interface of RGMII to alternately transmit 1111-0000-1111-0000, so that the level of the four-bit data interface of RGMII can always jump from high to low to high to low when the data is sampled twice adjacently.

[0043] It can be understood that the RGMII interface transmits test data with frequent high and low transitions in the data bits, which is most likely to cause sampling errors in the first chip due to abnormal jitter on the rising and falling edges of the electrical level. Therefore, if the first chip samples multiple test messages without errors, then it can be assumed that the first chip will not make any errors in receiving other messages.

[0044] Exemplarily, the first chip calculates a first check value of the received message data and compares it with a second check value carried in the message. If the two are equal, it is determined that the first chip has correctly received the test message; if the two are not equal, it is determined that the first chip has received the test message incorrectly.

[0045] For example, in one embodiment, Figure 2 As shown, the sampling delay dynamic adjustment method records the number of erroneous receptions of all test messages according to the reception result of each test message, including:

[0046] S111: Calculate a first check value according to the test data in the test message, and compare the calculated first check value with a second check value carried in the test message to determine whether the test message is correctly received.

[0047] S112: Count the erroneously received test messages to determine the number of erroneous receptions.

[0048] Optionally, there is a counting register in the first chip for recording errors in receiving test messages. Each time a message with a data error is received, the count is increased by one. The number of erroneous receptions can be obtained by receiving the value of the counting register. The sampling delay dynamic adjustment method detects possible errors in the transmission of test messages through a cyclic redundancy check (CRC). The CRC check is implemented by calculating the agreed relationship between the data bits and the check bits to ensure the integrity and accuracy of the test message. The second chip uses a specific polynomial to calculate the test data, and attaches the calculation result (i.e., the second check value) to the test data and sends it out. After receiving the test data, the first chip uses the same polynomial for calculation, and compares the calculation result with the first check value sent. If the two are equal, it indicates that the test data has not been tampered with during the transmission process, thereby verifying the integrity and correctness of the test message.

[0049] S120: Determine whether to reconfigure the sampling time of the first chip according to the number of erroneous receptions.

[0050] For example, if the number of error receptions is zero, it proves that the first chip can correctly sample the data message based on the initial delay time, and the initial delay time is used as the current optimal delay time for the first chip. If the number of errors is greater than zero, it means that the first chip cannot correctly sample the data message based on the initial delay time, and the first chip needs to reconfigure its own sampling time.

[0051] For example, in one embodiment, the sampling time dynamic adjustment method determines whether to reconfigure the sampling time of the first chip based on the number of erroneous reception times, including: if the number of erroneous reception times is greater than zero, then determining to reconfigure the sampling time; if the number of erroneous reception times is equal to zero, then determining that there is no need to reconfigure the sampling time.

[0052] S130: If the sampling time is reconfigured, a plurality of test messages sent by the second chip are received again based on the current preset delay time.

[0053] Optionally, when the system clock is 125Mhz, the preset delay time ranges from 0.5ns to 3.5ns. For example, the first chip can sequentially set the preset delay time to 0.5ns, 1ns, 1.5ns, 2ns, 2.5ns, 3ns, and 3.5ns.

[0054] S140: Record the current number of erroneous receptions according to the reception result of each test message based on the current preset delay time;

[0055] S150: judging whether the current preset delay time satisfies a preset condition according to the current number of erroneous receptions, and adjusting the current preset delay time to the optimal delay time of the first chip if the preset condition is satisfied.

[0056] Exemplarily, the first chip records the increasing number of erroneous reception test messages under each configured preset delay time, and selects the preset delay time corresponding to zero error increasing number as its own optimal delay time.

[0057] For example, in one embodiment, the sampling time dynamic adjustment method determines whether the current preset delay time meets the preset conditions based on the current number of erroneous receptions, including the following steps: if the number of erroneous receptions is greater than zero, it is determined that the current preset delay time does not meet the preset conditions; if the number of erroneous receptions is equal to zero, it is determined that the current preset delay time meets the preset conditions, and the current preset delay time is used as the optimal delay time.

[0058] Exemplarily, when the first chip determines that the current preset delay time does not meet the preset conditions, the first chip configures the next preset delay time and continues to receive multiple test messages until the number of erroneous reception of the test message is zero, and then uses the next preset delay time as its own optimal delay time.

[0059] For example, in one embodiment, the method for dynamically adjusting the sampling delay further includes: if the current preset delay time does not meet the preset condition, re-receiving multiple test messages based on the next preset delay time until the optimal delay time is determined.

[0060] Specifically, if the first chip determines the current optimal sampling time, the second chip continues to send test messages, the first chip continues to receive data messages, and continues to count the number of erroneous receptions of data messages. Once the environmental interference factors change and cause abnormal data sampling of the RGMII interface, and the number of errors increases to non-zero, the first chip reconfigures its own sampling time and tries to find a new optimal delay time.

[0061] Exemplary, such as Figure 3 As shown, when the first chip is a CPU chip and the second chip is a PHY chip, the method for dynamically adjusting the sampling delay includes the following steps:

[0062] S210: receiving a plurality of test messages sent by the PHY chip based on the initial delay time configured for the CPU chip, and recording the number of erroneous receptions of all the test messages according to the reception result of each test message.

[0063] S220: Determine whether to reconfigure the sampling time of the CPU chip according to the number of erroneous receptions.

[0064] S230: If the sampling time is reconfigured, multiple test messages sent by the PHY chip are received again based on the current preset delay time.

[0065] S240: Record the current number of erroneous receptions according to the reception result of each test message based on the current preset delay time.

[0066] S250: judging whether the current preset delay time satisfies a preset condition according to the current number of erroneous receptions, and adjusting the delay time to the optimal delay time of the CPU chip if the condition is satisfied.

[0067] It can be understood that the sampling delay dynamic adjustment method of the above embodiment is applicable to the CPU chip. The CPU chip can determine whether there is an error in the sampling data based on the current sampling delay by continuously receiving multiple test messages sent by the PHY chip. If it is determined that there is a data sampling error, different preset delay times are configured in turn. Under each configuration, the PHY chip sends multiple test messages. At the same time, the number of increases in technical test message errors under each configuration is measured, and the preset delay time corresponding to the number of errors increasing to zero is selected as its own optimal delay time.

[0068] Exemplary, such as Figure 4 As shown, when the first chip is a PHY chip and the second chip is a CPU chip, the method for dynamically adjusting the sampling delay includes the following steps:

[0069] S310: receiving a plurality of test messages sent by the CPU chip based on the initial delay time configured for the PHY chip, and recording the number of erroneous receptions of all the test messages according to the reception result of each test message.

[0070] S320: Determine whether to reconfigure the sampling time of the PHY chip according to the number of erroneous receptions.

[0071] S330: If the sampling time is reconfigured, multiple test messages sent by the CPU chip are received again based on the current preset delay time.

[0072] S340: Record the current number of erroneous receptions according to the reception result of each test message based on the current preset delay time.

[0073] S350: judging whether the current preset delay time satisfies a preset condition according to the current number of erroneous receptions, and adjusting the delay time to the optimal delay time of the PHY chip if the condition is satisfied.

[0074] It can be understood that the sampling delay dynamic adjustment method of the above-mentioned embodiment is applicable to the PHY chip. The PHY chip can determine whether there is an error in the sampling data based on the current sampling delay by continuously receiving multiple test messages sent by the CPU chip. If it is determined that there is a data sampling error, different preset delay times are configured in turn. Under each configuration, multiple test messages are received from the CPU chip, and the number of test message errors is counted under each configuration. The preset delay time corresponding to the error growth number of zero is selected as its own optimal delay time.

[0075] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program, thereby enabling the terminal device to execute the above-mentioned dynamic adjustment method of sampling delay.

[0076] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a CPU chip (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU) and a network processor (Network Processor, NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0077] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Among them, the memory is used to store a computer program, and the processor can execute the computer program accordingly after receiving an execution instruction.

[0078] The present application also provides a computer-readable storage medium for storing a computer program used in the above-mentioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0079] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are merely schematic, for example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and a module, a program segment or a part of a code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0080] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0081] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-receivable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of each embodiment of the present application.

[0082] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A method for dynamically adjusting sampling delay, characterized in that: The method comprises: receiving a plurality of test messages sent by the second chip based on the initial delay time configured for the first chip, and recording the number of erroneous receptions of all the test messages according to the reception result of each of the test messages; Determining whether to reconfigure the sampling time of the first chip according to the number of erroneous receptions; If the sampling time is reconfigured, the multiple test messages sent by the second chip are received again based on the current preset delay time; According to the reception result of each of the test messages based on the current preset delay time, record the current number of erroneous receptions; According to the current number of erroneous receptions, it is determined whether the current preset delay time satisfies a preset condition, and if so, it is adjusted to be the optimal delay time of the first chip.

2. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: Also includes: If the current preset delay time does not meet the preset condition, the multiple test messages are received again based on the next preset delay time until the optimal delay time is determined.

3. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: The test message includes a source address, a destination address, a message type and test data, and the data bits of the test data are shown as high-low alternating transitions.

4. The method for dynamic adjustment of sampling delay according to claim 3, characterized in that: The step of recording the number of erroneous receptions of all the test messages according to the reception result of each of the test messages comprises: Calculating a first check value according to the test data in the test message, and comparing the calculated first check value with a second check value carried in the test message to determine whether the test message is correctly received; The test messages that are erroneously received are counted to determine the number of erroneous receptions.

5. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: The determining, according to the number of erroneous receptions, whether to reconfigure the sampling time of the first chip comprises: If the number of erroneous receptions is greater than zero, determining to reconfigure the sampling time; If the number of erroneous reception times is equal to zero, it is determined that there is no need to reconfigure the sampling time.

6. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: The determining, according to the current number of erroneous receptions, whether the current preset delay time satisfies a preset condition includes: If the number of erroneous receptions is greater than zero, it is determined that the current preset delay time does not meet the preset condition; If the number of erroneous reception times is equal to zero, it is determined that the current preset delay time meets the preset condition, and the current preset delay time is used as the optimal delay time.

7. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: When the system clock is 125Mhz, the value range of the preset delay time is: 0.5ns-3.5ns.

8. The method for dynamic adjustment of sampling delay according to claim 1, characterized in that: When the first chip is a CPU chip, the second chip is a PHY chip; When the first chip is a PHY chip, the second chip is a CPU chip.

9. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the method for dynamic adjustment of sampling delay according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: A computer program is stored therein, and when the computer program is executed on a processor, the method for dynamically adjusting the sampling delay according to any one of claims 1 to 8 is implemented.

Images