Chip test system, chip test method and device

Abstract

The embodiment of the invention discloses a chip test system, a chip test method and equipment, the system comprises a test unit, an execution unit and at least one image acquisition unit, and the image acquisition unit comprises an image acquisition chip; the test unit is used for sending a plurality of test items for the image acquisition chip to the execution unit; the execution unit is used for sending a first image acquisition instruction corresponding to one test item to each image acquisition unit; in response to a detected first acquisition ending message triggered by the first image acquisition unit, sending a second image acquisition instruction corresponding to the next test item to the first image acquisition unit, obtaining a first acquisition image obtained based on the first image acquisition instruction, and performing image calculation on the first acquisition image to obtain an image test result, sending an image test result to a test unit; and the image acquisition unit is used for performing image acquisition based on the image acquisition instruction in response to the image acquisition instruction to obtain an acquired image.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a chip testing system, a chip testing method and a chip testing device. Background Art

[0002] In the process of testing the image acquisition chip, a plurality of test items related to image acquisition are usually set. The test equipment controls the image acquisition chip to acquire images based on the plurality of test items, determines the quality of the image acquired by the image acquisition chip according to the image acquisition results, and obtains the test results of the image acquisition chip.

[0003] In the related art, a testing device sequentially tests an image acquisition chip based on multiple test items to obtain test results corresponding to the multiple test items. After completing one test item, the testing device continues to execute the next test item. When there are a large number of test items, the testing efficiency of this method is low. Summary of the invention

[0004] The embodiments of the present disclosure provide a method and an apparatus, an electronic device, and a storage medium to solve the above technical problems to a certain extent.

[0005] In one aspect of an embodiment of the present disclosure, a chip testing system is provided, comprising a testing unit, an execution unit, and at least one image acquisition unit, wherein the image acquisition unit comprises an image acquisition chip;

[0006] The testing unit is used to send a plurality of test items for the image acquisition chip to the execution unit, and receive the image test results sent by the execution unit;

[0007] The execution unit is configured to receive the multiple test items; send a first image acquisition instruction corresponding to a test item to each of the image acquisition units respectively; in response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by the first image acquisition unit, send a second image acquisition instruction corresponding to a next test item to the first image acquisition unit, and acquire a first acquisition image obtained based on the first image acquisition instruction, perform image calculation on the first acquisition image to obtain an image test result corresponding to the one test item, and send the image test result to the test unit; wherein the first image acquisition unit is any image acquisition unit among the at least one image acquisition unit, and the multiple test items include the one test item and the next test item;

[0008] The image acquisition unit is used to, in response to receiving the image acquisition instruction sent by the execution unit, perform image acquisition based on the image acquisition instruction to obtain an acquired image.

[0009] Another aspect of the embodiments of the present disclosure provides a chip testing method, the method being used in an execution unit of a chip testing system, the chip testing system further comprising a testing unit and at least one image acquisition unit, the method comprising:

[0010] receiving a plurality of test items for the image acquisition chip sent by the test unit;

[0011] Sending a first image acquisition instruction corresponding to one of the multiple test items to each of the image acquisition units respectively;

[0012] In response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by a first image acquisition unit, sending a second image acquisition instruction corresponding to a next test item to the first image acquisition unit, acquiring a first acquired image obtained by the first image acquisition unit executing the first image acquisition instruction, performing image calculation on the first acquired image to obtain an image test result corresponding to the one test item, the multiple test items including the next test item, and the first image acquisition unit being any image acquisition unit of the at least one image acquisition unit;

[0013] Sending the image test result corresponding to the one test item to the test unit.

[0014] In an exemplary embodiment, the step of acquiring the first captured image obtained by the first image acquisition unit executing the first image acquisition instruction includes:

[0015] Read the first acquired image from a storage path where the first image acquisition unit stores images;

[0016] The method further comprises:

[0017] Clear the first acquired image stored in the storage path.

[0018] In an exemplary embodiment, in response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by the first image acquisition unit, sending a second image acquisition instruction corresponding to a next test item to the first image acquisition unit includes:

[0019] In response to detecting the first acquisition end message, sending the first acquisition end message to the test unit so that the test unit sends the next test item;

[0020] The next test item sent by the test unit is received, and a second image acquisition instruction corresponding to the next test item is sent to the first image acquisition unit.

[0021] According to another aspect of the embodiments of the present disclosure, a chip testing device is provided, wherein the chip testing device includes the chip testing system as described in any of the above embodiments.

[0022] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the chip testing method described in any of the above embodiments is implemented.

[0023] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the chip testing method described in any of the above embodiments is implemented.

[0024] Another aspect of the embodiments of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the chip testing method described in any of the above embodiments.

[0025] In an embodiment of the present disclosure, an execution unit is provided between a test unit that manages test items and an image acquisition unit that performs image acquisition. The execution unit receives multiple test items sent by the test unit. For one image acquisition unit, the execution unit sends a first image acquisition instruction corresponding to a test item to the image acquisition unit. When receiving a first acquisition completion message triggered by the image acquisition unit, the execution unit may send a next test item to the image acquisition unit so that the image acquisition unit continues to perform the image acquisition task of the next test item. At the same time, the execution unit may perform image calculation on a first acquired image acquired by the image acquisition unit based on the first image acquisition instruction to obtain an image test result corresponding to the test item, and return the test result to the test unit. That is, the execution unit controls the image acquisition unit to perform image acquisition based on each test item respectively, so that the image acquisition unit can continue to perform the image acquisition task of the next test item after completing the image acquisition task corresponding to one test item, without waiting for the image calculation process of the test item. This can improve the efficiency of the image acquisition unit in executing multiple image acquisition tasks corresponding to multiple test items and avoid waste of hardware resources.

[0026] In addition, when the execution unit controls the image acquisition unit to perform image acquisition based on each test item, the execution unit performs image calculation on the image acquired by the image acquisition unit to obtain an image processing result. Even if the image calculation process of one test item can be executed in parallel with the image acquisition process of the next test item, compared with the serial execution method of the test items in the related technology, the execution efficiency of multiple test items can be improved, which helps to improve the testing efficiency of the image acquisition chip.

[0027] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0029] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0030] Figure 1 A schematic diagram of the structure of a chip testing system provided by an exemplary embodiment of the present disclosure.

[0031] Figure 2 It is a structural schematic diagram of a chip testing system provided by another exemplary embodiment of the present disclosure.

[0032] Figure 3 It is a flowchart of a chip testing process performed by a chip testing system provided by an exemplary embodiment of the present disclosure.

[0033] Figure 4 is a flowchart of a chip testing method provided by an exemplary embodiment of the present disclosure.

[0034] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0036] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0037] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0038] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0039] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0040] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0041] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0042] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0043] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0044] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0045] The disclosed embodiments can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0046] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0047] In the related art, for multiple test items for testing image acquisition chips, the test equipment sequentially executes each of the multiple test items to obtain the test results of each test item. After one test item is executed, the next test item is executed, which makes the test efficiency of the image acquisition chip low.

[0048] The execution process of a test item includes an image acquisition process and an image calculation process. In the embodiment of the present disclosure, an execution unit is set between the test unit and the image acquisition unit of the chip testing system, and the execution unit executes the image calculation process of the test item, separating the image acquisition process and the image calculation process of the test item, so that the image acquisition and image calculation processes corresponding to different test items can be executed in parallel, thereby improving the testing efficiency of the image acquisition chip.

[0049] like Figure 1 , which shows a structural block diagram of a chip testing system provided by an exemplary embodiment of the present disclosure. The chip testing system 10 includes a testing unit 110 , an execution unit 120 and at least one image acquisition unit 130 .

[0050] The test unit 110 is a unit for managing the test process in the chip test system. In an exemplary embodiment, during the test of the image acquisition chip, the test unit 110 is used to issue multiple test items for the image acquisition chip and output the test results of the multiple test items corresponding to the image acquisition chip. Among them, different test items for the image acquisition chip may correspond to at least one of different image acquisition conditions, different image acquisition methods, and different image acquisition contents.

[0051] The execution unit 120 is a unit for executing the test process in the chip test system. In an exemplary embodiment, during the test of the image acquisition chip, the test unit 110 sends a test item to the execution unit 120, and the execution unit 120 controls each image acquisition unit in the lower computer to perform image acquisition based on the test item according to the test item, and performs image calculation on the image acquired by each image acquisition unit to obtain an image test result.

[0052] In one possible implementation, the test unit 110 and the execution unit 120 may be integrated into the host computer of the test device, and the test unit 110 sends the test items, and the execution unit 120 controls the lower computer of the test device to execute the test items and obtain the test results corresponding to the test items. In another possible implementation, the test unit 110 and the execution unit 120 may be independently set up, and illustratively, the test unit 110 may be the host computer (Tester) of the test device, and the execution unit 120 may be a server for image processing, and the execution unit 120 may also be called a workstation (Work Station). The host computer sends each test item to the workstation, and the workstation controls the image acquisition unit to perform image acquisition based on the test items, and obtains the image acquired by the image acquisition unit to perform image calculation, and obtains the test results corresponding to the test items.

[0053] The image acquisition unit 130 is a unit in the chip test system for controlling the image acquisition chip to perform image acquisition. The image acquisition unit 130 includes an image acquisition chip. Optionally, one image acquisition unit 130 includes one image acquisition chip. In a possible implementation, the image acquisition unit 130 may be a test station (site) of an image acquisition board in a lower computer of a test device. An image acquisition board has multiple channels, and different channels are respectively connected to different test stations, which can control different test stations to perform image acquisition. In an exemplary embodiment, when the execution unit sends an image acquisition instruction to an image acquisition unit, the image acquisition instruction may be sent to the image acquisition board corresponding to the image acquisition unit, and the image acquisition board sends the instruction to the image acquisition unit to control the image acquisition unit to perform image acquisition.

[0054] In an exemplary embodiment, the testing unit is used to send multiple test items for the image acquisition chip to the execution unit, and receive the image test results sent by the execution unit.

[0055] An execution unit is used to receive multiple test items; send a first image acquisition instruction corresponding to a test item to each image acquisition unit respectively; in response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by the first image acquisition unit, send a second image acquisition instruction corresponding to the next test item to the first image acquisition unit, and obtain a first acquisition image obtained based on the first image acquisition instruction, perform image calculation on the first acquisition image to obtain an image test result corresponding to the test item, and send the image test result to the test unit. The first image acquisition unit is any image acquisition unit in at least one image acquisition unit, and the multiple test items include a test item and a next test item.

[0056] The image acquisition unit is used to, in response to receiving the image acquisition instruction sent by the execution unit, perform image acquisition based on the image acquisition instruction to obtain the acquired image.

[0057] Specifically, the test unit may obtain multiple test items configured by the user and send them to the execution unit. In one possible implementation, the test unit may send each test item to the execution unit in sequence; in another possible implementation, the test unit may send multiple test items for the image acquisition chip to the execution unit at the same time.

[0058] The execution unit receives multiple test items sent by the test unit. When the execution unit receives a test item, it sends a first image acquisition instruction corresponding to the test item to each image acquisition unit, and the first image acquisition instruction includes the image acquisition condition, image acquisition content, image acquisition method, etc. indicated by the test item.

[0059] After receiving an image acquisition instruction, the image acquisition unit will trigger a corresponding acquisition completion message after completing the image acquisition based on the image acquisition instruction, indicating that the image acquisition based on the current image acquisition instruction has been completed. In one possible implementation, after the image acquisition unit acquires the image, the image acquisition board may send an acquisition completion message to the execution unit so that the execution unit obtains the information that the image acquisition is completed; in another possible implementation, the execution unit may monitor the acquisition signal in the image acquisition board that is used to characterize the acquisition dynamics of the image acquisition unit, and when the acquisition signal indicates that the image acquisition unit has completed the image acquisition, it is determined that the acquisition completion message triggered by the image acquisition unit has been received.

[0060] For the first image acquisition unit in the image acquisition unit, after the execution unit detects the first acquisition end message corresponding to the first image acquisition instruction triggered by the first image acquisition unit, the second image acquisition instruction corresponding to the next test item is sent to the first image acquisition unit, so that the first image acquisition unit continues to perform image acquisition based on the second image acquisition instruction. The next test item is the next test item arranged after the above-mentioned sent test item in the multiple test items. The multiple test items have an arrangement order, and the execution unit sequentially controls the image acquisition unit to perform image acquisition according to the arrangement order of the multiple test items. Optionally, different test items have different numbers, and the arrangement order of the test items can be determined according to the numbers of the test items. Schematically, the multiple test items include 400 test items numbered 001-400. After sending the first image acquisition instruction based on the test item numbered 001 to the first image acquisition unit, in response to detecting the first acquisition end message corresponding to the first image acquisition instruction, it is determined that the first image acquisition unit has completed the image acquisition task corresponding to the test item 001, and the second image acquisition instruction corresponding to the next test item 002 of the test item 001 is sent to the first image acquisition unit.

[0061] By controlling the timing of image acquisition by each image acquisition unit through the execution unit, each image acquisition unit can continuously execute the image acquisition tasks corresponding to multiple test items without waiting for the image calculation process corresponding to the test items, which helps to improve the test efficiency and avoid the waste of hardware resources used for image acquisition.

[0062] The execution unit is also used to execute the image calculation process corresponding to the test item. After the execution unit detects the first acquisition end message corresponding to the first image acquisition instruction triggered by the first image acquisition unit, the first acquisition image obtained by the first image acquisition unit based on the first image acquisition instruction can be obtained, and the image calculation is performed on the first acquisition image to obtain an image test result corresponding to a test item, and the image test result is sent to the test unit, so that the image calculation process of one test item is executed in parallel with the image acquisition process of the next test item, thereby improving the test efficiency. In combination with the above example, after the execution unit detects the first acquisition end message corresponding to the first image acquisition instruction based on test item 001, the first acquisition image obtained by the first image acquisition unit based on test item 001 can be obtained, and the image calculation is performed on the first acquisition image to obtain the image test result corresponding to test item 001, and the image test result is sent to the test unit, and the test unit performs test result statistics.

[0063] In a possible implementation, after the image acquisition unit acquires an acquired image based on the image acquisition instruction, the acquired image may be sent to the execution unit, and the execution unit receives the acquired image sent by the image acquisition unit to perform image calculation. In another possible implementation, after the image acquisition unit acquires an acquired image based on the image acquisition instruction, the acquired image may be stored in a preset storage location, and the execution unit may obtain the acquired image from the preset storage location to perform image calculation.

[0064] In an embodiment of the present disclosure, an execution unit is provided between a test unit that manages test items and an image acquisition unit that performs image acquisition. The execution unit receives multiple test items sent by the test unit. For one image acquisition unit, the execution unit sends a first image acquisition instruction corresponding to a test item to the image acquisition unit. When receiving a first acquisition completion message triggered by the image acquisition unit, the execution unit may send a next test item to the image acquisition unit so that the image acquisition unit continues to perform the image acquisition task of the next test item. At the same time, the execution unit may perform image calculation on a first acquired image acquired by the image acquisition unit based on the first image acquisition instruction to obtain an image test result corresponding to the test item, and return the test result to the test unit. That is, the execution unit controls the image acquisition unit to perform image acquisition based on each test item respectively, so that the image acquisition unit can continue to perform the image acquisition task of the next test item after completing the image acquisition task corresponding to one test item, without waiting for the image calculation process of the test item. This can improve the efficiency of the image acquisition unit in executing multiple image acquisition tasks corresponding to multiple test items and avoid waste of hardware resources.

[0065] In addition, when the execution unit controls the image acquisition unit to perform image acquisition based on each test item, the execution unit performs image calculation on the image acquired by the image acquisition unit to obtain an image processing result. Even if the image calculation process of one test item can be executed in parallel with the image acquisition process of the next test item, compared with the serial execution method of the test items in the related technology, the execution efficiency of multiple test items can be improved, which helps to improve the testing efficiency of the image acquisition chip.

[0066] In an exemplary embodiment, the execution unit includes a message distribution subunit, a file processing subunit, and an image processing subunit.

[0067] The message distribution subunit is used to receive multiple test items, send a first image acquisition instruction corresponding to a test item to the first image acquisition unit; in response to detecting the first acquisition end message, send an image reading instruction to the file processing subunit; and send an image test result corresponding to a test item to the test unit.

[0068] The file processing subunit is used to read the first acquired image from the storage path where the first image acquisition unit stores images in response to the image reading instruction, and send the first acquired image to the image processing subunit.

[0069] The image processing subunit is used to perform image calculation on the first collected image to obtain an image test result corresponding to a test item; and send the image test result corresponding to the test item to the message processing subunit.

[0070] Indicatively, Figure 2, which shows a schematic diagram of the structure of a chip testing system provided by another exemplary embodiment of the present disclosure. The execution unit 120 includes a message dispatching subunit (Message Dispatcher) 1201, an image processing subunit (Image Process) 1202 and a file processing subunit 1203.

[0071] The message distribution subunit 1201 is used for message forwarding between the test unit 110 and the execution unit 120, for message forwarding between the execution unit 120 and the image acquisition unit 130, and for message forwarding between subunits in the execution unit. Optionally, the message distribution subunit and the test unit can communicate based on a communication protocol. Schematically, the communication protocol can be a remote procedure call (RPC) protocol, a gRPC protocol, etc.; or, the message distribution subunit and the test unit can communicate through a message queue system. Schematically, the message queue system can be a Kafka system, a ZeroMQ system, a Rabbit system, etc.

[0072] The image processing subunit 1202 is used to perform image calculation on the image acquired by the image acquisition unit to obtain an image test result. The image calculation process includes a feature extraction process and a feature processing process for the image. The image quality of the acquired image is determined by feature extraction and feature processing, and the test result corresponding to the test item is determined according to the image quality of the acquired image.

[0073] The file processing subunit 1203 is used to obtain and store images acquired by the image acquisition unit, and to clean up images that have undergone image calculation.

[0074] In one example, the message distribution subunit 1201 receives the test item sent by the test unit 110, and sends a first image acquisition instruction corresponding to a test item to the first image acquisition unit. The message distribution subunit 1201 also detects a first acquisition end message of the first image acquisition unit, and sends an image reading instruction to the file processing subunit 1203 in the execution unit 120 when the first acquisition end message is detected.

[0075] In a possible implementation, each image acquisition unit is pre-configured with a corresponding storage path, and the file processing subunit 1203 determines the storage path corresponding to the first image acquisition unit in response to the image reading instruction, and obtains the first acquisition image by reading the storage path of the first image acquisition unit. Optionally, the image reading instruction includes an instruction for instructing to read the first acquisition image, and the instruction may include an image identifier corresponding to the first acquisition image. Optionally, the image identifier of the acquisition image may be composed of a test item number and an image acquisition unit number, which is used to identify a unique image. For example, the image identifier of the first acquisition image may be composed of a test item number 001 and a first image acquisition unit number, which is used to indicate that the image is acquired by the first image acquisition unit based on the test item 001. Afterwards, the file processing subunit 1203 sends the read first acquisition image to the image processing subunit 1202. Optionally, the file processing subunit 1203 may send the first acquisition image to the message distribution subunit 1201, and the message distribution subunit 1201 forwards it to the image processing subunit 1202. After receiving the first acquired image, the image processing subunit 1202 performs image calculation on the first acquired image to obtain an image test result corresponding to a test item, and then sends the image test result corresponding to the test item to the message distribution subunit 1201. The message distribution subunit 1201 forwards the image test result corresponding to the test item to the test unit 110.

[0076] In an exemplary embodiment, the file processing subunit is further used to clear the first acquired image in the storage path for storing the first acquired image after sending the first acquired image to the image processing subunit. That is, after processing a acquired image, the stored acquired image is cleared to avoid the acquired image from continuously occupying the storage space. Schematically, the file processing subunit can send an image clearing instruction to the image acquisition board where the first image acquisition unit is located through the message distribution subunit, and the image clearing instruction includes the image identification of the first acquired image, and the image acquisition board clears the first acquired image in the storage path based on the image identification of the first acquired image.

[0077] In another possible implementation, after completing image acquisition, the image acquisition unit sends the acquired image to the file processing subunit 1203 of the execution unit through the message distribution subunit 1201 of the execution unit. The file processing subunit 1203 stores the acquired image, and the image processing subunit 1202 in the execution unit 120 processes the acquired images stored in the file processing subunit 1203 in sequence. During this process, the image processing subunit 1202 can obtain the acquired image from the file processing subunit 1203 through the message distribution subunit 1201. After the file processing subunit 1203 sends an acquired image, the stored acquired image is cleared.

[0078] In an exemplary embodiment, Figure 2 As shown, the execution unit 120 also includes a log recording subunit 1204 and an error handling subunit 1205, wherein the log recording subunit 1204 is used to record the logs generated during the image processing process so as to facilitate subsequent data query and location. The error handling subunit 1205 is used to handle errors during message forwarding, image processing, and file processing.

[0079] In the embodiment of the present disclosure, an image processing subunit is provided in the execution unit to perform image calculation on the image collected by the image acquisition unit, so as to realize the parallel execution of the image calculation and the image acquisition process. A message distribution subunit is also provided in the execution unit to manage the message distribution between different units and within the execution unit, so that the image acquisition and image processing processes are executed in an orderly manner.

[0080] In addition, the file processing subunit obtains the image collected by the image collection unit and cleans up the image that has been processed, so as to avoid the continuous occupation of storage space by the collected image and reduce the waste of hardware resources.

[0081] In one possible implementation, the test unit may send multiple test items to the execution unit at the same time, and the execution unit controls each image acquisition unit to perform image acquisition in sequence according to the order of the multiple test items. In another possible implementation, the execution unit sends a first acquisition end message to the test unit in response to detecting a first acquisition end message triggered by the first image acquisition unit, and the test unit sends the next test item to the execution unit in response to the first acquisition end message, so that the execution unit sends a second image acquisition instruction to the first image acquisition unit based on the next test item. That is, after any image acquisition unit completes the image acquisition task corresponding to a test item, the execution unit may send the corresponding acquisition end message to the test unit, and the test unit continues to send the next test item, which is sent to the execution unit in sequence according to the order of the multiple test items.

[0082] It should be noted that after the execution unit detects the first first acquisition end message, it sends the first acquisition end message to the test unit, so that the test unit sends the next test item. The execution unit stores the next test item. After detecting subsequent messages triggered by other image acquisition units, such as the second first acquisition end message and the third first acquisition end message, it does not need to be sent to the test unit again.

[0083] In an exemplary embodiment, after the message distribution subunit in the execution unit detects the first first acquisition end message, it sends the first acquisition end message to the test unit, the test unit sends the next test item to the message distribution subunit, and the message distribution subunit sends the image acquisition instruction corresponding to the next test item to the corresponding image acquisition unit based on the next test item.

[0084] In the disclosed embodiment, the test unit sends multiple test items to the execution unit in sequence according to the execution status of each test item. After detecting that an image acquisition unit has completed the image acquisition task of a test item, it continues to send the next test item to ensure the orderly execution of multiple test items.

[0085] In an exemplary embodiment, the execution unit is further used to send an image test result corresponding to any one of the multiple test items to the test unit. The test unit is also used to receive an image test result corresponding to any one of the multiple test items, and in response to receiving the image test result of the last test item, end the chip test of the image acquisition chip.

[0086] After calculating the image test result corresponding to any test item, the execution unit sends it to the test unit, and the test unit performs test result statistics. In a possible implementation, when the chip test system includes an image acquisition unit, and an image acquisition unit includes an image acquisition chip (i.e., testing an image acquisition chip), the execution unit may send image acquisition instructions corresponding to each test item to the image acquisition unit in sequence, so that the image acquisition unit controls the image acquisition chip to perform the image acquisition tasks corresponding to each test item in sequence, and the execution unit calculates the image corresponding to each test item acquired by the image acquisition unit, obtains the image quality of the image acquired by the image acquisition chip in the image acquisition unit based on each test item (i.e., the test result of testing the image acquisition chip based on each test item), and returns the image test result of each test item to the test unit. That is, when the chip testing system includes an image acquisition unit, the image test results in multiple test items sent by the execution unit to the test unit are test results obtained by testing the same image acquisition chip based on multiple test items. In this case, the test unit ends the chip test of the image acquisition chip in response to receiving the image test result of the last test item calculated based on the image acquired by the last test item and sent by the execution unit.

[0087] In another possible implementation, when the chip test system includes multiple image acquisition units (i.e., multiple image acquisition chips are tested simultaneously), the image test results of multiple test items sent by the execution unit to the test unit include the test results obtained by testing multiple image acquisition chips based on the multiple test items. Schematically, when 8 image acquisition units and 400 test items are included, the image test results of multiple test items sent by the execution unit to the test unit include the test results obtained by testing the image acquisition chips in the 8 image acquisition units based on the 400 test items. Since different image acquisition units have different times for image acquisition based on the same test item, the execution unit has different calculation times for images acquired by different image acquisition units based on the same test item. Therefore, the execution unit returns the test results obtained by testing the image acquisition chips in different image acquisition units based on the same test item to the test unit at different times. In a possible implementation, the test unit ends the chip test of multiple image acquisition chips after receiving the image test result of the last image acquisition chip based on the last test item. Optionally, the image test result returned by the execution unit to the test unit indicates a test item number and a corresponding image acquisition unit number, and can determine whether an image test result obtained by testing the image acquisition chip in the last image acquisition unit based on the last test item has been received based on the test item number and the image acquisition unit number; after receiving the image test result of the last image acquisition chip based on the last test item, the chip test of multiple image acquisition chips is terminated, and the test results obtained by testing each image acquisition chip based on different test items are output.

[0088] In a possible implementation, different image acquisition units in at least one image acquisition unit perform image acquisition in parallel based on the image acquisition instructions received by each. That is, after the test unit sends a test item to the execution unit, the execution unit sends a first image acquisition instruction corresponding to a test item to different image acquisition units respectively, and each image acquisition unit performs image acquisition in parallel based on the first image acquisition instruction. After any image acquisition unit completes image acquisition based on the first image acquisition instruction, the execution unit detects a first acquisition end message triggered by the image acquisition unit and sends a second image acquisition instruction to the image acquisition unit. When the execution unit detects the first acquisition end message triggered by other image acquisition units, it sends a second image acquisition instruction to other image acquisition units. Each image acquisition unit performs its own image acquisition task in parallel, which can improve the test efficiency of multiple image acquisition chips based on multiple test items.

[0089] Optionally, different image acquisition units may include different types of image acquisition chips to implement parallel testing of different types of image acquisition chips.

[0090] In the embodiment of the present disclosure, the chip testing system includes different image acquisition units that can execute image acquisition tasks in parallel, that is, multiple image acquisition chips can be tested in parallel, which helps to improve the testing efficiency of multiple image acquisition chips.

[0091] In an exemplary embodiment, the execution unit is further used to perform image calculation on the next acquired image after performing image calculation on the first acquired image to obtain an image test result corresponding to a test item, and to send an image test result corresponding to a test item to the test unit in parallel.

[0092] That is, the execution unit performs the image calculation process and the process of returning the image test result of the test item to the test unit in parallel. Exemplarily, when the execution unit performs image calculation on the first acquired image acquired by the image acquisition chip 01 based on the test item 001 and obtains the image test result obtained by testing the image acquisition chip 01 based on the test item 001, it performs image calculation on the next acquired image and sends the image test result corresponding to the test item 001 to the test unit in parallel.

[0093] Optionally, the next acquisition image refers to an acquisition image corresponding to an acquisition end message received by the execution unit after receiving the first acquisition end message. The next acquisition end message may be the next acquisition end message triggered by the first image acquisition unit that acquires the first acquisition image. In this case, the next acquisition image may be the second acquisition image acquired by the first image acquisition unit based on the next test item. Alternatively, the next acquisition end message may be the first acquisition end message or an acquisition end message corresponding to another test item triggered by a second image acquisition unit different from the first image acquisition unit. In this case, the next acquisition image is the acquisition image acquired by the second image acquisition unit.

[0094] In the disclosed embodiment, the execution unit executes the image calculation process and the process of returning the image test result to the test unit in parallel, which can further improve the efficiency of testing the image acquisition chip based on multiple test items.

[0095] In an exemplary embodiment, Figure 3 As shown, it shows a schematic flow chart of a chip testing process executed by a chip testing system provided by an exemplary embodiment of the present disclosure.

[0096] The test unit 110 runs the test item, that is, starts the test, and sends a test item to the execution unit 120. The message distribution subunit of the execution unit 120 receives the test item and sends a first image acquisition instruction corresponding to the test item to each image acquisition unit (including the image acquisition unit 1300 (site0), the image acquisition unit 1301 (site1), and the image acquisition unit 1302 (site2)). The image acquisition units 1300, 1301, and 1302 perform image acquisition based on the first image acquisition instruction in parallel. After the image acquisition unit 1300 acquires an image based on a test item to obtain a first acquisition image, a first acquisition end message is triggered. The message distribution subunit of the execution unit 120 detects the first acquisition end message and sends the first acquisition end message to the test unit 110. The test unit 110 sends the next test item to the execution unit 120. The message distribution subunit of the execution unit 120 receives the next test item and sends the second image acquisition instruction corresponding to the next test item to the image acquisition unit 1300. The image acquisition unit 1300 continues to perform image acquisition based on the second image acquisition instruction. When the message distribution subunit of the execution unit 120 detects the first acquisition end message, it sends an image reading instruction to the file processing submodule, the file processing submodule reads the first acquisition image, and sends it to the image processing subunit through the message distribution subunit, the image processing subunit performs image calculation to obtain an image test result corresponding to a test item and sends it to the test unit. After receiving the test result of the last test item, the test unit ends the test of the image acquisition chip.

[0097] like Figure 4 As shown, it shows a chip testing method provided by an exemplary embodiment of the present disclosure, which can be used in the execution unit of the above chip testing system. The method includes the following steps 410-440:

[0098] Step 410: receiving a plurality of test items for the image acquisition chip sent by a test unit.

[0099] In a possible implementation, the message distribution subunit in the execution unit may receive multiple test items sent by the test unit.

[0100] Step 420: Send a first image acquisition instruction corresponding to a test item among the multiple test items to each image acquisition unit.

[0101] The message distribution subunit sends a first image acquisition instruction corresponding to a test item among the multiple test items to each image acquisition unit in the at least one image acquisition unit.

[0102] Step 430, in response to detecting a first acquisition end message corresponding to a first image acquisition instruction triggered by the first image acquisition unit, sending a second image acquisition instruction corresponding to a next test item to the first image acquisition unit, acquiring a first acquired image obtained by the first image acquisition unit executing the first image acquisition instruction, and performing image calculation on the first acquired image to obtain an image test result corresponding to a test item.

[0103] The multiple test items include a test item and a next test item, and the first image acquisition unit is any image acquisition unit of the at least one image acquisition unit.

[0104] In an exemplary embodiment, in response to detecting a first acquisition end message corresponding to a first image acquisition instruction triggered by a first image acquisition unit, a first acquisition end message is sent to a test unit so that the test unit sends a next test item, and then the next test item sent by the test unit is received, and a second image acquisition instruction corresponding to the next test item is sent to the first image acquisition unit.

[0105] When the message distribution subunit detects that the first image acquisition instruction triggered by the first image acquisition unit corresponds to the first acquisition end message, the first acquisition end message can be sent to the test unit. In response to the first acquisition end message, the test unit sends the next test item to the execution unit. After receiving the next test item, the message distribution subunit sends the second image acquisition instruction corresponding to the next test item to the first image acquisition unit.

[0106] In an exemplary embodiment, when acquiring the first acquired image obtained by the first image acquisition unit executing the first image acquisition instruction, the first acquired image can be read from the storage path of the first image acquisition unit storing images. After reading, the first acquired image stored in the storage path is cleared. Specifically, the message distribution subunit sends an image reading instruction to the file processing subunit in response to the first acquisition end message. The file processing subunit reads the first acquired image from the storage path of the first image acquisition unit storing images based on the first acquired image to be read indicated by the image reading instruction, and sends it to the image processing subunit through the message distribution subunit. The image processing subunit performs image calculation on the first acquired image to obtain an image test result, and sends the image test result to the message distribution subunit. The message distribution subunit sends the image test result to the test unit. When the message distribution subunit sends the image test result to the test unit, the image processing subunit can perform the image calculation process for the next acquired image in parallel. After sending the first acquired image to the image processing subunit, the file processing subunit may clear the first acquired image in the storage path of the first image acquisition unit for storing images. Schematically, an image clearing instruction may be sent to an image acquisition board corresponding to the first image acquisition unit. The image clearing instruction includes an image identifier corresponding to the first acquired image. The image acquisition board clears the image according to the image identifier of the first acquired image.

[0107] Step 440: Send an image test result corresponding to a test item to the test unit.

[0108] The chip testing method in the embodiment of the present disclosure may correspond to the embodiment of the chip testing system in the present disclosure, and the relevant contents may be referenced to each other and will not be repeated here.

[0109] In an embodiment of the present disclosure, an execution unit is provided between a test unit that manages test items and an image acquisition unit that performs image acquisition. The execution unit receives multiple test items sent by the test unit. For one image acquisition unit, the execution unit sends a first image acquisition instruction corresponding to a test item to the image acquisition unit. When receiving a first acquisition completion message triggered by the image acquisition unit, the execution unit may send a next test item to the image acquisition unit so that the image acquisition unit continues to perform the image acquisition task of the next test item. At the same time, the execution unit may perform image calculation on a first acquired image acquired by the image acquisition unit based on the first image acquisition instruction to obtain an image test result corresponding to the test item, and return the test result to the test unit. That is, the execution unit controls the image acquisition unit to perform image acquisition based on each test item respectively, so that the image acquisition unit can continue to perform the image acquisition task of the next test item after completing the image acquisition task corresponding to one test item, without waiting for the image calculation process of the test item. This can improve the efficiency of the image acquisition unit in executing multiple image acquisition tasks corresponding to multiple test items and avoid waste of hardware resources.

[0110] In addition, when the execution unit controls the image acquisition unit to perform image acquisition based on each test item, the execution unit performs image calculation on the image acquired by the image acquisition unit to obtain an image processing result. Even if the image calculation process of one test item can be executed in parallel with the image acquisition process of the next test item, compared with the serial execution method of the test items in the related technology, the execution efficiency of multiple test items can be improved, which helps to improve the testing efficiency of the image acquisition chip.

[0111] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0112] Memory for storing computer programs;

[0113] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip testing method described in any of the above embodiments of the present disclosure is implemented.

[0114] like Figure 5 As shown, the electronic device includes one or more processors and memory.

[0115] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0116] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the chip testing method of each embodiment of the present disclosure described above and / or other desired functions.

[0117] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0118] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0119] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0120] Of course, to simplify, Figure 5 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0121] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0122] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0123] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0124] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0125] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0126] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0127] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0128] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0129] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0130] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0131] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip testing system, characterized in that: It includes a testing unit, an execution unit and at least one image acquisition unit, wherein the image acquisition unit includes an image acquisition chip; The testing unit is used to send a plurality of test items for the image acquisition chip to the execution unit, and receive the image test results sent by the execution unit; The execution unit is used to receive the multiple test items; Sending a first image acquisition instruction corresponding to a test item to each of the image acquisition units respectively; In response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by a first image acquisition unit, sending a second image acquisition instruction corresponding to a next test item to the first image acquisition unit, acquiring a first acquisition image based on the first image acquisition instruction, performing image calculation on the first acquisition image to obtain an image test result corresponding to the one test item, and sending the image test result to the test unit; wherein the first image acquisition unit is any one of the at least one image acquisition unit, and the multiple test items include the one test item and the next test item; The image acquisition unit is used to, in response to receiving the image acquisition instruction sent by the execution unit, perform image acquisition based on the image acquisition instruction to obtain an acquired image.

2. The system according to claim 1, characterized in that The execution unit includes a message distribution subunit, a file processing subunit and an image processing subunit; The message distribution subunit is configured to receive the multiple test items and send a first image acquisition instruction corresponding to the one test item to the first image acquisition unit; In response to detecting the first acquisition end message, sending an image reading instruction to the file processing subunit; sending an image test result corresponding to the one test item to the test unit; The file processing subunit is used to read the first acquired image from the storage path where the first image acquisition unit stores images in response to the image reading instruction, and send the first acquired image to the image processing subunit; The image processing subunit is used to perform image calculation on the first collected image to obtain an image test result corresponding to the one test item; Sending the image test result corresponding to the one test item to the message processing subunit.

3. The system according to claim 2, characterized in that The file processing subunit is further configured to clear the first acquired image stored in the storage path after sending the first acquired image to the image processing subunit.

4. The system according to any one of claims 1 to 3, characterized in that: The execution unit is further configured to send the first acquisition end message to the test unit in response to detecting the first acquisition end message; The testing unit is further configured to send the next test item to the executing unit in response to the first acquisition completion message.

5. The system according to any one of claims 1 to 3, characterized in that: The execution unit is further configured to send an image test result corresponding to any test item among the multiple test items to the test unit; The testing unit is further configured to receive an image test result corresponding to any one of the multiple test items, and terminate the chip test of the image acquisition chip in response to receiving the image test result of the last test item.

6. The system according to any one of claims 1 to 3, characterized in that: Different image acquisition units in the at least one image acquisition unit perform image acquisition in parallel based on the image acquisition instructions received by each of them.

7. The system according to any one of claims 1 to 3, characterized in that: The execution unit is further configured to, after performing image calculation on the first collected image to obtain the image test result corresponding to the test item, perform image calculation on the next collected image, and send the image test result corresponding to the test item to the test unit in parallel.

8. A chip testing method, characterized in that: The method is used for an execution unit of a chip testing system, the chip testing system further comprising a testing unit and at least one image acquisition unit, and the method comprises: receiving a plurality of test items for the image acquisition chip sent by the test unit; Sending a first image acquisition instruction corresponding to one of the multiple test items to each of the image acquisition units respectively; In response to detecting a first acquisition end message corresponding to the first image acquisition instruction triggered by a first image acquisition unit, sending a second image acquisition instruction corresponding to a next test item to the first image acquisition unit, acquiring a first acquired image obtained by the first image acquisition unit executing the first image acquisition instruction, performing image calculation on the first acquired image to obtain an image test result corresponding to the one test item, the multiple test items including the next test item, and the first image acquisition unit being any image acquisition unit of the at least one image acquisition unit; Sending the image test result corresponding to the one test item to the test unit.

9. A chip testing device, characterized in that: The chip testing device comprises a chip testing system as described in any one of claims 1-7 above.

10. An electronic device, characterized in that: include: Memory for storing computer programs; The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip testing method described in claim 8 is implemented.

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