Globally synchronous and locally asynchronous single slope ADC and CMOS image sensor

Abstract

The present invention belongs to the field of integrated circuits, and specifically relates to a globally synchronous and locally asynchronous single slope ADC and CMOS image sensor. It includes: a timing control circuit, a dynamic ramp generator, a row judgment module, a column readout circuit and a column judgment module. The timing control circuit is used to keep the total conversion time of each pixel unit consistent during the quantization process. The row judgment module is used to determine the swing range of the adaptive ramp; the column readout circuit generates the final pixel value in combination with the quantization results of each stage; the column judgment module is used to generate an enable signal for controlling the dynamic ramp generator and the column readout circuit according to the full-scale quantization results of each pixel unit in the pixel multi-sampling quantization stage, and the circuit is turned off when necessary to reduce the power consumption of the overall circuit. The present invention solves the problem of large overall frame rate differences that still exist when the existing single slope ADC adopts an adaptive correlated multi-sampling mechanism.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a globally synchronous and locally asynchronous single-slope ADC and a CMOS image sensor. Background Art

[0002] CMOS Image Sensor (CIS) has the advantages of small size and easy integration, so it has been widely used in smart phones, security monitoring and medical imaging. In recent years, with the continuous advancement of CMOS integrated circuit technology, more and more advanced application scenarios have put forward higher requirements on the performance of CIS, especially in low-light environments. The noise suppression capability of CMOS image sensors can improve image quality. However, under low-light conditions, the random noise generated by the readout circuit has a greater impact on the total noise. Therefore, how to reduce random noise has become the key to improving the signal-to-noise ratio and thus improving imaging quality.

[0003] The traditional correlated multiple sampling (CMS) technology suppresses circuit noise by sampling the circuit output signal multiple times. Generally speaking, after M samplings, the random noise of the readout circuit can be reduced to 1 / M of the original. However, in the traditional CMS working process, each additional sampling time will double the ADC conversion time, resulting in a significant decrease in the frame rate of the image sensor. On this basis, the conditional correlated multiple sampling (CCMS) technology was proposed. The main idea is to judge the brightness of the pixel output voltage and use a small voltage range ramp to quantize the small swing dark pixel output multiple times to reduce random noise and A / D conversion time. Since the large swing of the two-pixel output is mainly photon shot noise, it cannot be reduced by multiple sampling within one frame time. Therefore, when the pixel output voltage swing exceeds a certain value, the full voltage range ramp is used for single quantization. However, CCMS technology requires the addition of an additional ramp generator, which will face the problem of mismatch between ramp generators and increase the power consumption of the SS ADC.

[0004] On this basis, an adaptive correlated multi-sampling technology is proposed, which latches the maximum and minimum values ​​of the pixel voltage in a row, thereby effectively reducing the slope range of multiple quantization stages without affecting the quantization results. If the pixel voltages of an entire row are relatively close, the adaptive slope used by the ADC using the adaptive correlated multi-sampling technology during quantization has a smaller coverage range, which can greatly reduce the conversion time of the ADC. However, when the adaptive correlated multi-sampling technology generates different adaptive ramp signals for different pixel units, the timing of the entire circuit will be asynchronous, and the A / D conversion time of the circuit for each row of pixel signals is different, which causes the overall frame rate of the CMOS image sensor to be not a fixed value, so there are still difficulties in practical applications. In addition, the existing adaptive correlated multi-sampling technology usually matches the same adaptive ramp for a column or a row of pixel units, which actually causes signal mismatch and increased power consumption for some pixel units. Summary of the invention

[0005] In order to overcome the problems of large overall frame rate difference and high power consumption of existing ADCs using adaptive correlated multi-sampling technology, the present invention provides a globally synchronous and locally asynchronous single-slope ADC and a CMOS image sensor.

[0006] The technical solution provided by the present invention is:

[0007] A globally synchronous and locally asynchronous single slope ADC uses adaptive correlated multi-sampling technology to quantize the output of all pixel units in a CIS. The quantization process includes three stages: reset signal quantization, pixel single full-scale quantization, and pixel multi-sampling quantization. The single slope ADC includes: a timing control circuit, a dynamic ramp generator, a row judgment module, a column readout circuit, and a column judgment module.

[0008] Among them, the timing control circuit is used to generate a global clock control signal that keeps the total conversion time of each pixel unit consistent during the quantization process; the dynamic ramp generator is used to generate the required standard ramp signal, full-scale ramp signal and adaptive ramp signal in three different quantization stages.

[0009] The row judgment module is used to obtain the full-scale quantization results of all pixel units in the same row in the pixel single full-scale quantization stage and identify the maximum value V min and minimum value V max , then according to V min and V max The threshold voltage V that represents the light intensity lt The relationship between the adaptive ramp and the ramp amplitude range is determined and sent to the dynamic ramp generator.

[0010] The column readout circuit is used to perform reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization on the output of the pixel unit in three quantization stages using three types of ramp signals generated by a dynamic ramp generator, and generate the final pixel value by combining the quantization results of each stage.

[0011] The column judgment module is used to first obtain the full-scale quantization results of each pixel unit in each column during the pixel multi-sampling quantization stage, and then generate an enable signal for controlling the dynamic ramp generator and the column readout circuit. This achieves: (1) If the full-scale quantization result of any column pixel unit is greater than V lt , then the multi-sampling quantization task of the pixel in the current column is terminated directly and the column readout circuit of the current column is turned off; (2) If the full-scale quantization result of any column pixel unit is not greater than V lt , then the pixel multi-sampling quantization task of the current column is performed according to the generated adaptive ramp signal; (3) After the pixel multi-sampling quantization tasks of all columns are completed, the ramp generator and the column readout circuits of all columns are turned off, so that the circuit is in idle mode until the preset standard conversion time is reached.

[0012] In the globally synchronous and locally asynchronous single slope ADC provided by the present invention, the standard conversion time is the swing amplitude of the adaptive slope from 0 to V lt The total time consumed by any pixel unit in the pixel multisampling quantization stage when .

[0013] As a further improvement of the present invention, the dynamic ramp generator includes a current steering ramp generator, a two-to-one selector, a first counter and a second counter; the input end of the two-to-one selector is respectively connected to the first counter and the second counter, and the output end is connected to the current steering ramp generator.

[0014] The first counter stores a first code and a second code for controlling the current steering ramp generator to generate a standard ramp with a fixed swing and a full-scale ramp. The second counter stores a third code that can control the current steering ramp generator to generate an adaptive ramp signal with a specified swing. The two-to-one selector selects the corresponding code at different quantization stages to generate the required standard ramp signal, full-scale ramp signal or adaptive ramp signal.

[0015] As a further improvement of the present invention, the current steering ramp generator is a controllable switch circuit, which is composed of a current steering DAC, an enable switch array, a negative feedback circuit and a unit gain buffer. Among them, the current steering DAC is composed of multiple current sources, an output switch array, and resistors R1~R2. In the current steering ramp generator, the output of each current source is divided into two paths, one of which is connected to the upper end of R1 through a group of independent transmission gates in the output switch array and the enable switch array in turn, and the other is connected to the upper end of R2 through another group of independent transmission gates in the output switch array and the enable switch array in turn.

[0016] The negative feedback circuit is connected at the junction of R1 and R2, thereby clamping the initial voltage of the generated ramp signal to a specified fixed value. The unity gain buffer is connected between R1 and the current source of the final stage, thereby outputting a ramp signal that starts from a fixed value and rises at a fixed slope.

[0017] As a further improvement of the present invention, the row judgment module includes a maximum value search circuit, a minimum value search circuit and a swing amplitude generation module. The maximum value search circuit is composed of a multi-stage AND gate, a multi-bit counter and a subtractor; and is used to identify and output the maximum value V according to the full-scale quantization results of the pixel units of all columns in the same row. max The minimum value search circuit is composed of a multi-stage OR gate and a multi-bit counter; and is used to identify and output the minimum value V according to the full-scale quantization results of the pixel units in all columns in the same row. min The swing generation module is implemented by a logic circuit, which is used to convert V min As the lower limit of the adaptive ramp signal, V max and V lt The smaller one of them serves as the upper limit of the swing of the adaptive ramp signal.

[0018] As a further improvement of the present invention, the column judgment module is composed of an initial value preset module and a final value judgment module. The initial value preset module is used to write the lower limit of the swing into the second counter as the initial voltage of the generated adaptive ramp signal. The final value judgment module is used to judge whether each slope in the adaptive ramp signal reaches the preset upper limit of the swing, and to count the number of slopes contained in the adaptive ramp signal; and to generate a control signal for enabling the dynamic ramp generator and the column readout circuit.

[0019] As a further improvement of the present invention, the column readout circuit is composed of a column-level comparator, a column-level counter, a first latch array, a second latch array and a CDS module. Among them, the column-level comparator is used to use various ramp signals generated by the dynamic ramp generator to complete the reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization of each pixel unit. The column-level counter is used to generate the quantization values ​​of the reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization stages according to the output of the column-level comparator, which are recorded as K1, K2 and K3. The first latch array is used to latch the K1 of each pixel unit; the second latch array is used to first store the K2 of each pixel unit, and then overwrite K2 when any pixel unit generates K3. The CDS module is used to generate the final pixel value K of each pixel unit according to the following formula:

[0020] .

[0021] As a further improvement of the present invention, the column-level comparator is formed by cascading a preamplifier, a dynamic latch comparator and a buffer-level circuit. The preamplifier is obtained by cascading three operational amplifiers. Among them, the enable signal of each operational amplifier is EN; the value of EN depends on whether pixel multi-sampling quantization is required and whether pixel multi-sampling quantization is completed. The enable signal of the dynamic latch comparator is CLK-EN; CLK-EN is obtained by inverting EN and performing an OR operation with the clock signal CLK.

[0022] As a further improvement of the present invention, the quantization logic of the globally synchronous and locally asynchronous single slope ADC is as follows:

[0023] 1. Reset signal quantization stage

[0024] The dynamic ramp generator generates a standard ramp signal; the column readout circuit obtains the value K1 of each pixel unit in the same row at the reset signal quantization stage.

[0025] 2. Pixel single full-range quantization stage

[0026] The dynamic ramp generator generates a full-scale ramp signal; the column readout circuit obtains the value K2 of each pixel unit in the same row in the pixel single full-scale quantization stage.

[0027] 3. Pixel Multi-sampling Quantization Stage

[0028] The row judgment module obtains K2 of all pixel units, determines the swing amplitude of the adaptive ramp signal according to the K2, and controls the dynamic ramp generator to generate the required adaptive ramp signal with the specified swing amplitude;

[0029] The column judgment module distinguishes different situations according to K2 of each pixel unit in turn and makes the following decisions:

[0030] (1) If K2 of all pixel units in the current row is greater than V lt , then the pixel multi-sampling quantization task of all columns is terminated; the dynamic ramp generator and the column readout circuits of all columns are turned off until the preset standard conversion time is reached;

[0031] (2) If there are some columns of pixel units whose K2 is greater than V lt , then the pixel multi-sampling quantization task of the corresponding column is ended; the column readout circuit of the corresponding column is turned off until the preset standard conversion time is reached;

[0032] (3) If there are some columns of pixel units whose K2 is not greater than V lt , after the pixel multi-sampling quantization task of the corresponding column is completed; turn off the dynamic ramp generator and the column readout circuits of all columns until the preset standard conversion time is reached;

[0033] The column readout circuit latches K1 and K2, and overwrites K2 when generating K3; then combines K1 and K2 or K1 and K3 to generate the final pixel value K of each pixel unit.

[0034] The present invention also includes a CMOS image sensor, which includes a pixel array and uses the globally synchronous and locally asynchronous single-slope ADC as described above.

[0035] The technical solution provided by the present invention has the following beneficial effects:

[0036] The present invention designs a new globally synchronous and locally asynchronous single slope ADC based on the adaptive correlated multi-sampling technology. Due to the use of the adaptive correlated multi-sampling technology, the circuit shortens the effective time of multiple sampling in asynchronous timing. On this basis, the present invention also introduces a low power consumption mode for the circuit in asynchronous timing. On the one hand, it realizes the purpose of selectively shutting down part of the circuit at different stages according to different situations, thereby effectively reducing the total power consumption of the circuit. On the other hand, it can ensure that the whole circuit achieves the effect of consistent overall frame rate in different quantization tasks, thereby realizing global synchronization, improving the reliability of the circuit, and solving the problem of poor practicality of only asynchronous timing in CIS.

[0037] In addition, the globally synchronous and locally asynchronous single-slope ADC designed by the present invention only uses one dynamic ramp generator, and utilizes the row judgment module and the column judgment module to enable it to generate the required standard ramp, full-scale ramp and adaptive ramp at different stages. This avoids the problem of slope mismatch when multiple ramp generators are used in the traditional single-slope ADC circuit. Compared with the two-step ADC, the single-slope ADC of the present invention does not need to temporarily store the coarse quantization voltage, avoiding the problem of insufficient precision of the temporarily stored voltage value. In addition, the row / column light intensity can be directly determined by the quantization result of the pixel single full-scale quantization stage, without the need to introduce an additional judgment module, reducing the complexity of the circuit and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a working timing diagram of the globally synchronous and locally asynchronous single-slope ADC provided in Example 1 of the present invention.

[0039] Figure 2 This is a circuit architecture diagram of a globally synchronous and locally asynchronous single-slope ADC provided in Example 1 of the present invention.

[0040] Figure 3 This is a circuit diagram of the current steering ramp generator used in Example 1 of the present invention.

[0041] Figure 4 This is a circuit schematic diagram of a row judgment module used in Embodiment 1 of the present invention.

[0042] Figure 5 This is a circuit schematic diagram of the column judgment module used in Embodiment 1 of the present invention.

[0043] Figure 6 This is a circuit diagram of a column-level comparator used in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0045] Example 1

[0046] The present embodiment provides a globally synchronous and locally asynchronous single slope ADC, which uses adaptive correlated multi-sampling technology to quantize the outputs of all pixel units in the CIS. In the present embodiment, each round of quantization process is synchronously implemented between the pixel units of each column in the same row in the pixel array. After the task is completed, the pixel value K of all pixel units in the row can be obtained. For all single slope ADCs using adaptive correlated multi-sampling technology, the quantization process usually includes three stages: reset signal quantization, pixel single full-scale quantization, and pixel multi-sampling quantization.

[0047] In the reset signal quantization stage (Phase 1), it is necessary to obtain the precise value of the reset signal output by each pixel unit. At this time, the ramp generator will generate a standard ramp signal, and then perform the first round of quantization on the reset signal of the pixel unit through the standard ramp to obtain the quantized value of the reset signal. It is assumed that the upper limit of the swing of the ramp signal corresponding to the range of the quantization process is V FS , the standard ramp signal swing is usually 3 / 4V FS To V FS The reset signal quantization stage needs to obtain the precise value of the reset signal, and repeated sampling is also required in this stage. Therefore, the standard ramp signal usually contains multiple (typically 4) swings in the range of 3 / 4V. FS To V FS Continuous small slopes in between.

[0048] The pixel single full-scale quantization stage (Phase 2) is also called the ambient light detection stage. That is, in this stage, the circuit will use a full-scale ramp with a repetition number of 1 to scan all pixel units in the entire row at one time to obtain the approximate range of the quantization results of each pixel signal. Then, based on the approximate distribution of the pixel values ​​of each pixel unit, it is judged whether the ambient light corresponding to each pixel is strong. If the pixel values ​​of all pixels are large, it means that the ambient light at this time is relatively strong, and there is less noise information in the quantized results, so there is no need to perform correlated multi-sampling processing. When the value of the pixel signal is detected to be small, it means that the ambient light at this time is weak, and correlated multi-sampling is required to eliminate the error of the full-scale ramp quantization result. A threshold voltage is usually set when judging the intensity of ambient light, denoted as V lt , and then according to the minimum value V of the pixel signal in the same row min With V lt The magnitude relationship of the threshold voltage V lt Usually set to V FS Half of V lt =1 / 2V FS .

[0049] The main task of the pixel multi-sampling quantization stage (Phase 3) is to perform correlated multi-sampling on the pixel units in any row when there are pixel units whose quantization results are less than the threshold voltage. Specifically, in this stage, the ramp generator will again generate an adaptive ramp with a swing that is adapted to the distribution range of the quantization results of the pixel units in the current row in the previous stage. Like the standard ramp signal, the adaptive ramp signal is also a ramp signal including multiple continuous small ramps. The adaptive ramp signal can be used to perform correlated multi-sampling of the third stage on all pixel units in the row. Then, a more accurate pixel signal quantization result of each pixel unit can be obtained. Finally, the pixel value of each pixel unit can be calculated based on the reset signal and the quantization result of the pixel signal.

[0050] It should be noted that: for each pixel unit, the standard ramp signal and full-scale ramp signal used in the reset signal quantization process of the first stage and the pixel single full-scale quantization process of the second stage are completely consistent, and this process is a synchronous timing. For the third stage, since the distribution range of pixel values ​​of pixel units in different rows is usually not fixed, the adaptive ramp signals used in each row are usually inconsistent, which results in the ramp signal swing range being not fixed when the circuit performs the third stage quantization on each row, so this timing process also belongs to asynchronous timing.

[0051] Specifically, if Figure 1As shown, in order to shorten the conversion time and reduce the circuit power consumption, the selection of the swing amplitude of the adaptive ramp in the third stage of this embodiment is divided into the following cases: (1) Assuming that the quantized value of each pixel signal obtained in the second stage is just between 0 and 1 / 2V FS If the generated adaptive ramp signal has a swing range of 0 to 1 / 2V, FS (2)Assuming that the quantized values ​​of all pixel signals obtained in the second stage are all within 1 / 2V FS Below, the swing range of the generated adaptive ramp signal is also set to the maximum value V of the quantization result of the previous stage min and minimum value V max (3) Assuming that the quantized values ​​of the pixel signals obtained in the second stage are between 1 / 2V FS Above, some are at 1 / 2V FS Below, the swing range of the generated adaptive ramp signal is within V min and 1 / 2V FS Between (more than 1 / 2V FS The part indicates that the ambient light intensity is high and no repeated quantization is required). (4) Assuming that the quantized values ​​of the pixel signals obtained in the second stage are all within 1 / 2V FS As described above, no adaptive ramp signal is generated, and the pixel units in this row do not need to perform adaptive correlated multi-sampling.

[0052] Combination Figure 1 From the working sequence, we can find that when the circuit quantizes the pixel units in different rows, the time spent by each row of pixel units in the third stage is inconsistent due to the different swing amplitudes of the adaptive ramp signal used in the third stage. Among them, when adaptive correlated multi-sampling is not required, the total conversion time of the circuit is the shortest. FS When adaptive correlated multi-sampling is performed on each pixel unit within the range, the total conversion time of the circuit is the longest. The difference in total conversion time will cause the timing of the entire circuit to be chaotic, which is not conducive to circuit design and normal operation.

[0053] In order to solve the above-mentioned timing asynchrony problem, Figure 1 As shown, the solution proposed in this embodiment is: to use a swing range of 0 to V ltThe total conversion time consumed by the adaptive ramp signal during the pixel multi-sampling quantization stage is used as the standard conversion time. When the total conversion time spent by the pixel unit of any row after the pixel multi-sampling quantization task is completed does not reach the standard conversion time, an idle stage (Phase 4) is added after this stage. In this stage, most modules in the circuit (such as the ramp generator and the column readout circuit) remain closed until the standard conversion time is reached, and the next round of quantization is performed. After this improvement, although the single slope ADC is "locally asynchronous" in Phase 3, it can still maintain "global synchronization" throughout the quantization process.

[0054] On the basis of the above improvements, in order to further reduce the power consumption of the circuit, this embodiment also improves the quantization logic of the circuit in Phase 3. In the traditional adaptive correlated multi-sampling technology, after the single slope ADC identifies the signal distribution of each pixel unit in Phase 2 and generates an adaptive ramp signal, it will use the adaptive ramp signal to perform correlated multi-sampling quantization on all pixel units in the row in Phase 3, which means that as long as there is a pixel unit in a row that needs correlated multi-sampling (the pixel value is less than the threshold voltage), all pixel units need to be "forced" to perform correlated multi-sampling. In this embodiment, this strategy is changed, and a column judgment module is added. This module will re-judge whether each pixel unit needs to perform adaptive correlated multi-sampling in Phase 3. If yes, it will be executed, otherwise it will not be executed, and the column readout circuit of the corresponding column will be turned off.

[0055] It should be emphasized that: when all columns have completed the task of ending Phase 3 but the standard conversion time has not been reached, the single slope ADC designed in this embodiment will turn off the ramp generator and the column readout circuit at the same time. When the column judgment module determines that a certain column does not need to perform correlated multi-sampling, it will only turn off the column readout circuit of the row until the preset standard conversion time is reached. The latter will not turn off the ramp generator, so it will not affect the normal operation of those columns that need to perform correlated multi-sampling.

[0056] In order to realize the above circuit functions, the hardware design of the global synchronous and local asynchronous single slope ADC provided in this embodiment is as follows: Figure 2 As shown, specifically, the single slope ADC includes: a timing control circuit, a dynamic slope generator, a row judgment module, a column readout circuit and a column judgment module.

[0057] Among them, the timing control circuit is used to generate a global clock control signal that keeps the total conversion time of each pixel unit consistent during the quantization process. During the quantization process of each row of the pixel array, the global clock control signal can control the overall circuit to complete the related tasks of Phase 1, Phase 2 and Phase 3 in sequence, and after the task of Phase 3 is completed, it is determined according to the specific situation whether the circuit needs to be switched to a low-power idle mode, and then after waiting for the end of Phase 4, the start of the quantization task of the next row of pixel units is triggered.

[0058] The dynamic ramp generator is used to generate the required standard ramp signal, full-scale ramp signal and adaptive ramp signal in three different quantization stages. In particular, unlike the traditional dynamic ramp generators that can generate ramp signals with required swing amplitudes, the dynamic ramp generator of this embodiment adds a shutdown mechanism to stop the output of the dynamic ramp generator in Phase 4, so that it is in a low-power idle mode.

[0059] The row judgment module is used to obtain the full-scale quantization results of all pixel units in the same row in the pixel single full-scale quantization stage and identify the maximum value V min and minimum value V max , then according to V min and V max The threshold voltage V that represents the light intensity lt The relationship between the adaptive ramp and the ramp amplitude range is determined and sent to the dynamic ramp generator.

[0060] Specifically, in the solution of this embodiment, since the threshold voltage V lt Set to the upper limit voltage V FS Therefore, the row judgment module can actually work according to the V min The value of the highest bit is used to determine whether an adaptive ramp needs to be generated. For example, when V min When the highest bit is 1, it means V min ≥V lt At this time, there is no need to perform the Phase 3 task and generate an adaptive ramp signal. min When the highest bit is 0, it means V min <V lt At this time, the Phase 3 task needs to be executed, and the swing range of the generated adaptive ramp signal needs to be further combined with V min 、V max and V lt Specifically, the logic for generating the swing range is: V min As the lower limit of the adaptive ramp signal, V max and V ltThe smaller one of them serves as the upper limit of the swing of the adaptive ramp signal.

[0061] The column readout circuit is used to perform reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization on the output of the pixel unit in three quantization stages using three types of ramp signals generated by a dynamic ramp generator, and generate the final pixel value by combining the quantization results of each stage.

[0062] The column judgment module is used to first obtain the full-scale quantization results of each pixel unit in each column during the pixel multi-sampling quantization stage, and then generate an enable signal for controlling the dynamic ramp generator and the column readout circuit. This achieves: (1) If the full-scale quantization result of any column pixel unit is greater than V lt , then the multi-sampling quantization task of the pixel in the current column is terminated directly and the column readout circuit of the current column is turned off; (2) If the full-scale quantization result of any column pixel unit is not greater than V lt , then the pixel multi-sampling quantization task of the current column is performed according to the generated adaptive ramp signal; (3) After the pixel multi-sampling quantization tasks of all columns are completed, the ramp generator and the column readout circuits of all columns are turned off, so that the circuit is in idle mode until the preset standard conversion time is reached.

[0063] In order to make the circuit design of the globally synchronous and locally asynchronous single slope ADC provided in this embodiment clearer, the circuit design of several core modules is described in detail below, taking a single slope ADC with a 10-bit quantization accuracy level as an example:

[0064] 1. Dynamic ramp generator

[0065] like Figure 2 As shown, the dynamic ramp generator in this embodiment includes a current steering ramp generator, a two-choice selector, a first counter and a second counter; wherein a current steering DAC structure combining a thermometer code and a binary code is adopted. The slope accuracy is 10 bits, and the output ramp signal is connected to the negative input terminal of the comparator in the column readout circuit. The lower 4 bits of the ramp signal are in the form of binary coding, which can reduce the number of thermometer coding bits, thereby reducing the area of ​​the thermometer coding circuit; the upper 6 bits are in the form of thermometer coding, which can reduce the noise generated by too many flipping bits during the carry process. The two-choice selector, the first counter and the second counter are all 10-bit devices. The input terminals of the two-choice selector are respectively connected to the first counter and the second counter, and the output terminal is connected to the current steering ramp generator.

[0066] The first counter stores the first code and the second code (Q0-Q9) for controlling the current steering ramp generator to generate a standard ramp with a fixed swing amplitude and a full-scale ramp. The second counter is used to store the third code (Q10 ~Q 19 ). The first code and the second code stored in the first counter are actually fixed codes, and the two remain unchanged during the circuit application process. The third code pre-stored in the second counter needs to be dynamically adjusted according to the swing range of the adaptive ramp signal determined during the quantization process of each row of pixel units. The two-to-one selector selects the corresponding code at different quantization stages to generate the required standard ramp signal, full-scale ramp signal or adaptive ramp signal.

[0067] Specifically, the 10-bit precision current steering ramp generator used in this embodiment is a switch-controllable current steering ramp generator. Figure 3 As shown, it is composed of a current steering DAC, an enable switch array, a negative feedback circuit and a unit gain buffer. Among them, the current steering DAC is composed of multiple current sources, an output switch array, and resistors R1~R2. The current steering in the single slope ADC with 10-bit quantization accuracy of this embodiment includes 67 current sources, and the outputs of the first four current sources are i0, 2i0, 4i0, and 8i0 respectively; the outputs of the last 63 current sources are all 16i0. In the current steering ramp generator, the output of each current source is divided into two paths, one of which is connected to the upper end of R1 through a group of independent transmission gates in the output switch array and the enable switch array in turn, and the other is connected to the upper end of R2 through another group of independent transmission gates in the output switch array and the enable switch array in turn.

[0068] The negative feedback circuit is connected at the junction of R1 and R2, thereby clamping the initial voltage of the generated ramp signal to a specified fixed value, such as V x The unit gain buffer is connected between R1 and the current source of the final stage, and outputs a ramp signal that starts from a fixed value and increases at a fixed slope. Ideally, the positive output voltage of the current steering DAC of this embodiment can output a ramp signal from 0 V to 1.5 V, thereby meeting the quantization task of the pixel unit output signal in the interval of 0.5~1.5 V.

[0069] Specifically, the negative feedback circuit is composed of an operational amplifier A1, an NMOS tube N0 and a capacitor C0; wherein the negative input terminal of A1 is connected to V x ; The positive input of A1, the drain of N0 and one end of C0 are connected to the lower ends of R1 and R2; The output of A1 is connected to the other end of C0 and the gate of N0; The source of N0 is grounded. The unity gain buffer uses an operational amplifier A2; The positive input of A2 is connected to the upper end of R2; The inverting input of A2 is connected to the output and is used to output the generated ramp signal.

[0070] In particular, Figure 3In the normal case, the enable signal EN controls all 134 transmission gates in the enable switch array to be turned on. When Phase 3 is over, the enable signal EN can control all 134 transmission gates in the enable switch array to be turned off, thereby disconnecting the path between each current source in the current steering DAC and the output port below, so as to reduce the total power consumption of the circuit in the remaining cycle.

[0071] 2. Row Judgment Module

[0072] The function of the row judgment module in this embodiment is to find the maximum and minimum values ​​from the full-scale single quantization results of all columns after Phase 2 ends, and then determine whether it is necessary to generate an adaptive ramp signal of Phase 3, and determine the swing of the generated adaptive ramp signal.

[0073] Therefore, if Figure 4 As shown, the row judgment module includes a maximum value search circuit, a minimum value search circuit and a swing amplitude generation module. The maximum value search circuit is composed of a multi-level AND gate, a multi-bit counter and a subtractor; and is used to identify and output the maximum value V according to the full-scale quantization results of the pixel units of all columns in the same row. max The minimum value search circuit is composed of a multi-stage OR gate and a multi-bit counter; and is used to identify and output the minimum value V according to the full-scale quantization results of the pixel units in all columns in the same row. min The swing generation module is implemented by a logic circuit, which is used to convert V min As the lower limit of the adaptive ramp signal, V max and V lt The smaller one of them serves as the upper limit of the swing of the adaptive ramp signal.

[0074] In the actual circuit, each input end of the multi-stage AND gate in the maximum value search circuit is connected to the output end of the comparator in the column readout circuit of each column, that is: C1~C n The output end of the multi-stage AND gate is connected to the input end of the multi-bit counter, and the output end of the multi-bit counter is connected to the input end of the subtractor; the output end of the subtractor is used to output the maximum value of the quantization results of each pixel unit in the same row.

[0075] Correspondingly, the minimum value search unit is composed of a multi-stage OR gate and a multi-bit counter. The input terminals of the multi-stage OR gate are respectively connected to the output terminals of the comparators in the column readout circuit of each column; the output terminal of the multi-stage OR gate is connected to the input terminal of the multi-bit counter, and the output terminal of the multi-bit counter is used to output the minimum value of the primary quantization results of each pixel unit in the same row.

[0076] 3. Column Judgment Module

[0077] like Figure 5 As shown, the column judgment module provided in this embodiment is composed of an initial value preset module and a final value judgment module. The initial value preset module is used to write the lower limit of the swing into the second counter as the initial voltage of the generated adaptive ramp signal. The final value judgment module is used to judge whether each slope in the adaptive ramp signal reaches the preset upper limit of the swing, and count the number of slopes contained in the adaptive ramp signal; and generate a control signal for enabling the dynamic ramp generator and the column readout circuit.

[0078] Specifically, the initial value preset module includes two 10-bit two-to-one selectors to control the second counter to reset to the minimum value X9~X0 (XB9~XB0 is the inverse of X9~X0) in Phase 3. The output signal Q19~Q10 of the output end of the second counter is transmitted to the final value judgment module.

[0079] The final value judgment module consists of a valve, two T flip-flops TFF1 and TFF2, a third counter, a fourth counter, a 10-bit two-to-one selector, 18 XOR gates, 4 AND gates, and a buffer. Among them, the output signal of the second counter is connected to a 10-bit AND gate after passing through 10 XOR gates. Among them, one end of the input end of these 10 XOR gates is connected to Q19~Q10, and the other end is determined by the control signal of the two-to-one selector to connect to Y9~Y0 or 0111111111. Therefore, when the value of the second counter is equal to the maximum value or 1 / 2VFS, that is, when the slope of Phase 3 reaches the end, L1=1. Therefore, in this scheme, L1 is used as a signal for the end of the adaptive slope in the multi-quantized pixel signal stage to control the number of times the adaptive slope is generated.

[0080] The output signal of the third counter is connected to a 5-bit AND gate after passing through 5 XOR gates to obtain L2; L2 is used as the signal for the start of the adaptive slope in the multiple quantization pixel signal stage, that is, to control the reset time before the adaptive slope starts. When the reset starts, the third counter starts counting, and when it reaches 30 CLKs corresponding to 11110, L2=1, so the reset ends and the adaptive slope starts to be generated.

[0081] L1 and L2 are connected to TFF1 through an OR gate. Since the T terminal is always connected to a high level, the output terminal signal flips whenever there is a rising edge at the CLK terminal. Therefore, the output Q terminal signal ctrl of TFF is 1 only in the reset stage in the middle of the adaptive ramp and after the multiple quantization pixel signal stages, and serves as the RB signal of the third counter and the CLK signal of the fourth counter.

[0082] The output of the fourth counter passes through a certain logic circuit to generate ctrl_all as the end signal of the multiple quantized pixel signal stage to control the termination of the entire asynchronous timing. When ctrl generates 4 rising edges, it means that the fourth adaptive slope ends, and the output of the AND gate after the XOR gate is 1. A buffer and an AND gate are added before connecting to TFF2 to prevent the problem of errors in the results caused by a certain delay in the flip of the digital signal.

[0083] 4. Column Readout Circuit

[0084] like Figure 2 As shown, the column readout circuit provided in this embodiment is composed of a column-level comparator, a column-level counter, a first latch array, a second latch array and a CDS module. Among them, the column-level comparator is used to use various ramp signals generated by the dynamic ramp generator to complete the reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization of each pixel unit. The column-level counter is used to generate the quantization values ​​of the reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization stages according to the output of the column-level comparator, which are recorded as K1, K2 and K3.

[0085] The first latch array is used to latch the quantization result K1 of the reset signal in each pixel unit quantized in Phase 1; the second latch array is used to store K2 obtained after the pixel signal of each pixel unit is initially quantized by the full-scale signal in Phase 2. Afterwards, if a column needs to perform the related multi-sampling task in Phase 3, K2 is overwritten by K3 obtained in Phase 3. If the related multi-sampling task in Phase 3 does not need to be performed, K2 obtained in Phase 2 is retained. The CDS module is used to synthesize the final pixel value K of each pixel unit according to the values ​​of K1, K2 or K1, K3 obtained by the first latch array and the second latch array in the entire quantization process. Specifically, the calculation formula of the pixel value K is as follows:

[0086] .

[0087] Taking into account the quantization error and column-to-column inconsistency problems introduced by the comparator due to the offset voltage, flip delay and other issues, the embodiment adopts the digital domain correlated double sampling technology (DCDS) to eliminate the error, and at the same time can eliminate most of the fixed pattern noise introduced by the column-level circuit itself. In the selection of the structure of the comparator, in order to reduce the offset voltage of the overall comparator and prevent the kick-back noise caused by the comparator flip from having a greater impact on the input signal, the column-level comparator of this embodiment selects a structure such as a pre-amplifier + dynamic latch comparator. Figure 6As shown, the column-level comparator in this embodiment is cascaded by a preamplifier, a dynamic latch comparator and a buffer stage circuit. Among them, the enable signal of each op amp is EN; the value of EN depends on whether pixel multi-sampling quantization is required and whether pixel multi-sampling quantization is completed. The enable signal of the dynamic latch comparator is CLK-EN; CLK-EN is obtained by inverting EN and performing an OR operation with the clock signal CLK.

[0088] exist Figure 6 In the column-level comparator shown, the pre-amplifier selects three-stage operational amplifiers for cascading to achieve high gain, and the positive feedback formed by the cross-coupling structure also improves the amplification speed. At the same time, a buffer stage is added to the output end of the dynamic latch comparator to stabilize the dual-end output voltage of the comparator. On this basis, this embodiment uses output offset elimination technology for the comparator to further reduce the offset voltage of the comparator to within 1 / 2LSB. When the column is in a range of high light intensity, there is no need to perform correlated multi-sampling operations, so the column enable signal EN turns off the pre-amplifier and the dynamic latch comparator; when the column is in a range of low light intensity, correlated multi-sampling is required, so after the multiple quantization pixel signal stages are completed, the column enable signal EN turns off the pre-amplifier and the dynamic latch comparator to reduce the total power consumption of the circuit.

[0089] Based on the globally synchronous and locally asynchronous single slope ADC shown above, the quantization logic is as follows:

[0090] 1. Reset signal quantization stage

[0091] The dynamic ramp generator generates a standard ramp signal; the column readout circuit obtains the value K1 of each pixel unit in the same row at the reset signal quantization stage.

[0092] 2. Pixel single full-range quantization stage

[0093] The dynamic ramp generator generates a full-scale ramp signal; the column readout circuit obtains the value K2 of each pixel unit in the same row in the pixel single full-scale quantization stage.

[0094] 3. Pixel Multi-sampling Quantization Stage

[0095] The row judgment module obtains K2 of all pixel units, determines the swing amplitude of the adaptive ramp signal according to the K2, and controls the dynamic ramp generator to generate the required adaptive ramp signal with the specified swing amplitude;

[0096] The column judgment module distinguishes different situations according to K2 of each pixel unit in turn and makes the following decisions:

[0097] (1) If K2 of all pixel units in the current row is greater than V lt, then the pixel multi-sampling quantization tasks of all columns are ended; the dynamic ramp generator and the column readout circuits of all columns are turned off until the preset standard conversion time is reached.

[0098] (2) If there are some columns of pixel units whose K2 is greater than V lt , then the pixel multi-sampling quantization task of the corresponding column is ended; the column readout circuit of the corresponding column is turned off until the preset standard conversion time is reached.

[0099] (3) If there are some columns of pixel units whose K2 is not greater than V lt , after the pixel multi-sampling quantization task of the corresponding column is completed; turn off the dynamic ramp generator and the column readout circuits of all columns until the preset standard conversion time is reached.

[0100] Finally, the column readout circuit latches K1 and K2, and overwrites K2 when generating K3; then combines K1 and K2 or K1 and K3 to generate the final pixel value K of each pixel unit.

[0101] Example 2

[0102] On the basis of the scheme of Example 1, this embodiment further provides a CMOS image sensor, which includes a pixel array, and in particular, it also adopts a globally synchronous and locally asynchronous single slope ADC as in Example 1. Therefore, the CMOS image sensor provided by this embodiment can, on the one hand, further maintain global timing synchronization and unify the overall frame rate of the CMOS image sensor on the basis of implementing adaptive correlated multi-sampling technology to improve the quantization accuracy of the CIS circuit and reduce noise, so as to make the circuit more reliable. On the other hand, the CMOS image sensor can also distinguish at the unit level whether each pixel unit needs to perform a correlated multi-sampling task in different quantization scenarios; and introduce a sleep mechanism in the dynamic ramp generator and the column readout circuit to further reduce the overall power consumption of the circuit.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A globally synchronous and locally asynchronous single slope ADC, which uses adaptive correlated multi-sampling technology to quantize the output of all pixel units in CIS, the quantization process includes three stages: reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization, characterized in that: The single slope ADC comprises: A timing control circuit, which is used to generate a global clock control signal so that the total conversion time of each pixel unit in the quantization process remains consistent; A dynamic ramp generator, which is used to generate required standard ramp signals, full-scale ramp signals and adaptive ramp signals in three different quantization stages respectively; The row judgment module is used to obtain the full-scale quantization results of all pixel units in the same row and identify the maximum value V min and minimum value V max , then according to V min and V max The threshold voltage V that represents the light intensity lt The relationship between the adaptive ramp and the adaptive ramp amplitude range is determined and sent to the dynamic ramp generator; A column readout circuit, which is used to perform reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization on the output of the pixel unit using the three types of ramp signals generated by the dynamic ramp generator in three quantization stages, and generate a final pixel value in combination with the quantization results of each stage; and The column judgment module is used to first obtain the full-scale quantization result of each pixel unit in each column in the pixel multi-sampling quantization stage, and then generate an enable signal for controlling the dynamic ramp generator and the column readout circuit, thereby achieving: (1) If the full-scale quantization result of any column pixel unit is greater than V lt , then the multi-sampling quantization task of the pixel in the current column is terminated directly and the column readout circuit of the current column is turned off; (2) If the full-scale quantization result of any column pixel unit is not greater than V lt , then the pixel multi-sampling quantization task of the current column is performed according to the generated adaptive ramp signal; (3) After the pixel multi-sampling quantization tasks of all columns are completed, the ramp generator and the column readout circuits of all columns are turned off, so that the circuit is in idle mode until the preset standard conversion time is reached.

2. The globally synchronous and locally asynchronous single slope ADC according to claim 1, wherein: The standard conversion time is for the adaptive ramp to swing from 0 to V lt The total time consumed by any pixel unit in the pixel multisampling quantization stage when .

3. The globally synchronous and locally asynchronous single slope ADC according to claim 1, wherein: The dynamic ramp generator comprises a current steering ramp generator, a two-to-one selector, a first counter and a second counter; the input end of the two-to-one selector is respectively connected to the first counter and the second counter, and the output end is connected to the current steering ramp generator; The first counter stores a first code and a second code for controlling the current steering ramp generator to generate a standard ramp and a full-scale ramp with a fixed swing amplitude; the second counter is used to store a third code that can control the current steering ramp generator to generate an adaptive ramp signal with a specified swing amplitude; the two-to-one selector selects the corresponding code in different quantization stages to generate the required standard ramp signal, full-scale ramp signal or adaptive ramp signal.

4. The globally synchronous and locally asynchronous single slope ADC according to claim 3, wherein: The current steering ramp generator is composed of a current steering DAC, an enable switch array, a negative feedback circuit and a unit gain buffer; the current steering DAC is composed of multiple current sources, an output switch array, and resistors R1-R2; the output of each current source is divided into two paths, one of which is connected to the upper end of R1 through a group of independent transmission gates in the output switch array and the enable switch array in sequence, and the other is connected to the upper end of R2 through another group of independent transmission gates in the output switch array and the enable switch array in sequence; The negative feedback circuit is connected at the intersection of R1 and R2, thereby clamping the initial voltage of the generated ramp signal to a fixed value; the unit gain buffer is connected between R1 and the current source of the final stage, thereby outputting a ramp signal that increases at a fixed slope starting from the fixed value.

5. The globally synchronous and locally asynchronous single slope ADC according to claim 4, characterized in that: The row judgment module includes a maximum value search circuit, a minimum value search circuit and a swing amplitude generation module; The maximum value search circuit is composed of a multi-stage AND gate, a multi-bit counter and a subtractor, and is used to identify and output the maximum value V according to the full-scale quantization results of the pixel units of all columns in the same row. max ; The minimum value search circuit is composed of a multi-stage OR gate and a multi-bit counter, and is used to identify and output the minimum value V according to the full-scale quantization results of the pixel units of all columns in the same row. min ; The swing amplitude generation module is implemented by a logic circuit, which is used to convert V min As the lower limit of the adaptive ramp signal, V max and V lt The smaller one of them serves as the upper limit of the swing of the adaptive ramp signal.

6. The globally synchronous and locally asynchronous single slope ADC of claim 4, wherein: The column judgment module is composed of an initial value preset module and a final value judgment module; The initial value preset module is used to write the lower limit of the swing amplitude into the second counter as the initial voltage of the generated adaptive ramp signal; The final value judgment module is used to judge whether each slope in the adaptive ramp signal reaches a preset swing upper limit, and to count the number of slopes contained in the adaptive ramp; and to generate a control signal for enabling the dynamic ramp generator and the column readout circuit.

7. The globally synchronous and locally asynchronous single slope ADC of claim 1, wherein: The column readout circuit is composed of a column-level comparator, a column-level counter, a first latch array, a second latch array and a CDS module; The column-level comparator is used to complete the reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization of each pixel unit by using various ramp signals generated by the dynamic ramp generator; The column-level counter is used to generate quantization values ​​of reset signal quantization, pixel single full-scale quantization and pixel multi-sampling quantization stages according to the output of the column-level comparator, which are denoted as K1, K2 and K3; The first latch array is used to latch K1 of each pixel unit; the second latch array is used to first store K2 of each pixel unit, and then overwrite K2 when any pixel unit generates K3: The CDS module is used to generate the final pixel value K of each pixel unit according to the following formula: 。 8. The globally synchronous and locally asynchronous single slope ADC of claim 7, wherein: The column-level comparator is formed by cascading a preamplifier, a dynamic latch comparator and a buffer-level circuit; the preamplifier is obtained by cascading three operational amplifiers; wherein the enable signal of each operational amplifier is EN; the value of EN depends on whether pixel multi-sampling quantization is required and whether pixel multi-sampling quantization is completed; the enable signal of the dynamic latch comparator is CLK-EN; CLK-EN is obtained by inverting EN and performing an OR operation with the clock signal CLK.

9. The globally synchronous and locally asynchronous single slope ADC of claim 1, wherein: The quantification logic is as follows:

1. Reset signal quantization stage The dynamic ramp generator generates a standard ramp signal; the column readout circuit obtains the value K1 of each pixel unit in the same row at the reset signal quantization stage; 2. Pixel single full-range quantization stage The dynamic ramp generator generates a full-scale ramp signal; the column readout circuit obtains the value K2 of each pixel unit in the same row at the pixel single full-scale quantization stage; 3. Pixel Multi-sampling Quantization Stage The row judgment module obtains K2 of all pixel units, determines the swing amplitude of the adaptive ramp signal according to the K2, and controls the dynamic ramp generator to generate the required adaptive ramp signal with the specified swing amplitude; The column judgment module distinguishes different situations according to K2 of each pixel unit in turn and makes the following decisions: (1) If K2 of all pixel units in the current row is greater than V lt , then the pixel multi-sampling quantization task of all columns is terminated; the dynamic ramp generator and the column readout circuits of all columns are turned off until the preset standard conversion time is reached; (2) If there are some columns of pixel units whose K2 is greater than V lt , then the pixel multi-sampling quantization task of the corresponding column is ended; the column readout circuit of the corresponding column is turned off until the preset standard conversion time is reached; (3) If there are some columns of pixel units whose K2 is not greater than V lt , after the pixel multi-sampling quantization task of the corresponding column is completed; turn off the dynamic ramp generator and the column readout circuits of all columns until the preset standard conversion time is reached; The column readout circuit latches K1 and K2, and overwrites K2 when generating K3; then combines K1 and K2 or K1 and K3 to generate the final pixel value K of each pixel unit.

10. A CMOS image sensor comprising a pixel array, characterized in that: It adopts the globally synchronous and locally asynchronous single slope ADC as described in any one of claims 1-9.

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