Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The invention provides a semiconductor memory device with improved manufacturability and a method for manufacturing the semiconductor memory device. According to one embodiment, a semiconductor memory device includes a stacked body and a plurality of contacts. The plurality of stacked bodies includes a plurality of gate electrode layers. The plurality of contacts includes a first contact, a second contact, and a third contact. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer disposed on a first side with respect to the first gate electrode layer, and a third gate electrode layer disposed on the first side with respect to the second gate electrode layer. The laminated body includes a conductive first protruding portion that protrudes from the first gate electrode layer toward the first contact, and a conductive second protruding portion that protrudes from the third gate electrode layer toward the third contact. The first contact is in contact with the first protrusion. The second contact is in contact with the second gate electrode layer. The third contact is in contact with the second protrusion.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2023-111719 (filing date: July 6, 2023). The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor storage device and a method for manufacturing the semiconductor storage device. Background Art

[0004] There is known a semiconductor memory device including a stacked body in which a plurality of gate electrode layers and a plurality of insulating layers are alternately stacked one by one, and a plurality of contacts provided on the stacked body. Summary of the invention

[0005] One embodiment provides a semiconductor memory device with improved manufacturability and a method for manufacturing the semiconductor memory device.

[0006] A semiconductor storage device according to one embodiment includes a stacked body and a plurality of contacts. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are stacked alternately layer by layer in a first direction. The plurality of contacts extend in the first direction, respectively. The stacked body includes a first region, a second region, and a third region. The first region, the second region, and the third region are arranged in the order of the first region, the second region, and the third region in a second direction different from the first direction. The plurality of contacts include a first contact arranged in the first region, a second contact arranged in the second region, and a third contact arranged in the third region. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer arranged on the first side relative to the first gate electrode layer in the first direction, and a third gate electrode layer arranged on the first side relative to the second gate electrode layer. The laminate includes a conductive first protrusion protruding from the first gate electrode layer toward the first contact, and a conductive second protrusion protruding from the third gate electrode layer toward the third contact. The first contact is in contact with the first protrusion. The second contact is in contact with the second gate electrode layer. The third contact is in contact with the second protrusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a partial configuration of a semiconductor memory device according to the first embodiment.

[0008] Figure 2This is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment.

[0009] Figure 3 It is a cross-sectional view showing a part of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 Yes Figure 3 : is a cross-sectional view showing an enlarged view of the area surrounded by line F4 shown in FIG.

[0011] Figure 5 yes Figure 4 A cross-sectional view of the semiconductor memory device shown in FIG. 1 taken along line F5 - F5.

[0012] Figure 6 It is a cross-sectional view showing a step region of the semiconductor memory device according to the first embodiment.

[0013] Figure 7 This is a cross-sectional view showing a part of the step region in an enlarged manner according to the first embodiment.

[0014] Fig. 8A These are diagrams for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Figure 8B These are diagrams for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0016] Fig. 9 FIG. 1 is a cross-sectional view showing a step region of a semiconductor memory device according to a modification of the first embodiment.

[0017] Fig.10 It is a cross-sectional view showing a step region of the semiconductor memory device according to the second embodiment.

[0018] Fig.11A It is a diagram for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0019] Fig. 11B It is a diagram for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0020] Fig. 11C It is a diagram for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0021] Fig.12 It is a perspective cross-sectional view showing a step region of a semiconductor memory device according to a third embodiment.

[0022] Fig.13 FIG. 1 is a cross-sectional view showing a step region of a semiconductor memory device according to a modification of the embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are marked with the same symbols. In addition, repeated descriptions of these components are sometimes omitted. In the following description, for reference symbols with numbers or letters at the end for distinguishing, the numbers or letters at the end are sometimes omitted when there is no need to distinguish them from each other.

[0024] In this application, the terms are defined as follows. "Parallel", "orthogonal", or "same" may include "approximately parallel", "approximately orthogonal", or "approximately the same", respectively. The so-called "connection" is not limited to mechanical connection, but may include electrical connection. In other words, the so-called "connection" is not limited to the situation where multiple elements are directly connected, but may include the situation where multiple elements are connected with other elements in between.

[0025] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the word line WL described later extends (see Figure 3 ). The -X direction is the direction opposite to the +X direction. In the case where the +X direction and the -X direction are not distinguished, it is simply referred to as the X direction. The +Y direction is a direction intersecting (for example, orthogonal to) the X direction. The +Y direction is the direction in which the bit line BL extends (refer to Figure 3 ). The -Y direction is the direction opposite to the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (for example, is orthogonal to) the X direction and the Y direction. The +Z direction is a direction from the bit line BL described later toward the stacked body 40 (refer to Figure 3 ). The -Z direction is the direction opposite to the +Z direction. When the +Z direction and the -Z direction are not distinguished, it is simply referred to as the Z direction.

[0026] In the following description, the +Z direction side is sometimes referred to as "upper" and the -Z direction side is sometimes referred to as "lower". In addition, in the following description, the position in the Z direction is sometimes referred to as "height". However, these expressions are for convenience and do not specify the direction of gravity. The Z direction is an example of the "first direction". The +Z direction side is an example of the "first side". The -Z direction side is an example of the "second side". The X direction is an example of the "second direction". In the drawings described below, illustrations of structures that are not related to the description are sometimes omitted.

[0027] (First embodiment)

[0028] <1. Configuration of semiconductor memory device>

[0029] Figure 11 is a block diagram showing a part of the structure of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, a NAND (Not AND) type flash memory. The semiconductor memory device 1 can be connected to an external host device and used as a storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0030] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer greater than or equal to 1). The block BLK is a collection of memory cell transistors. The block BLK is used as a data erasing unit. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0031] The command register 12 stores the command CMD received by the semiconductor memory device 1 from the host device. The address register 13 stores the address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used to select the block BLK, the word line, and the bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 performs a data write operation, a data read operation, or an erase operation based on the command CMD stored in the command register 12.

[0032] The driver module 15 includes a voltage generating circuit, and generates voltages used for various operations of the semiconductor memory device 1. The row decoder module 16 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line. In the write operation, the sense amplifier module 17 applies the required voltage to each bit line. In the read operation, the sense amplifier module 17 determines the data value stored in each memory cell transistor based on the voltage of each bit line, and transmits the determination result to the host device in the form of read data DAT.

[0033] <2. Electrical structure of memory cell array>

[0034] Figure 2 1 is a diagram showing an equivalent circuit of a part of the memory cell array 11 . Figure 2 1 block BLK included in the memory cell array 11 is shown. The block BLK includes a plurality of (eg, four) strings STR0 to STR3.

[0035] Each string STR includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than 1), respectively. Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MTn (n is an integer greater than 1), one or more drain side selection transistors STD, and one or more source side selection transistors STS.

[0036] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. Each memory cell transistor MT accumulates charge in the charge storage unit according to the voltage applied to the control gate via the word line WL, thereby storing the data value non-volatilely.

[0037] The drain of the drain side selection transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain side selection transistor STD is connected to one end of the memory cell transistors MT0 to MTn connected in series. The control gate of the drain side selection transistor STD is connected to any one of the drain side selection gate lines SGD0 to SGD3. The drain side selection transistor STD is electrically connected to the row decoder module 16 via the drain side selection gate line SGD. The drain side selection transistor STD connects the NAND string NS to the bit line BL when a specified voltage is applied to the corresponding drain side selection gate line SGD.

[0038] The drain of the source side selection transistor STS is connected to the other end of the memory cell transistors MT0 to MTn connected in series. The source of the source side selection transistor STS is connected to the source line SL. The control gate of the source side selection transistor STS is connected to the source side selection gate line SGS. When a specified voltage is applied to the source side selection gate line SGS, the source side selection transistor STS connects the NAND string NS to the source line SL.

[0039] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn. In the same string STR, the control gates of the drain side selection transistors STD are commonly connected to the corresponding drain side selection gate lines SGD0 to SGD3. The control gates of the source side selection transistors STS are commonly connected to the source side selection gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS assigned the same column address in the multiple strings STR.

[0040] <3. Physical structure of semiconductor memory device>

[0041] Next, the physical structure of semiconductor memory device 1 will be described.

[0042] Figure 3 2 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 includes a first chip 2 and a second chip 3, for example.

[0043] <3.1 First Chip>

[0044] The first chip 2 is a circuit chip including a peripheral circuit and includes, for example, a semiconductor substrate 21 , a peripheral circuit 22 , an insulating portion 23 , and a plurality of pads 24 .

[0045] The semiconductor substrate 21 is a substrate that becomes the base of the first chip 2. At least a part of the semiconductor substrate 21 is in a plate shape along the X direction and the Y direction. The semiconductor substrate 21 is formed of a semiconductor material such as silicon, for example.

[0046] The peripheral circuit 22 is a circuit for making the memory cell array 11 function. The peripheral circuit 22 includes one or more of the command register 12, the address register 13, the control circuit 14, the driver module 15, the row decoder module 16, and the sense amplifier module 17. The peripheral circuit 22 includes, for example, a plurality of transistors 31, a plurality of contacts 32, a plurality of wiring layers 33, and a plurality of through holes 34.

[0047] The transistor 31 is provided on the semiconductor substrate 21. The contact 32 is conductive, extends in the Z direction, and is in contact with the source region, the drain region, or the gate electrode of the transistor 31. A plurality of wiring layers 33 are separately arranged at a plurality of heights. Each wiring layer 33 includes a plurality of wirings 33a extending in the X direction or the Y direction. The through hole 34 is an electrical connection portion extending in the Z direction in the first chip 2. The plurality of through holes 34 include, for example, a through hole 34 connecting two wirings 33a arranged at different heights, and a through hole 34 connecting the wiring 33a to the pad 24.

[0048] The insulating portion 23 covers the plurality of transistors 31, the plurality of contacts 32, the plurality of wiring layers 33, and the plurality of through holes 34. The plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the wiring 33a via the through hole 34.

[0049] <3.2 Second chip>

[0050] The second chip 3 is an array chip including the memory cell array 11. The second chip 3 includes, for example, the memory cell array 11, an insulating portion 35, and a plurality of pads 36. Here, the insulating portion 35 and the plurality of pads 36 are described, and the memory cell array 11 will be described later.

[0051] The insulating portion 35 covers the memory cell array 11. A plurality of pads 36 are provided on the surface of the insulating portion 35. Each pad 36 is electrically connected to a wiring (e.g., wiring 81 or wiring 83) included in a wiring portion 80 of the memory cell array 11 described later. In this embodiment, the plurality of pads 24 of the first chip 2 and the plurality of pads 36 of the second chip 3 are adjacently bonded together, so that the first chip 2 and the second chip 3 are integrated.

[0052] <4. Physical structure of memory cell array>

[0053] Next, the physical structure of the memory cell array 11 will be described.

[0054] like Figure 3 As shown, the memory cell array 11 has a stacked body 40, a source line SL, a plurality of memory columns MH, a plurality of bit lines BL, a plurality of contacts CH for the memory columns, a plurality of contacts VY for the memory columns, a plurality of contacts 70 for the conductive layer, and a wiring portion 80.

[0055] <4.1 Laminated body>

[0056] First, the layered body 40 will be described.

[0057] Figure 4 Yes Figure 3 1 is an enlarged cross-sectional view of a region surrounded by line F4 of semiconductor memory device 1 shown in FIG. Laminated body 40 includes a plurality of conductive layers 41, a plurality of insulating layers 42, and insulating portion 43. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately laminated layer by layer in the Z direction.

[0058] The conductive layers 41 extend along the X direction and the Y direction. Each conductive layer 41 includes a conductive material (first material) such as tungsten, molybdenum, or silicon doped with impurities. The conductive layer 41 is an example of a "gate electrode layer".

[0059] One or more (e.g., multiple) of the multiple conductive layers 41 located at the bottom function as a drain side selection gate line SGD. The drain side selection gate line SGD is provided in common with respect to multiple memory columns MH arranged in the X direction or the Y direction. The intersection of the drain side selection gate line SGD and the channel layer 52 (described later) of each memory column MH functions as the drain side selection transistor STD.

[0060] One or more (e.g., multiple) of the multiple conductive layers 41 located at the top function as a source side selection gate line SGS. The source side selection gate line SGS is commonly provided for multiple memory columns MH arranged in the X direction or the Y direction. The intersection of the source side selection gate line SGS and the channel layer 52 of each memory column MH functions as the source side selection transistor STS.

[0061] At least a portion of the remaining conductive layers 41 disposed between the conductive layers 41 functioning as the drain side selection gate line SGD and the source side selection gate line SGS among the plurality of conductive layers 41 functions as a word line WL. The word line WL is provided in common with respect to the plurality of storage columns MH arranged in the X direction and the Y direction. In the present embodiment, the intersection of the word line WL and the channel layer 52 of each storage column MH functions as a storage cell transistor MT. The storage cell transistor MT will be described in detail later.

[0062] In this embodiment, the lengths of the plurality of conductive layers 41 in the X direction are different from each other. For example, among the plurality of conductive layers 41, the closer the conductive layer 41 is to the +Z direction side, the greater the extension in the -X direction. Thus, the laminate 40 has a step region SR where the ends of the plurality of conductive layers 41 are arranged in a step-like manner. The step region SR is an example of a connection region where the plurality of contacts 70 are connected to the plurality of conductive layers 41.

[0063] The insulating layer 42 is an interlayer insulating film provided between two conductive layers 41 adjacent to each other in the Z direction to insulate the two conductive layers 41. The insulating layer 42 extends along the X direction and the Y direction. The insulating layer 42 is formed of a film containing silicon and oxygen, for example.

[0064] The insulating portion 43 is provided in the step region SR and covers the end portions of the plurality of conductive layers 41 arranged in a step shape. The insulating portion 43 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4).

[0065] <4.2 Source Line>

[0066] The source line SL is arranged above the laminate body 40. The source line SL is a conductive layer extending in the X direction and the Y direction. The source line SL includes a conductive material such as tungsten, molybdenum, or silicon doped with impurities.

[0067] <4.3 Storage column>

[0068] A plurality of memory columns MH are arranged in the X direction and the Y direction (refer to Figure 3 Each memory column MH extends in the Z direction in the laminate 40 and penetrates the laminate 40. The upper end of the memory column MH is connected to the source line SL. On the other hand, the lower end of each memory column MH is connected to a contact CH described later.

[0069] Figure 5 yes Figure 4 The memory pillar MH includes, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap 54 (see FIG. Figure 4 ).

[0070] The memory film 51 is provided on the outer peripheral side of the channel layer 52. The memory film 51 is located between the plurality of conductive layers 41 and the channel layer 52. The memory film 51 includes a blocking insulating film 61, a charge trapping film 62, and a tunnel insulating film 63, for example.

[0071] The blocking insulating film 61 is arranged between the multiple conductive layers 41 and the charge trapping film 62. The blocking insulating film 61 is an insulating film that suppresses reverse tunneling. Reverse tunneling is a phenomenon in which charges return from the word line WL to the charge trapping film 62. The blocking insulating film 61 is formed in a ring shape and extends in the Z direction. The blocking insulating film 61, for example, covers the entire length of the storage column MH in the Z direction. The blocking insulating film 61 is, for example, a laminated structure film formed by laminating multiple insulating films such as a film containing silicon and oxygen or a film containing metal and oxygen. An example of a film containing metal and oxygen is aluminum oxide. The blocking insulating film 61 may also include a high dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0072] The charge trapping film 62 is located between the blocking insulating film 61 and the tunnel insulating film 63. The charge trapping film 62 is formed in a ring shape and extends in the Z direction. The charge trapping film 62, for example, covers the entire length of the storage column MH in the Z direction. The charge trapping film 62 is a functional film that has a plurality of crystal defects (trapping levels) and can trap charges at the crystal defects. The charge trapping film 62 is formed, for example, of a film containing silicon and nitrogen. The portion of the charge trapping film 62 adjacent to each word line WL is an example of a "charge storage unit" that can store information by accumulating charges.

[0073] The tunnel insulating film 63 is provided between the channel layer 52 and the charge trapping film 62. The tunnel insulating film 63 is, for example, annular along the outer peripheral surface of the channel layer 52, and extends in the Z direction along the channel layer 52. The tunnel insulating film 63, for example, covers the entire length of the memory column MH in the Z direction. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge trapping film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0074] Thus, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed through the end of the word line WL adjacent to the memory pillar MH, the blocking insulating film 61, the charge trapping film 62, the tunnel insulating film 63, and the channel layer 52. In addition, the memory film 51 may also have a floating gate type charge storage part (floating gate electrode) as a charge storage part instead of the charge trapping film 62. The floating gate electrode is formed of, for example, silicon doped with impurities.

[0075] The insulating core 53 is disposed inside the channel layer 52. The insulating core 53 is buried in at least a portion of the channel layer 52. The insulating core 53 is formed of a film containing silicon and oxygen. A portion of the insulating core 53 is formed in a ring shape along the inner circumference of the channel layer 52. The insulating core 53 may also have a space portion (air gap) inside the insulating core 53. The insulating core 53 extends in the Z direction. For example, the insulating core 53 is spread over most of the storage column MH in the Z direction except for the lower end of the storage column MH (refer to Figure 4 ).

[0076] Secondly, back to Figure 4 , the cover 54 is described. The cover 54 is disposed below the insulating core 53. The cover 54 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover 54 may also be doped with impurities. The cover 54 is disposed on the inner peripheral side of the lower end of the storage film 51 and is formed integrally with the channel layer 52. The cover 54 simultaneously forms the lower end of the channel layer 52 and the lower end of the storage column MH. The contact CH is connected to the cover 54 in the Z direction.

[0077] <4.4 bit line>

[0078] Secondly, back to Figure 3 , the bit line BL is described.

[0079] The bit line BL is a wiring for selecting one memory column MH from a plurality of memory columns MH. The plurality of bit lines BL are arranged on the lower side relative to the stacked body 40. The plurality of bit lines BL are arranged in the X direction with intervals in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends in a manner passing under the corresponding plurality of memory columns MH.

[0080] When viewed from the Z direction, each bit line BL overlaps with a plurality of memory pillars MH (see Figure 6 Each bit line BL is connected to the channel layer 52 of the memory column MH via the contact VY and the contact CH. Thus, by combining the word line WL and the bit line BL, any memory cell transistor MT can be selected from a plurality of memory cell transistors MT arranged three-dimensionally.

[0081] <4.5 Contacts for conductive layers>

[0082] like Figure 3 As shown, the contact 70 is an electrical connection portion that electrically connects the conductive layer 41 to the wiring 83 (described later) included in the wiring portion 80. The plurality of contacts 70 are, for example, arranged in the step region SR of the laminate 40. The plurality of contacts 70 extend in the Z direction, and, for example, the lengths in the Z direction are different from each other. Each contact 70 includes a conductive material such as tungsten, molybdenum, or silicon doped with impurities. The upper end of each contact 70 is electrically connected to the corresponding conductive layer 41. The lower end of each contact 70 is electrically connected to the wiring 83 via a through hole 84 described later.

[0083] <4.6 Wiring section>

[0084] Next, the wiring section 80 will be described. The wiring section 80 is disposed, for example, between the laminated body 40 and the semiconductor substrate 21. The wiring section 80 includes, for example, a plurality of wirings 81, a plurality of through holes 82, a plurality of wirings 83, and a plurality of through holes 84.

[0085] The wiring 81 is an electrical connection portion that electrically connects the bit line BL to the pad 36. The plurality of wirings 81 are arranged, for example, below the plurality of bit lines BL. Each wiring 81 extends, for example, in the X direction or the Y direction. A through hole 82 that electrically connects the wiring 81 to the bit line BL is provided between the wiring 81 and the bit line BL.

[0086] The wiring 83 is an electrical connection portion that electrically connects the contact 70 for the conductive layer to the pad 36. The wiring 83 is electrically connected to the conductive layer 41 via the through hole 84 and the contact 70 for the conductive layer. A voltage is applied to the wiring 83 to select the conductive layer 41 (the word line WL, the drain side selection gate line SGD, or the source side selection gate line SGS).

[0087] <5. Structure of the step area>

[0088] Next, the structure of the step region SR will be described.

[0089] Figure 6 FIG. 4 is a cross-sectional view showing an enlarged view of the step region SR. Figure 6 In the following drawings, for convenience of explanation, the -Z direction is illustrated as the upper side, and the +Z direction is illustrated as the lower side.

[0090] like Figure 6 As shown, the step region SR includes, for example, the first to fourth regions R1, R2, R3, and R4. These regions are arranged in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4 in the -X direction. The first to fourth regions R1, R2, R3, and R4 are, for example, regions obtained by dividing the step region SR into four parts in the X direction. The sizes of the first to fourth regions R1, R2, R3, and R4 may be different from each other.

[0091] (Contacts of Groups 1 to 4)

[0092] like Figure 6 As shown, the plurality of contacts 70 extend in the Z direction, and the lengths in the Z direction are different from each other. For example, the closer the contact 70 is to the -X direction, the more it extends in the +Z direction. Each contact 70 is an example of a "columnar body".

[0093] The plurality of contacts 70 are separately arranged in the first to fourth regions R1, R2, R3, and R4. The plurality of contacts 70 include a plurality of contacts 70A of a first group CG1, a plurality of contacts 70B of a second group CG2, a plurality of contacts 70C of a third group CG3, and a plurality of contacts 70D of a fourth group CG4.

[0094] The plurality of contacts 70A of the first group CG1 are the plurality of contacts 70 arranged in the first region R1. Among the plurality of contacts 70A of the first group CG1, the closer the contact 70A is to the -X direction side in the first region R1, the more it extends in the +Z direction. One contact 70A included in the plurality of contacts 70A of the first group CG1 is an example of a "first contact".

[0095] The plurality of contacts 70B of the second group CG2 are the plurality of contacts 70 arranged in the second region R2. Among the plurality of contacts 70B of the second group CG2, the closer the contact 70B is to the -X direction side in the second region R2, the more it extends toward the +Z direction. One contact 70B included in the plurality of contacts 70B of the second group CG2 is an example of a "second contact".

[0096] The plurality of contacts 70C of the third group CG3 are the plurality of contacts 70 arranged in the third region R3. Among the plurality of contacts 70C of the third group CG3, the closer the contact 70C is to the -X direction side in the third region R3, the more it extends toward the +Z direction. Any one of the plurality of contacts 70C of the third group CG3 is an example of a "third contact".

[0097] The plurality of contacts 70D of the fourth group CG4 are the plurality of contacts 70 arranged in the fourth region R4. Among the plurality of contacts 70D of the fourth group CG4, the closer the contact 70D is to the -X direction side in the fourth region R4, the more it extends in the +Z direction. Any one of the plurality of contacts 70D included in the fourth group CG4 is an example of the "fourth contact".

[0098] (Conductive layers of the 1st to 4th groups)

[0099] like Figure 6 As shown, the plurality of conductive layers 41 include a plurality of conductive layers 41A of a first group LG1 , a plurality of conductive layers 41B of a second group LG2 , a plurality of conductive layers 41C of a third group LG3 , and a plurality of conductive layers 41D of a fourth group LG4 .

[0100] The plurality of conductive layers 41A of the first group LG1 are the plurality of conductive layers 41 corresponding to the plurality of contacts 70A of the first group CG1. In the present application, "corresponding" means being electrically connected to each other. Among the plurality of conductive layers 41A of the first group LG1, the closer the conductive layer 41 is to the +Z direction side, the more it extends in the -X direction. One conductive layer 41A (the conductive layer 41A corresponding to the first contact) included in the plurality of conductive layers 41A of the first group LG1 is an example of a "first gate electrode layer".

[0101] The plurality of conductive layers 41B of the second group LG2 are the plurality of conductive layers 41 corresponding to the plurality of contacts 70B of the second group CG2. The plurality of conductive layers 41B of the second group LG2 are arranged on the +Z direction side relative to the plurality of conductive layers 41A of the first group LG1. The plurality of conductive layers 41B of the second group LG2 are arranged between the plurality of conductive layers 41A of the first group LG1 and the plurality of conductive layers 41C of the third group LG3 in the Z direction. One conductive layer 41B (the conductive layer 41B corresponding to the second contact) included in the plurality of conductive layers 41B of the second group LG2 is an example of a “second gate electrode layer”.

[0102] The plurality of conductive layers 41C of the third group LG3 are the plurality of conductive layers 41 corresponding to the plurality of contacts 70C of the third group CG3. The plurality of conductive layers 41C of the third group LG3 are arranged on the +Z direction side relative to the plurality of conductive layers 41B of the second group LG2. The plurality of conductive layers 41C of the third group LG3 are arranged between the plurality of conductive layers 41B of the second group LG2 and the plurality of conductive layers 41D of the fourth group LG4 in the Z direction. One conductive layer 41C included in the plurality of conductive layers 41C of the third group LG3 (the conductive layer 41C corresponding to the third contact) is an example of a "third gate electrode layer".

[0103] The plurality of conductive layers 41D of the fourth group LG4 are the plurality of conductive layers 41 corresponding to the plurality of contacts 70D of the fourth group CG4. The plurality of conductive layers 41D of the fourth group LG4 are arranged on the +Z direction side relative to the plurality of conductive layers 41C of the third group LG3. One conductive layer 41D (the conductive layer 41D corresponding to the fourth contact) included in the plurality of conductive layers 41D of the fourth group LG4 is an example of a "fourth gate electrode layer".

[0104] (Conductive protrusion)

[0105] like Figure 6 As shown, the laminate 40 has a plurality of first protrusions 45 and a plurality of second protrusions 46 .

[0106] A plurality of first protrusions 45 are provided in the first region R1. The first protrusions 45 are conductive protrusions provided on the -Z direction side surface of the end of the conductive layer 41A of the first group LG1 and protruding from the conductive layer 41A in the -Z direction. The first protrusions 45 protrude from the conductive layer 41A toward the contact 70A included in the first group CG1 and contact the contact 70A. In other words, the first protrusions 45 are arranged between the conductive layer 41A and the contact 70A in the Z direction to electrically connect the conductive layer 41A and the contact 70A.

[0107] In the present embodiment, the first protrusion 45 is provided on each conductive layer of the plurality of conductive layers 41A of the first group LG1. Each contact 70A included in the plurality of contacts 70A of the first group CG1 is in contact with the first protrusion 45 provided on the conductive layer 41A corresponding to the contact 70A included in the plurality of conductive layers 41A of the first group LG1. In the present embodiment, the width in the X direction of one end in the -Z direction of the first protrusion 45 is the same as the width in the X direction of one end in the +Z direction of the contact 70A connected to the first protrusion 45.

[0108] A plurality of second protrusions 46 are provided in the third region R3. The second protrusions 46 are conductive protrusions provided on the -Z direction side surface of the end of the conductive layer 41C of the third group LG3 and protruding from the conductive layer 41C in the -Z direction. The second protrusions 46 protrude from the conductive layer 41C toward the contact 70C of the third group CG3 and contact the contact 70C. In other words, the second protrusions 46 are arranged between the conductive layer 41C and the contact 70C in the Z direction to electrically connect the conductive layer 41C and the contact 70C.

[0109] In the present embodiment, the second protrusion 46 is provided on each conductive layer of the plurality of conductive layers 41C of the third group LG3. Each contact 70C included in the plurality of contacts 70C of the third group CG3 is in contact with the second protrusion 46 provided on the conductive layer 41C corresponding to the contact 70C included in the plurality of conductive layers 41C of the third group LG3. In the present embodiment, the width in the X direction of one end in the -Z direction of the second protrusion 46 is the same as the width in the X direction of one end in the +Z direction of the contact 70C connected to the second protrusion 46.

[0110] The first protrusion 45 and the second protrusion 46 are, for example, regrown portions formed by regrowing a material contained in the conductive layer 41. The first protrusion 45 and the second protrusion 46 are formed in a manner protruding from the surface of the conductive layer 41 by, for example, selectively regrowing a material contained in the conductive layer 41 using CVD (Chemical Vapor Deposition). The material (first material) contained in the conductive layer 41 to be regrown is, for example, tungsten, molybdenum, or silicon doped with impurities, but is not limited thereto. In addition, the first protrusion 45 and the second protrusion 46 may be protrusions formed by regrowing using a method other than CVD, or may be protrusions formed by a method other than regrowing. Hereinafter, the first protrusion 45 and the second protrusion 46 are referred to as "protrusions PT" without distinguishing between them.

[0111] On the other hand, no protrusions corresponding to the protrusions PT are provided in the second region R2 and the fourth region R4 of the laminate 40. Therefore, each contact point 70B included in the plurality of contacts 70B of the second group CG2 is connected to the conductive layer 41B included in the plurality of conductive layers 41B of the second group LG2 that corresponds to the contact point 70B without passing through the protrusions. Furthermore, each contact point 70D included in the plurality of contacts 70D of the fourth group CG4 is connected to the conductive layer 41D included in the plurality of conductive layers 41D of the fourth group LG4 that corresponds to the contact point 70D without passing through the protrusions.

[0112] In other words, the above means that in the laminate 40, areas (e.g., the first area R1 or the third area R3) where a plurality of protrusions PT (e.g., a plurality of first protrusions 45 or a plurality of second protrusions 46) are provided and areas (e.g., the second area R2 and the fourth area R4) where the protrusions PT do not exist are alternately arranged in the X direction.

[0113] Figure 7 1 is a cross-sectional view showing a part of the step region SR in an enlarged manner according to the present embodiment. First, an example of the structure of the conductive layer 41 will be described. The conductive layer 41 includes, for example, a conductive portion 101 , a barrier metal film 102 , and an insulating film 103 .

[0114] The conductive portion 101 is a portion that forms a main portion of the conductive layer 41. The conductive portion 101 extends in a layered manner in the X direction and the Y direction. The conductive portion 101 includes the conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0115] The barrier metal film 102 is a film for suppressing diffusion of the conductive material contained in the conductive portion 101. The barrier metal film 102 is provided along the surface of the conductive portion 101. For example, the barrier metal film 102 is provided along both the +Z direction side surface and the -Z direction side surface of the conductive portion 101. The barrier metal film 102 is formed of, for example, a titanium-containing material, a titanium and nitrogen-containing material, a tantalum-containing material, a tantalum and nitrogen-containing material, or a tungsten and nitrogen-containing material.

[0116] The insulating film 103 is an insulating film disposed on the surface of the conductive layer 41. The insulating film 103 forms a part of the blocking insulating film 61, for example, at the intersection of the storage column MH and the conductive layer 41. The insulating film 103 is located on the side opposite to the conductive portion 101 relative to the barrier metal film 102. The insulating film 103 is disposed along the surface of the barrier metal film 102. For example, the insulating film 103 is disposed along two surfaces, namely, the +Z direction side surface and the -Z direction side surface of the barrier metal film 102. The insulating film 103 is, for example, aluminum oxide, but is not limited thereto. In addition, the insulating film 103 may also be omitted.

[0117] Next, an example of the structure of the contact 70 will be described. The contact includes, for example, a conductive portion 111 and a barrier metal film 112.

[0118] The conductive portion 111 is a portion that forms a main portion of the contact 70. The conductive portion 111 extends in a columnar shape in the Z direction. The conductive portion 111 includes the conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0119] The barrier metal film 112 is a film for suppressing diffusion of the conductive material contained in the conductive portion 111. The barrier metal film 112 is provided along the surface of the conductive portion 111. For example, the barrier metal film 112 has a surface portion 112a extending in the Z direction along the surface of the conductive portion 111, and a bottom portion 112b provided along the bottom surface of the conductive portion 111 on the +Z direction side. The barrier metal film 112 forms, for example, the surface of the contact 70. The barrier metal film 112 is formed of, for example, a titanium-containing material, a titanium and nitrogen-containing material, a tantalum-containing material, a tantalum and nitrogen-containing material, or a tungsten and nitrogen-containing material.

[0120] like Figure 7 As shown in FIG. 1 , the first protrusion 45 is provided between the conductive layer 41A and the contact 70A in the Z direction. Therefore, in the region (first region R1) where the first protrusion 45 is present, the barrier metal film 112 of the contact 70A and the conductive layer 41A (for example, the barrier metal film 102 of the conductive layer 41A) are separated from each other, and a distance L1 exists between the barrier metal film 112 of the contact 70A and the conductive layer 41A. In the present embodiment, a portion of the first protrusion 45 penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41A and is located inside the conductive layer 41A.

[0121] On the other hand, in the region (second region R2) where the first protrusion 45 does not exist, the contact 70B is in contact with the conductive layer 41B. For example, a portion of the contact 70B penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41B and is located inside the conductive layer 41B. In this case, in the region (second region R2) where the first protrusion 45 does not exist, the barrier metal film 112 of the contact 70B and the conductive layer 41B (for example, the barrier metal film 102 of the conductive layer 41B) are in contact with each other.

[0122] Similarly, the second protrusion 46 is provided between the conductive layer 41C and the contact 70C in the Z direction. Therefore, in the region (third region R3) where the second protrusion 46 is present, the barrier metal film 112 of the contact 70C and the conductive layer 41C (for example, the barrier metal film 102 of the conductive layer 41C) are separated from each other, and a distance L2 exists between the barrier metal film 112 of the contact 70C and the conductive layer 41C. In the present embodiment, a portion of the second protrusion 46 penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41C and is located inside the conductive layer 41C.

[0123] On the other hand, in the region (fourth region R4) where the second protrusion 46 does not exist, the contact 70D is in contact with the conductive layer 41D. For example, a portion of the contact 70D passes through the insulating film 103 and the barrier metal film 102 of the conductive layer 41D and is located inside the conductive layer 41D. In this case, in the region (fourth region R4) where the second protrusion 46 does not exist, the barrier metal film 112 of the contact 70D and the conductive layer 41D (for example, the barrier metal film 102 of the conductive layer 41D) are in contact with each other.

[0124] As described above, in this embodiment, in the cross section along the X direction and the Y direction ( Figure 7 ), the shortest distance (e.g., zero distance) between the barrier metal film 112 of the contact 70B and the conductive layer 41B is shorter than the shortest distance L1 between the barrier metal film 112 of the contact 70A and the conductive layer 41A, and is shorter than the shortest distance L2 between the barrier metal film 112 of the contact 70C and the conductive layer 41C. Similarly, in the cross section along the X direction and the Y direction, the shortest distance (e.g., zero distance) between the barrier metal film 112 of the contact 70D and the conductive layer 41D is shorter than the shortest distance L1 between the barrier metal film 112 of the contact 70A and the conductive layer 41A, and is shorter than the shortest distance L2 between the barrier metal film 112 of the contact 70C and the conductive layer 41C. In other words, for example, when there is a distance between the barrier metal film 112 of the contact 70 (eg, the bottom portion 112 b of the barrier metal film 112 ) and the conductive layer 41 , it can be considered that the protrusion PT exists between the contact 70 and the conductive layer 41 .

[0125] In addition, in the present embodiment, an example in which the contact 70 has the barrier metal film 112 is described. However, the contact 70 may not have the barrier metal film 112. In this case, when the morphology of the grains (the size of the grains or the packing density of the grains, etc.) is different between the contact 70 and the protrusion PT, when impurities (oxygen, etc.) are present at the interface between the contact 70 and the protrusion PT, or when the internal impurities are different between the contact 70 and the protrusion PT, etc., it can be considered that the protrusion PT exists between the contact 70 and the conductive layer 41. In addition, based on other viewpoints, when the morphology of the grains (the size of the grains or the packing density of the grains, etc.) is different between the conductive layer 41 and the protrusion PT, when impurities (oxygen, etc.) are present at the interface between the conductive layer 41 and the protrusion PT, or when the internal impurities are different between the conductive layer 41 and the protrusion PT, etc., it can be considered that the protrusion PT exists between the contact 70 and the conductive layer 41.

[0126] <6. Method for manufacturing semiconductor memory device>

[0127] Next, a method for manufacturing semiconductor memory device 1 will be described.

[0128] Fig. 8A and Figure 8B 1 is a diagram for explaining a method for manufacturing the semiconductor memory device 1. In addition, a method for forming the step region SR will be described below. The other parts of the semiconductor memory device 1 can be formed using a known method. Fig. 8A and Figure 8B In the figure, for convenience of explanation, the insulating layer 42 and the insulating portion 43 are shown as a whole.

[0129] First, a laminate 40 including a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating portion 43 is formed (see Fig. 8A (ST1) in the figure). A plurality of conductive layers 41 and a plurality of insulating layers 42 are alternately stacked layer by layer in the Z direction. The conductive layer 41 is an example of the "first layer". The insulating layer 42 is an example of the "second layer". The laminate 40 has first to fourth regions R1, R2, R3, and R4. These regions are arranged in the X direction in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4.

[0130] The formation of the laminated body 40 is performed, for example, in the following manner: after forming an intermediate laminated body in which sacrificial layers and insulating layers 42 are alternately laminated layer by layer in the Z direction, the sacrificial layers are replaced with the conductive layers 41. The sacrificial layers are replaced with the conductive layers 41, for example, by removing the sacrificial layers from the intermediate laminated body by wet etching, and then sequentially supplying materials for forming the insulating film 103, the barrier metal film 102, and the conductive portion 101 to the space after the sacrificial layers are removed, thereby forming the conductive layer 41.

[0131] Next, a mask M is formed so as to cover the laminate 40. Then, in the regions of the mask M corresponding to the third region R3 and the fourth region R4 of the laminate 40, a plurality of openings 121 for hole processing are formed by, for example, photolithography. Then, the third region R3 and the fourth region R4 of the laminate 40 are subjected to hole processing through the plurality of openings 121 of the mask M, thereby forming a plurality of holes 122 (see FIG. 1 ) extending to the middle of the laminate 40 in the Z direction. Fig. 8A (ST2) in the figure).

[0132] Next, a plurality of openings 131 for hole processing are formed in regions corresponding to the first region R1 and the second region R2 of the laminate 40 in the mask M by, for example, photolithography (see ( ST3 ) in A of FIG. 8 ).

[0133] Next, the hole processing is performed on the first region R1 and the second region R2 of the laminate 40 through the multiple openings 131 of the mask M, and the hole processing of the third region R3 and the fourth region R4 of the laminate 40 is started again using the multiple openings 121 of the mask M. Then, the hole processing of the first region R1, the second region R2, the third region R3, and the fourth region R4 of the laminate 40 is stopped in a state where the multiple holes 132 formed in the second region R2 of the laminate 40 and the multiple holes 122 formed in the fourth region R4 do not reach the conductive layer 41 of the multiple conductive layers 41 as their respective connection objects, and the multiple holes 132 formed in the first region R1 of the laminate 40 and the multiple holes 122 formed in the third region R3 reach the conductive layer 41 of the multiple conductive layers 41 as their respective connection objects (refer to Figure 8B (ST4)).

[0134] Next, by using, for example, CVD, a conductive material of the conductive portion 41 is supplied to each of the plurality of holes 131 formed in the first region R1 and the plurality of holes 121 formed in the third region R3 of the laminate 40, thereby forming a protrusion PT as a regrown portion on the surface of the conductive portion 41 (see Figure 8B (ST5) in the figure). The protrusion PT is, for example, a conductive portion that forms the first protrusion 45 or the second protrusion 46.

[0135] Next, the hole processing is performed again in the first region R1, the second region R2, the third region R3, and the fourth region R4 of the laminate 40 through the plurality of openings 121 and 131 of the mask M. At this time, the plurality of first protrusions 45 exist in the first region R1 of the laminate 40, and the plurality of second protrusions 46 exist in the third region R3. Therefore, the plurality of first protrusions 45 and the plurality of second protrusions 46 function as a barrier layer, and prevent the plurality of holes 122 and 132 in the first region R1 and the third region R3 from penetrating the conductive layer 41 as the connection object and being formed deeply.

[0136] Then, when the plurality of holes 132 formed in the second region R2 of the laminate 40 and the plurality of holes 122 formed in the fourth region R4 reach the conductive layer 41 of the plurality of conductive layers 41 as their respective connection objects, the hole processing of the first region R1, the second region R2, the third region R3, and the fourth region R4 is stopped (refer to Figure 8B (ST6) in the process). Thereafter, the materials of the barrier metal film 112 and the conductive portion 111 are sequentially supplied to the interior of the plurality of holes 122 and 132, thereby forming the contact 70. Thus, the formation of the step region SR is completed.

[0137] <7. Advantages>

[0138] As a comparative example, the following configuration is considered: in the hole processing for setting the contact 70, a regrown portion of tungsten or the like is formed inside a plurality of holes corresponding to the conductive layer 41 in the upper half (the portion on the -Z direction side) of the plurality of conductive layers 41, thereby suppressing the hole from penetrating the conductive layer 41 in the upper half of the plurality of conductive layers 41. However, in this case, in the upper half of the plurality of conductive layers 41, the hole processing of the conductive layer 41 in the upper layer portion (the portion on the -Z direction side) is also relatively severe, and hole penetration may occur in the conductive layer 41 in the upper layer portion. Therefore, in the configuration of the comparative example, it is necessary to significantly increase the film thickness of the regrown portion in the upper layer portion, for example, by setting a plurality of regrowing steps. In this case, the manufacturability of the semiconductor memory device is reduced.

[0139] On the other hand, in the present embodiment, the semiconductor memory device 1 includes a laminate 40 and a plurality of contacts 70. The laminate 40 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately laminated layer by layer in the Z direction. The plurality of contacts 70 extend in the Z direction, respectively. The laminate 40 includes a first region R1, a second region R2, and a third region R3. The first region R1, the second region R2, and the third region R3 are arranged in the order of the first region R1, the second region R2, and the third region R3 in the X direction. The plurality of contacts 70 include a first contact 70A arranged in the first region R1, a second contact 70B arranged in the second region R2, and a third contact 70C arranged in the third region R3. The plurality of conductive layers 41 include a first conductive layer 41A, a second conductive layer 41B disposed on the +Z direction side relative to the first conductive layer 41A, and a third conductive layer 41C disposed on the +Z direction side relative to the second conductive layer 41B. The laminate 40 includes a conductive first protrusion 45 protruding from the first conductive layer 41A toward the first contact 70A, and a conductive second protrusion 46 protruding from the third conductive layer 41C toward the third contact 70C. The first contact 70A is in contact with the first protrusion 45. The second contact 70B is in contact with the second conductive layer 41B. The third contact 70C is in contact with the second protrusion 46.

[0140] According to this configuration, the region including the first region R1 and the second region R2 and the region including the third region R3 can be separately processed to form holes for providing the contact 70. Therefore, even when the first protrusion 45 and the second protrusion 46 do not have a large thickness, it is possible to suppress the hole from penetrating the conductive layer 41. Therefore, the first protrusion 45 and the second protrusion 46 can be easily formed, and the manufacturability of the semiconductor memory device 1 can be improved.

[0141] <8. Variations>

[0142] Next, a modification example of the first embodiment will be described.

[0143] Fig. 9 1 is a cross-sectional view of a step region SR of a semiconductor storage device 1A showing a variation of the first embodiment. In this variation, the contact 70A has an end 70e1 connected to the first protrusion 45. The end 70e1 is an example of a "first end". On the other hand, the first protrusion 45 has an end 45e1 connected to the contact 70A. The end 45e1 is an example of a "second end". Here, the hole 132 (refer to Figure 8B ) After the first protrusion 45 is provided, the diameter may be enlarged by wet etching for manufacturing reasons, for example. In this case, the width W1 of the end 70e1 of the contact 70A in the X direction is greater than the width W2 of the end 45e1 of the first protrusion 45 in the X direction.

[0144] Similarly, the contact point 70C has one end 70e1 that contacts the second protrusion 46. On the other hand, the second protrusion 46 has one end 46e1 that contacts the contact point 70C. The hole 122 (see FIG. 122 ) for providing the contact point 70C Figure 8B ) After the second protrusion 46 is provided, the diameter may be enlarged by wet etching for manufacturing reasons, for example. In this case, the width W3 of the one end 70e1 of the contact 70C in the X direction is greater than the width W4 of the one end 46e1 of the second protrusion 46 in the X direction.

[0145] As described above, even if the contact 70 does not have the barrier metal film 112, when the width W1 of the one end 70e1 of the contact 70A in the X direction is larger than the width W2 of the one end 45e1 of the first protrusion 45 in the X direction, it can be considered that the first protrusion 45 exists between the contact 70A and the conductive layer 41A. Similarly, when the width W3 of the one end 70e1 of the contact 70C in the X direction is larger than the width W4 of the one end 46e1 of the second protrusion 46 in the X direction, it can be considered that the second protrusion 46 exists between the contact 70C and the conductive layer 41C.

[0146] (Second embodiment)

[0147] Next, the second embodiment will be described. The second embodiment is different from the first embodiment in that the step region SR has a region divided into six parts in the X direction. In addition, the other configurations except for the configuration described below are the same as those of the first embodiment.

[0148] Fig.10 1 is a cross-sectional view of a semiconductor memory device 1B according to a second embodiment. In this embodiment, the step region SR includes, for example, the first to sixth regions R1, R2, R3, R4, R5, and R6. These regions are arranged in the order of the first region R1, the second region R2, the third region R3, the fourth region R4, the fifth region R5, and the sixth region R6 in the X direction. The first to sixth regions R1, R2, R3, R4, R5, and R6 are, for example, regions obtained by dividing the step region SR into six parts in the X direction. The sizes of the first to sixth regions R1, R2, R3, R4, R5, and R6 may be different from each other.

[0149] (Contacts of Groups 1 to 6)

[0150] The plurality of contacts 70 are separately arranged in the first to sixth regions R1, R2, R3, R4, R5, and R6. The plurality of contacts 70 include a plurality of contacts 70A of the first group CG1, a plurality of contacts 70B of the second group CG2, a plurality of contacts 70C of the third group CG3, a plurality of contacts 70D of the fourth group CG4, a plurality of contacts 70E of the fifth group CG5, and a plurality of contacts 70F of the sixth group CG6.

[0151] The plurality of contacts 70E of the fifth group CG5 are the plurality of contacts 70 arranged in the fifth region R5. Among the plurality of contacts 70E of the fifth group CG5, the closer the contact 70E is to the -X direction side in the fifth region R5, the more it extends in the +Z direction. One contact 70E included in the plurality of contacts 70E of the fifth group CG5 is an example of the "fifth contact".

[0152] The plurality of contacts 70F of the sixth group CG6 are the plurality of contacts 70 arranged in the sixth region R6. Among the plurality of contacts 70F of the sixth group CG6, the closer the contact 70F is to the -X direction side in the sixth region R6, the more it extends in the +Z direction. One contact 70F included in the plurality of contacts 70F of the sixth group CG6 is an example of the "sixth contact".

[0153] (Conductive layers of the 1st to 6th groups)

[0154] The plurality of conductive layers 41 include a plurality of conductive layers 41A of a first group LG1 , a plurality of conductive layers 41B of a second group LG2 , a plurality of conductive layers 41C of a third group LG3 , a plurality of conductive layers 41D of a fourth group LG4 , a plurality of conductive layers 41E of a fifth group LG5 , and a plurality of conductive layers 41F of a sixth group LG6 .

[0155] The multiple conductive layers 41E of the fifth group LG5 are the multiple conductive layers 41 corresponding to the multiple contacts 70E of the fifth group CG5. The multiple conductive layers 41E of the fifth group LG5 are arranged on the +Z direction side relative to the multiple conductive layers 41D of the fourth group LG4. The multiple conductive layers 41E of the fifth group LG5 are arranged between the multiple conductive layers 41D of the fourth group LG4 and the multiple conductive layers 41F of the sixth group LG6 in the Z direction. One conductive layer 41E included in the multiple conductive layers 41E of the fifth group LG5 (the conductive layer 41E corresponding to the fifth contact) is an example of a "fifth gate electrode layer".

[0156] The plurality of conductive layers 41F of the sixth group LG6 are the plurality of conductive layers 41 corresponding to the plurality of contacts 70F of the sixth group CG6. The plurality of conductive layers 41F of the sixth group LG6 are arranged on the +Z direction side relative to the plurality of conductive layers 41E of the fifth group LG5. One conductive layer 41F (the conductive layer 41F corresponding to the sixth contact) included in the plurality of conductive layers 41F of the sixth group LG6 is an example of a "sixth gate electrode layer".

[0157] (Conductive protrusion)

[0158] like Fig.10 As shown, the layered body 40 has a plurality of first protrusions 45 , a plurality of second protrusions 46 , and a plurality of third protrusions 47 .

[0159] A plurality of third protrusions 47 are provided in the fifth region R5. The third protrusions 47 are conductive protrusions provided on the -Z direction side surface of the end of the conductive layer 41E of the fifth group LG5 and protruding from the conductive layer 41E in the -Z direction. The third protrusions 47 protrude from the conductive layer 41E toward the contact 70E of the fifth group CG5 and are in contact with the contact 70E. In other words, the third protrusions 47 are arranged between the conductive layer 41E and the contact 70E in the Z direction to electrically connect the conductive layer 41E and the contact 70E. Similar to the first protrusions 45 and the second protrusions 46, the third protrusions 47 are regrown portions formed by regrowing the material contained in the conductive layer 41.

[0160] In the present embodiment, the third protrusion 47 is provided on each conductive layer of the plurality of conductive layers 41E of the fifth group LG5. Each contact 70E included in the plurality of contacts 70E of the fifth group CG5 is in contact with the third protrusion 47 of the conductive layer 41E corresponding to the contact 70E included in the plurality of conductive layers 41E of the fifth group LG5. Hereinafter, the first protrusion 45, the second protrusion 46, and the third protrusion 47 are referred to as "protrusion PT" without distinguishing between them.

[0161] (Method for manufacturing semiconductor memory device)

[0162] Next, a method for manufacturing semiconductor memory device 1B according to the second embodiment will be described. FIG. 11A to FIG. 11C FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor memory device 1B according to the second embodiment. FIG. 11A to FIG. 11C In the figure, for convenience of explanation, the insulating layer 42 and the insulating portion 43 are shown as a whole.

[0163] First, similarly to the first embodiment, a laminate 40 (see Fig.11A (ST1) in the figure). Next, a mask M is formed in a manner covering the laminate 40. Then, in the regions of the mask M corresponding to the fifth region R5 and the sixth region R6 of the laminate 40, a plurality of openings 141 for hole processing are formed by, for example, photolithography. Then, the fifth region R5 and the sixth region R6 of the laminate 40 are hole processed through the plurality of openings 141 of the mask M, thereby forming a plurality of holes 142 (refer to Fig.11A (ST2) in the figure).

[0164] Next, in the regions of the mask M corresponding to the third region R3 and the fourth region R4 of the laminate 40, a plurality of openings 131 for hole processing are formed by, for example, photolithography (see FIG. 1 ). Fig.11A (ST3) in the figure).

[0165] Next, the third region R3 and the fourth region R4 of the laminate 40 are processed by the plurality of openings 131 of the mask M, and the fifth region R5 and the sixth region R6 of the laminate 40 are processed again by using the plurality of openings 141 of the mask M. Then, the third to sixth regions R3, R4, R5, and R6 of the laminate 40 are processed by the plurality of openings 131 and 141 of the mask M, thereby forming a plurality of holes 132 and 142 (see FIG. 1 ) extending to the middle of the Z direction of the laminate 40. Fig. 11B (ST4) in the figure).

[0166] Next, in the regions of the mask M corresponding to the first region R1 and the second region R2 of the laminate 40, a plurality of openings 121 for hole processing are formed by, for example, photolithography (see FIG. 1 ). Fig. 11B (ST5) in the figure.

[0167] Next, the hole processing is performed on the first region R1 and the second region R2 of the laminate 40 through the multiple openings 121 of the mask M, and the hole processing of the third to sixth regions R3, R4, R5, and R6 of the laminate 40 is started again using the multiple openings 131 and 141 of the mask M. Then, the hole processing of the first to sixth regions R1, R2, R3, R4, R5, and R6 is stopped in a state where the multiple holes 122 formed in the second region R2 of the laminate 40, the multiple holes 132 formed in the fourth region R4, and the multiple holes 142 formed in the sixth region R6 do not reach the conductive layer 41 of the multiple conductive layers 41 as their respective connection objects, and the multiple holes 122 formed in the first region R1 of the laminate 40, the multiple holes 132 formed in the third region R3, and the multiple holes 142 formed in the fifth region R5 reach the conductive layer 41 of the multiple conductive layers 41 as their respective connection objects (refer to Fig. 11B (ST6) in the figure).

[0168] Next, by using, for example, CVD, the conductive material of the conductive portion 41 is supplied to each of the plurality of holes 122 formed in the first region R1, the plurality of holes 132 formed in the third region R3, and the plurality of holes 142 formed in the fifth region R5 of the laminate 40, thereby forming a protrusion PT as a regrown portion on the surface of the conductive portion 41 (see Fig. 11B(ST7) in the figure). The protrusion PT is, for example, a conductive portion that forms the first protrusion 45, the second protrusion 46, or the third protrusion 47.

[0169] Next, the hole processing of the first to sixth regions R1, R2, R3, R4, R5, and R6 of the laminate 40 is started again through the plurality of openings 121, 131, and 141 of the mask M. At this time, there are a plurality of first protrusions 45 in the first region R1 of the laminate 40, a plurality of second protrusions 46 in the third region R3, and a plurality of third protrusions 47 in the fifth region R5. Therefore, the plurality of first protrusions 45, the plurality of second protrusions 46, and the plurality of third protrusions 47 function as a barrier layer, and prevent the plurality of holes 122, 132, and 142 in the first region R1, the third region R3, and the fifth region R5 from penetrating the conductive layer 41 to be connected and being formed deeply.

[0170] Then, when the plurality of holes 122 formed in the second region R2, the plurality of holes 132 formed in the fourth region R4, and the plurality of holes 142 formed in the sixth region R6 of the laminate 40 reach the conductive layer 41 as their respective connection objects among the plurality of conductive layers 41, the hole processing of the first to sixth regions R1, R2, R3, R4, R5, and R6 is stopped (refer to Fig. 11C (ST8) in the process). Thereafter, the materials of the barrier metal film 112 and the conductive portion 111 are sequentially supplied to the interiors of the plurality of holes 122, 132, and 142, thereby forming the contact 70. Thus, the formation of the step region SR is completed.

[0171] According to this configuration, the reliability of the semiconductor storage device 1B is improved as in the first embodiment. In addition, according to the present embodiment, the number of divisions is larger than in the first embodiment, so even if the first protrusion 45, the second protrusion 46, and the third protrusion 47 are thin, it is possible to suppress the hole from penetrating the conductive layer 41. Therefore, the protrusions 45, 46, and 47 are easily formed, and the manufacturability of the semiconductor storage device 1B can be improved.

[0172] (Third embodiment)

[0173] Next, the third embodiment will be described. The third embodiment is different from the first embodiment in that the configuration of the first embodiment is applied to a multi-row step region SR. In addition, the configuration other than the configuration described below is the same as that of the first embodiment.

[0174] Fig.12 1 is a perspective cross-sectional view showing a stepped region SR of a semiconductor storage device 1C according to the third embodiment. In this embodiment, the plurality of conductive layers 41 have a plurality of stepped regions SR in a stepped manner. For example, Fig.12A two-row step region SR is shown as an example of a multi-row step region. Fig.12 In FIG. 1 , in each of the regions R1 , R2 , R3 , and R4 , the conductive layers 41 are schematically shown as four layers each.

[0175] In the third embodiment, the odd-numbered conductive layers 41 in the Z direction (hereinafter referred to as "conductive layers 41S" for convenience of explanation) have a first portion 151 and a second portion 152. In each conductive layer 41S, the first portion 151 and the second portion 152 are arranged in the Y direction. The length of the second portion 152 in the -X direction is shorter than the length of the first portion 151 in the -X direction.

[0176] On the other hand, the conductive layer 41 adjacent to the conductive layer 41S in the +Z direction (hereinafter referred to as "conductive layer 41T" for convenience of explanation) has a third portion 153 and a fourth portion 154. In each conductive layer 41T, the third portion 153 and the fourth portion 154 are arranged in the Y direction. The third portion 153 is located on the +Z direction side of the first portion 151 of the conductive layer 41S. The fourth portion 154 is located on the +Z direction side of the second portion 152 of the conductive layer 41S. The length of each of the third portion 153 and the fourth portion 154 in the -X direction is the same as the length of the first portion 151 of the conductive layer 41S in the -X direction. As a result, the third portion 153 of the conductive layer 41T is covered by the first portion 151 of the conductive layer 41S. On the other hand, the fourth portion 154 of the conductive layer 41T is exposed in the -Z direction and is not covered by the second portion 152 of the conductive layer 41S.

[0177] In this embodiment, the plurality of contacts 70 include a contact 70S electrically connected to the first portion 151 of the conductive layer 41S and a contact 70T electrically connected to the fourth portion 154 of the conductive layer 41T. The contact 70S and the contact 70T are arranged in the Y direction. With this configuration, the length of the step region SR in the -X direction can be shortened.

[0178] Furthermore, in the present embodiment, the first protrusion 45 is provided between each contact 70S arranged in the first region R1 of the laminate 40 and the first portion 151 of the conductive layer 41S corresponding to the contact 70S. Furthermore, the first protrusion 45 is provided between each contact 70T arranged in the first region R1 of the laminate 40 and the fourth portion 154 of the conductive layer 41T corresponding to the contact 70T.

[0179] Similarly, a second protrusion 46 is provided between each contact 70S arranged in the third region R3 of the laminate 40 and the first portion 151 of the conductive layer 41S corresponding to the contact 70S. In addition, a second protrusion 46 is provided between each contact 70T arranged in the third region R3 of the laminate 40 and the fourth portion 154 of the conductive layer 41T corresponding to the contact 70T.

[0180] On the other hand, in the second region R2 and the fourth region R4 of the laminate 40, there is no protrusion PT between each contact 70S and the first portion 151 of the conductive layer 41S corresponding to the contact 70S, and each contact 70S is in contact with the first portion 151 of the conductive layer 41S. Similarly, in the second region R2 and the fourth region R4 of the laminate 40, there is no protrusion PT between each contact 70T and the fourth portion 154 of the conductive layer 41T corresponding to the contact 70T, and each contact 70T is in contact with the fourth portion 154 of the conductive layer 41T.

[0181] According to this configuration, similar to the first embodiment, the manufacturability of the semiconductor storage device 1C can be improved. In addition, in this embodiment, a two-column step region SR is described. However, the embodiment is not limited to the example. For example, the semiconductor storage device 1C may also have a plurality of step regions SR with three or more columns.

[0182] (Variation Example)

[0183] Next, modified examples of the first to third embodiments will be described.

[0184] Fig.13 FIG. 1 is a cross-sectional view showing a step region SR of a semiconductor memory device 1D according to a modification of the embodiment. Fig.13 For example, this is a modification example corresponding to the configuration of the semiconductor memory device 1 of the first embodiment. In this modification example, the closer the protrusion PT is to the +Z direction side, the greater the thickness of the protrusion PT in the Z direction.

[0185] For example, the plurality of protrusions 45 provided in the first region R1 include a protrusion 45 - 1 , a protrusion 45 - 2 , and a protrusion 45 - 3 .

[0186] The protrusion 45-2 is disposed on the +Z direction side compared to the protrusion 45-1. In other words, the conductive layer 41A provided with the protrusion 45-2 is disposed on the +Z direction side compared to the conductive layer 41A provided with the protrusion 45-1. In this variation, the Z direction thickness T2 of the protrusion 45-2 is greater than the Z direction thickness T1 of the protrusion 45-1.

[0187] The protrusion 45-3 is disposed on the +Z direction side compared to the protrusion 45-2. In other words, the conductive layer 41A provided with the protrusion 45-3 is disposed on the +Z direction side compared to the conductive layer 41A provided with the protrusion 45-2. In this variation, the Z direction thickness T3 of the protrusion 45-3 is greater than the Z direction thickness T2 of the protrusion 45-2.

[0188] Similarly, the plurality of protrusions 46 provided in the third region R3 include a protrusion 46 - 1 , a protrusion 46 - 2 , and a protrusion 46 - 3 .

[0189] The protrusion 46-1 is disposed on the +Z direction side compared to the protrusion 45-3 disposed in the first region R1. In other words, the conductive layer 41C provided with the protrusion 46-1 is disposed on the +Z direction side compared to the conductive layer 41A provided with the protrusion 45-3. In this variation, the Z direction thickness T4 of the protrusion 46-1 is greater than the Z direction thickness T3 of the protrusion 45-3.

[0190] The protrusion 46-2 is disposed on the +Z direction side compared to the protrusion 46-1. In other words, the conductive layer 41C provided with the protrusion 46-2 is disposed on the +Z direction side compared to the conductive layer 41C provided with the protrusion 46-1. In this variation, the Z direction thickness T5 of the protrusion 46-2 is greater than the Z direction thickness T4 of the protrusion 46-1.

[0191] The protrusion 46-3 is disposed on the +Z direction side compared to the protrusion 46-2. In other words, the conductive layer 41C provided with the protrusion 46-3 is disposed on the +Z direction side compared to the conductive layer 41C provided with the protrusion 46-2. In this variation, the Z direction thickness T6 of the protrusion 46-3 is greater than the Z direction thickness T5 of the protrusion 46-2.

[0192] This configuration is achieved, for example, by the protrusion PT being cut more as it is located on the -Z direction side due to etching when processing the hole 122 or the hole 132. However, this configuration may be achieved by a factor other than the etching.

[0193] The configuration of this variation can also be applied to the configuration of the second embodiment. In this case, the closer the protrusion PT is to the +Z direction side, the greater the Z direction thickness of the protrusion PT is.

[0194] Several embodiments and variations have been described above. However, the embodiments and variations are not limited to the examples described above. For example, the protrusion PT may not exist in some of the conductive layers 41 located on the -Z direction side among the plurality of conductive layers 41 (for example, some of the conductive layers 41 located on the -Z direction side among the plurality of conductive layers 41 electrically connected to the contact 70A in the first region R1). For example, the protrusion PT may disappear because the conductive layers 41 located on the -Z direction side among the plurality of conductive layers 41 (for example, some of the conductive layers 41 located on the -Z direction side among the plurality of conductive layers 41 electrically connected to the contact 70A in the first region R1) are cut by etching during processing of the hole 122 or the hole 132. In addition, several conductive layers 41 located on the -Z direction side among the multiple conductive layers 41 (for example, several conductive layers 41 located on the -Z direction side among the multiple conductive layers 41 electrically connected to the contact 70A in the first region R1) may also be over-etched to an extent that does not penetrate when processing the hole 122 or the hole 132, etc., so that the end of the contact 70 on the +Z direction side enters the interior of the conductive layer 41.

[0195] According to at least one embodiment described above, a semiconductor memory device includes a laminated body and a plurality of contacts. The plurality of laminated bodies include a plurality of gate electrode layers and a plurality of insulating layers. The plurality of contacts include a first contact, a second contact, and a third contact. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer arranged on a first side relative to the first gate electrode layer, and a third gate electrode layer arranged on a first side relative to the second gate electrode layer. The laminated body includes a conductive first protrusion protruding from the first gate electrode layer toward the first contact, and a conductive second protrusion protruding from the third gate electrode layer toward the third contact. The first contact is in contact with the first protrusion. The second contact is in contact with the second gate electrode layer. The third contact is in contact with the second protrusion. According to this configuration, the manufacturability of the semiconductor device can be improved.

[0196] Several embodiments have been described above. However, the embodiments are not limited to the above examples. For example, the step region SR may be divided into eight or more parts instead of four or six parts.

[0197] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0198] [Explanation of Symbols]

[0199] 1,1A,1B,1C:Semiconductor storage device

[0200] 40:Laminated body

[0201] 41: Conductor layer (gate electrode layer)

[0202] 41A: conductive layer of group 1

[0203] 41B: Conductive layer of the second group

[0204] 41C: Conductive layer of group 3

[0205] 41D: Conductive layer of group 4

[0206] 41E: Conductive layer of group 5

[0207] 41F: Conductive layer of group 6

[0208] 42: Insulation layer

[0209] 45: 1st protrusion

[0210] 46: Second protrusion

[0211] 47: The third salient

[0212] 70:Contact

[0213] 70A: Contact of Group 1

[0214] 70B: Contact of the second group

[0215] 70C: Contact of the third group

[0216] 70D: Contact of the 4th group

[0217] 70E: Contact point of group 5

[0218] 70F: Contact of Group 6

[0219] 122: Barrier metal layer of contact

[0220] R1: Area 1

[0221] R2: Area 2

[0222] R3: Area 3

[0223] R4: Region 4

[0224] R5: Area 5

[0225] R6: Region 6.

Claims

1. A semiconductor memory device, have: A laminated body comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately laminated layer by layer in a first direction; and A plurality of contacts extending in the first direction respectively; The laminate includes a first region, a second region, and a third region, wherein the first region, the second region, and the third region are arranged in the order of the first region, the second region, and the third region in a second direction different from the first direction. The plurality of contacts include a first contact disposed in the first region, a second contact disposed in the second region, and a third contact disposed in the third region. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer arranged on a first side in the first direction relative to the first gate electrode layer, and a third gate electrode layer arranged on the first side relative to the second gate electrode layer. The laminate includes a conductive first protrusion protruding from the first gate electrode layer toward the first contact, and a conductive second protrusion protruding from the third gate electrode layer toward the third contact. The first contact point is in contact with the first protrusion, The second contact is in contact with the second gate electrode layer, and The third contact point is in contact with the second protrusion.

2. The semiconductor memory device according to claim 1, wherein When the side opposite to the first side in the first direction is defined as the second side, The plurality of contacts include a first group of contacts, the first group of contacts are arranged in the first region and include the first contact, The plurality of gate electrode layers include a first group of plurality of gate electrode layers, the first group of plurality of gate electrode layers being arranged on the second side relative to the second gate electrode layer and including the first gate electrode layer, The first protrusion is provided on each gate electrode layer of the first group of multiple gate electrode layers, and each contact included in the first group of multiple contacts is in contact with the first protrusion provided on the gate electrode layer corresponding to the contact included in the first group of multiple gate electrode layers.

3. The semiconductor memory device according to claim 2, wherein The plurality of contacts include a second group of contacts, the second group of contacts are arranged in the second region and include the second contact, The plurality of gate electrode layers include a second group of gate electrode layers, the second group of gate electrode layers are arranged between the first group of gate electrode layers and the third gate electrode layer, and include the second gate electrode layer, and Each contact included in the second group of multiple contacts is in contact with a gate electrode layer corresponding to the contact included in the second group of multiple gate electrode layers.

4. The semiconductor memory device according to claim 3, wherein The plurality of contacts include a third group of contacts, the third group of contacts are arranged in the third region and include the third contact, The plurality of gate electrode layers include a third group of gate electrode layers, the third group of gate electrode layers are arranged on the first side relative to the second group of gate electrode layers and include the third gate electrode layer, The second protrusion is provided on each gate electrode layer of the third group of multiple gate electrode layers, and each contact included in the third group of multiple contacts is connected to the second protrusion of the gate electrode layer corresponding to the contact provided on the third group of multiple gate electrode layers.

5. The semiconductor memory device according to claim 1 or 2, wherein In a connection region where the plurality of contacts are connected to the plurality of gate electrode layers, the length of the second gate electrode layer in the second direction is longer than that of the first gate electrode layer, and In the connection region, the third gate electrode layer has a length in the second direction longer than that of the second gate electrode layer.

6. The semiconductor memory device according to claim 1 or 2, wherein The first contact, the second contact, and the third contact respectively include a barrier metal film, and in a cross section along the first direction and the second direction, the shortest distance between the barrier metal film of the second contact and the second gate electrode layer is shorter than the shortest distance between the barrier metal film of the first contact and the first gate electrode layer, and shorter than the shortest distance between the barrier metal film of the third contact and the third gate electrode layer.

7. The semiconductor memory device according to claim 1 or 2, wherein The first contact point has a first end connected to the first protrusion, The first protrusion has a second end connected to the first end of the first contact point, and The width of the first end in the second direction is greater than the width of the second end in the second direction.

8. The semiconductor memory device according to claim 1 or 2, wherein The first gate electrode layer, the second gate electrode layer, and the third gate electrode layer each include a first material, namely, tungsten, molybdenum, or silicon, and Each of the first protrusion and the second protrusion is a regrown portion of the first material.

9. The semiconductor memory device according to claim 1 or 2, wherein The laminate includes a fourth region and a fifth region, and the first region, the second region, the third region, the fourth region, and the fifth region are arranged in the order of the first region, the second region, the third region, the fourth region, and the fifth region in the second direction. The plurality of contacts include a fourth contact disposed in the fourth region and a fifth contact disposed in the fifth region. The plurality of gate electrode layers include a fourth gate electrode layer arranged on the first side relative to the third gate electrode layer, and a fifth gate electrode layer arranged on the first side relative to the fourth gate electrode layer. The laminate includes a conductive third protrusion protruding from the fifth gate electrode layer toward the fifth contact. The fourth contact is connected to the fourth gate electrode layer, and The fifth contact point is in contact with the third protrusion.

10. A method for manufacturing a semiconductor storage device, comprising: forming a laminated body including a plurality of first layers and a plurality of second layers, wherein the plurality of first layers and the plurality of second layers are alternately laminated layer by layer in a first direction, wherein the laminated body includes a first region, a second region, and a third region, wherein the first region, the second region, and the third region are arranged in the order of the first region, the second region, and the third region in a second direction different from the first direction, and the plurality of first layers include a first material; By performing hole processing on the third region, a plurality of holes each extending to a midway position of the laminate in the first direction are formed; The hole processing of the first region and the second region is performed, and the hole processing of the third region is restarted, and the hole processing of the first region, the second region, and the third region is stopped in a state in which the plurality of holes formed in the second region do not reach the layers of the plurality of first layers as the respective connection targets, and the plurality of holes formed in the first region and the plurality of holes formed in the third region reach the layers of the plurality of first layers as the respective connection targets; forming a regrown portion of the first material inside the plurality of holes formed in the first region and the plurality of holes formed in the third region; and The hole machining of the first region, the second region, and the third region is restarted.

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