Novel memory with 3D structure and preparation method thereof

Abstract

The invention provides a novel memory with a 3D structure and a preparation method thereof. According to the invention, after the process of forming the gate structure, the storage unit is directly formed on the active region, so that the influence of the thermal budget of the related process of the storage unit on the device in the previous process is reduced, and the influence of the front layer on the outline of the storage unit is reduced; the lower electrode of the storage unit is directly connected with the active region, and the upper electrode of the storage unit is led out through a lead-out structure with a larger size, so that the connection reliability of the upper / lower electrode of the storage unit and a corresponding component is improved; the leading-out structure and the active region / gate structure without the storage unit are led out through the corresponding contact structure / connection structure, so that a dielectric layer and a photomask process are reduced; the storage units of the 3D structure are continuously distributed on the inner wall of the groove, and the phase change effective area is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a novel memory with a 3D structure and a preparation method thereof. Background Art

[0002] New memory devices such as phase change memory (PRAM) or ferroelectric memory (FeRAM) are devices that integrate memory cells in the back-end of the line (BEOL). Memory cells are inserted between metal layers, and their storage performance is proportional to the effective area of ​​the storage layer and the electrode layer. The use of a three-dimensional (3D) structure in memory cells can effectively increase storage density or achieve better cell performance / reliability at the same cell area.

[0003] After the traditional 3D structure process is integrated into the devices and contact structures of the front-end-of-line (FEOL) process, the thermal budget of the 3D structure process (the heat energy required for silicon exposure in the process) may affect the front-end process devices. At the same time, the profile of the 3D structure storage unit is greatly affected by the previous layer. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a new type of memory with a 3D structure and a preparation method thereof, which can reduce the impact of the thermal budget of the memory cell-related process on the front-end process devices while ensuring the connection performance of the contact structure remains unchanged, reduce the impact of the front layer on the memory cell profile, increase the effective area of ​​the phase change, improve the storage performance, save the mask process, and reduce the production cost.

[0005] In order to solve the above problems, the present invention provides a method for preparing a novel memory with a 3D structure, the method comprising the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, an active area defined in the substrate; forming a first dielectric layer, the first dielectric layer covering the surface of the substrate, a groove penetrating the first dielectric layer in a direction perpendicular to the surface of the substrate and exposing a portion of the active area; forming a storage unit and a lead-out structure of a 3D structure, the storage unit being continuously distributed on the inner wall of the groove, the storage unit comprising a first electrode layer, a storage layer and a second electrode layer stacked in sequence; A layer is formed, at the bottom of the groove, the first electrode layer is in contact with the active area, the lead-out structure covers the second electrode layer and fills the groove; a second dielectric layer is formed, the second dielectric layer covers the first dielectric layer, all the storage units and all the lead-out structures, a contact hole is formed in the second dielectric layer along a direction perpendicular to the substrate surface and penetrates the second dielectric layer and exposes part of the lead-out structure; and a contact structure and a metal structure are formed, the contact structure fills the contact hole and contacts the lead-out structure, and the metal structure is located on the surface of the second dielectric layer and contacts the contact structure.

[0006] In order to solve the above problems, the present invention also provides a new type of memory with a 3D structure, comprising: a substrate, an active area is defined in the substrate; a first dielectric layer, covering the surface of the substrate, a groove is formed in the first dielectric layer, which penetrates the first dielectric layer in a direction perpendicular to the substrate surface and exposes part of the active area; a storage unit is continuously distributed on the inner wall of the groove, the storage unit comprises a first electrode layer, a storage layer and a second electrode layer which are stacked in sequence, and at the bottom of the groove, the first electrode layer is in contact with the active area; a lead-out structure, covering the second electrode layer and filling the groove; a second dielectric layer, covering the first dielectric layer, all the storage units and all the lead-out structures, a contact hole is formed in the second dielectric layer, which penetrates the second dielectric layer in a direction perpendicular to the substrate surface and exposes part of the lead-out structure; a contact structure, which fills the contact hole and contacts the lead-out structure; and a metal structure, located on the surface of the second dielectric layer and contacts the contact structure.

[0007] The above technical solution, by directly forming a memory cell on the active area after forming the gate structure process, reduces the impact of the thermal budget of the memory cell related process on the front-end process device, and reduces the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell is led out through a lead-out structure with a larger size, which improves the connection reliability between the upper / lower electrode of the memory cell and the corresponding component; the lead-out structure and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, reducing the dielectric layer and mask process; the memory cell of the 3D structure continuously distributed on the inner wall of the groove increases the phase change effective area. The present invention can reduce the impact of the thermal budget of the memory cell related process on the front-end process device, reduce the impact of the front layer on the memory cell profile, reduce the dielectric layer and mask process, and improve the storage performance, optimize and improve the device operation efficiency and reliability, and reduce the production cost on the basis of increasing the phase change effective area of ​​the memory cell and keeping the connection performance of the contact structure unchanged.

[0008] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 A schematic diagram of a device structure of a 3D structure memory in the prior art;

[0011] Figure 2 A schematic diagram of a contour defect of a memory with a 3D structure in the prior art;

[0012] Figure 3 A schematic diagram of the steps of a method for preparing a novel memory with a 3D structure according to an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;

[0014] Figure 5A to Figure 5B A schematic diagram of a device structure for forming a first dielectric layer according to an embodiment of the present invention;

[0015] Figure 6A to Figure 6C A schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention;

[0016] Figure 7A to Figure 7B A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention;

[0017] Figure 8 A schematic diagram of a device structure for forming a contact structure and a metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] See also Figure 1 , which is a schematic diagram of the device structure of a 3D structure memory in the prior art. Figure 1 As shown, the existing 3D structure memory includes: a substrate 10, a first dielectric layer 111 formed on the substrate 10, a first connection structure 121 formed in the first dielectric layer 111, a second dielectric layer 112 formed on the first dielectric layer 111, a storage unit 14 formed in the second dielectric layer 112 and in contact with the first connection structure 121, and a second connection structure 122 in contact with the storage unit 14, a third dielectric layer 113 covering the second dielectric layer 112 and covering the storage unit 14 and the second connection structure 122, a third connection structure 123 formed in the third dielectric layer 113 and in contact with the storage unit 14, and a metal structure 13 formed on the surface of the third dielectric layer 113 and in contact with the third connection structure 123. The storage unit 14 is composed of a lower electrode layer 141, a middle storage layer 142, and an upper electrode layer 143. A first blocking layer 191 is formed between the first dielectric layer 111 and the second dielectric layer 112 , and a second blocking layer 192 is formed between the second dielectric layer 112 and the third dielectric layer 113 .

[0020] The memory cell 14 uses a three-dimensional (3D) structure to effectively improve storage density, or achieve better unit performance / reliability under the same unit area. However, after the memory cell manufacturing process is integrated into the device and contact structure of the front-end process (FEOL), the thermal budget of the process will affect the front-end process device. The profile of the memory cell is greatly affected by the previous layer, such as Figure 2 As shown in the dotted box. Figure 2In the figure, a single-layer color block is used to indicate a storage unit, and the outline of the storage unit in the dotted frame is affected by the protruding contact structure and deformed. At the same time, when preparing the memory, multiple dielectric layers need to be deposited, and the preparation of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three mask processes, resulting in increased production costs.

[0021] In order to solve the problem in the prior art that the thermal budget of the storage unit preparation process affects the front-end process devices, the profile of the storage unit is greatly affected by the front layer, and multiple dielectric layer deposition and multiple mask processes are required, resulting in increased production costs, the present invention provides a new type of memory with a 3D structure and a preparation method thereof, which can reduce the impact of the thermal budget of the storage unit-related processes on the front-end process devices, reduce the impact of the front layer on the profile of the storage unit, reduce the dielectric layer and mask processes, thereby improving storage performance, optimizing and improving device operation efficiency and reliability, and reducing production costs.

[0022] An embodiment of the present invention provides a method for preparing a novel memory with a 3D structure.

[0023] Please also read Figure 3 to Figure 8 ,in, Figure 3 A schematic diagram of the steps of a method for preparing a novel memory with a 3D structure according to an embodiment of the present invention; Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention; Figure 5A to Figure 5B A schematic diagram of a device structure for forming a first dielectric layer according to an embodiment of the present invention; Figure 6A to Figure 6C A schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention;

[0024] Figure 7A to Figure 7B A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention; Figure 8 A schematic diagram of a device structure for forming a contact structure and a metal structure according to an embodiment of the present invention.

[0025] like Figure 3As shown, the preparation method of the novel memory of the 3D structure described in this embodiment includes the following steps: S1, forming a semiconductor substrate, the semiconductor substrate includes a substrate, and an active area is defined in the substrate; S2, forming a first dielectric layer, the first dielectric layer covers the surface of the substrate, and a groove is formed in the first dielectric layer along a direction perpendicular to the surface of the substrate and penetrates the first dielectric layer and exposes part of the active area; S3, forming a storage unit and a lead-out structure of the 3D structure, the storage unit is continuously distributed on the inner wall of the groove, the storage unit includes a first electrode layer, a storage layer and a second electrode layer which are sequentially stacked and arranged, and in the The bottom of the groove, the first electrode layer is in contact with the active area, the lead-out structure covers the second electrode layer and fills the groove; S4, forming a second dielectric layer, the second dielectric layer covers the first dielectric layer, all the storage units and all the lead-out structures, and a contact hole is formed in the second dielectric layer along a direction perpendicular to the substrate surface and penetrates the second dielectric layer and exposes part of the lead-out structure; and S5, forming a contact structure and a metal structure, the contact structure fills the contact hole and contacts the lead-out structure, and the metal structure is located on the surface of the second dielectric layer and contacts the contact structure.

[0026] Please refer to step S1 and Figure 4 , forming a semiconductor substrate, the semiconductor substrate includes a substrate 40, and an active area 401 is defined in the substrate 40.

[0027] The substrate 40 is used to support the device structure above it, and the device structure may also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0028] In this embodiment, a gate structure 49 is further formed on the surface of the substrate 40, and an active region 401 is defined in the substrate 40 between two adjacent gate structures 49. Before the step (S2) of forming the first dielectric layer, the step further includes: forming a contact layer 41, the contact layer 41 covers the surface of the substrate 40 and exposes the gate structure 49, such as Figure 4As shown. The source / drain on both sides of the gate structure 49 can be led out through the contact layer 41. Specifically, the material of the contact layer 41 is metal silicide. The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491.

[0029] Please refer to step S2 and Figure 5B , forming a first dielectric layer 51, the first dielectric layer 51 covers the surface of the substrate 40, and a groove 510 is formed in the first dielectric layer 51 along a direction perpendicular to the surface of the substrate 40 and penetrating the first dielectric layer 51 and exposing a portion of the active area 401.

[0030] In this embodiment, the step of forming the first dielectric layer 51 specifically includes: (1) forming a first etch stop layer 58 covering the surface of the substrate 40, forming the first dielectric layer 51 covering the first etch stop layer 58, and forming a first protective layer 59 covering the first dielectric layer 51, such as Figure 5A (2) Using the first etching barrier layer 58 as an etching stop layer, the first protective layer 59 and the first dielectric layer 51 are etched to form the groove 510, as shown in FIG. Figure 5B As shown. The material of the first dielectric layer 51 may be an oxide (OX) material, such as silicon oxide (SiO). The material of the first etch stop layer 58 may be silicon nitride (SiN). The material of the first protective layer 59 may be silicon oxynitride (SiON). The first etch stop layer 58 serves as an etch stop layer for etching the groove 510, and the first protective layer 59 is used to protect the first dielectric layer 51 when etching the groove.

[0031] When a gate structure 49 and a contact layer 41 are further formed on the surface of the substrate 40 , the first etch stop layer 58 covers the gate structure 49 and the contact layer 41 , and the first dielectric layer 51 fills the area between two adjacent gate structures 49 .

[0032] Please refer to step S3 and Figure 6C , forming a 3D structure storage unit 60 and a lead-out structure 64, the storage unit 60 is continuously distributed on the inner wall of the groove 510, the storage unit 60 includes a first electrode layer 61, a storage layer 62 and a second electrode layer 63 which are stacked in sequence, at the bottom of the groove 510, the first electrode layer 61 is in contact with the active area 401, and the lead-out structure 64 covers the second electrode layer 63 and fills the groove 510.

[0033] Specifically, when the surface of the substrate 40 is covered with a contact layer 41 , the first electrode layer 61 is in contact with the active region 401 through the contact layer 41 .

[0034] In this embodiment, the 3D structured storage unit 60 and the lead-out structure 64 further include: (1) depositing a first electrode material layer 610, a storage material layer 620 and a second electrode material layer 630 on the inner wall of the groove 510 and the surface of the first dielectric layer 51 in sequence, such as Fig. 6A (2) Depositing to form a lead-out material layer 640 covering the second electrode material layer 630 and filling the groove 510, as shown in FIG. Figure 6B (3) Patterning the first electrode material layer 610, the storage material layer 620, the second electrode material layer 630 and the lead-out material layer 640 to form the first electrode layer 61, the storage layer 62, the second electrode layer 63 which are continuously distributed on the inner wall of the groove 510 and are stacked in sequence, and forming the lead-out structure 64 which covers the second electrode layer 63 and fills the groove 510, as shown in FIG. Figure 6C shown.

[0035] In some embodiments, the first electrode material layer 610, the storage material layer 620, and the second electrode material layer 630 may be deposited and grown by maskless atomic layer deposition (ALD). The extraction material layer 640 may also be deposited and grown by maskless atomic layer deposition (ALD). The patterning may be achieved by etching the first electrode material layer 610, the storage material layer 620, the second electrode material layer 630, and the extraction material layer 640 using a predetermined mask.

[0036] In some embodiments, the materials of the first electrode layer 61 and the second electrode layer 63 are both titanium nitride, the material of the storage layer 62 is a ferroelectric material or a phase change material, and the material of the lead-out structure 64 can be metal tungsten.

[0037] In this embodiment, the memory cell 60 is a 3D structure. Specifically, the first electrode layer 61, the memory layer 62 and the second electrode layer 63 are of the same shape.

[0038] In this embodiment, the storage units 60 are continuously distributed on the inner wall of the groove 510 and a portion of the surface of the first dielectric layer 51 adjacent to the groove 510. Figure 6C shown.

[0039] In this embodiment, a second protective layer 69 is also formed on the surface of the lead-out structure 64. The material of the second protective layer 69 may be silicon oxynitride (SiON). The second protective layer 69 may be formed before the above-mentioned patterning process to protect the lead-out material layer 640 during the patterning process, and remain on the surface of the lead-out structure 64 after the patterning process is completed.

[0040] This embodiment directly forms a memory cell after forming a gate structure (further forming a contact layer) process, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the subsequent upper electrode (second electrode layer) of the memory cell is led out through a lead-out structure with a larger size, thereby improving the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components and reducing the dielectric layer and mask process; and the 3D structure of the memory cell 60 continuously distributed on the inner wall of the groove 510 increases the effective area of ​​the phase change.

[0041] Please refer to step S4 and Figure 7B , forming a second dielectric layer 71, the second dielectric layer 71 covers the first dielectric layer 51, all the storage units 60 and all the lead-out structures 64, and a contact hole 701 is formed in the second dielectric layer 71 along a direction perpendicular to the surface of the substrate 40 and penetrating the second dielectric layer 71 and exposing a portion of the lead-out structure 64.

[0042] In this embodiment, the step of forming the second dielectric layer 71 specifically includes: (1) forming a second etch stop layer 78 covering the first dielectric layer 51, all the storage units 60 and all the lead-out structures 64, forming the second dielectric layer 71 covering the second etch stop layer 78, and forming an etch protection layer 79 covering the second dielectric layer 71, such as Fig. 7A (2) Using the second etching barrier layer 78 as an etching stop layer, etching the etching protection layer 79 and the second dielectric layer 71 to form the contact hole 701, as shown in FIG. Figure 7B As shown. The material of the second dielectric layer 71 may be an oxide (OX) material, such as silicon oxide (SiO). The material of the second etch stop layer 78 may be silicon nitride (SiN). The material of the etch protection layer 79 may be silicon oxynitride (SiON). The second etch stop layer 78 serves as an etch stop layer for etching to form the contact hole 701, and the etch protection layer 79 is used to protect the second dielectric layer 71 when etching the contact hole.

[0043] In this embodiment, a connection hole 702 is formed at the same time as the contact hole 701. The connection hole 702 penetrates the second dielectric layer 71 and the first dielectric layer 51 in a direction perpendicular to the surface of the substrate 40 and is spaced apart from the contact hole 701. Specifically, after the contact hole 701 is formed by etching with the second etch barrier layer 78 as an etch stop layer, the first protective layer 59 and the first dielectric layer 51 are etched with the first etch barrier layer 58 as an etch stop layer to form the connection hole 702. Specifically, part of the connection hole 702 exposes the substrate 40 (specifically, the contact layer 41 above another active region 401 without a memory cell in the substrate 40), and part of the connection hole 702 exposes the top of the gate structure 49 (not shown).

[0044] Please refer to step S5 and Figure 8 , forming a contact structure 81 and a metal structure 89 , wherein the contact structure 81 fills the contact hole 701 and contacts the lead-out structure 64 , and the metal structure 89 is located on the surface of the second dielectric layer 71 and contacts the contact structure 81 .

[0045] In some embodiments, the steps of forming the contact structure 81 and the metal structure 89 specifically include: (1) depositing a metal material and planarizing it to form the contact structure 81 in the contact hole 701; (2) depositing a metal material on the surface of the second dielectric layer 71 and patterning it to form the metal structure 89. The planarization can be achieved by a chemical mechanical polishing (CMP) process. The patterning can refer to the existing metal patterning process and will not be described in detail here.

[0046] In this embodiment, the top surface of the contact structure 81 is flush with the top surface of the second dielectric layer 71. The material of the contact structure 81 may be metal tungsten.

[0047] In this embodiment, a connection structure 82 is formed while forming the contact structure 81. The connection structure 82 penetrates the second dielectric layer 71 and the first dielectric layer 51 in a direction perpendicular to the surface of the substrate 40, and the connection structure 82 is spaced apart from the contact structure 81. A portion of the connection structure 82 is used to contact the substrate 40 (specifically, to contact the contact layer 41 above another active region 401 without a memory cell in the substrate 40), and a portion of the connection structure 82 is used to contact the gate structure 49. Through the contact structure 81 and the connection structure 82, the lead-out structure on the upper electrode (second electrode layer) of the memory cell and the active region / gate structure without a memory cell are led out.

[0048] In this embodiment, the metal structure 89 is in one-to-one contact with the connection structure 82. The metal structure 89 serves as a pad. The material of the metal structure 89 is selected from aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.

[0049] Based on the same inventive concept, the present invention also provides a new type of memory with a 3D structure prepared by the above method of the present invention.

[0050] See also Figures 4 to 8 The novel memory with a 3D structure described in this embodiment includes: a substrate 40 , an active region 401 , a first dielectric layer 51 , a storage unit 60 , a lead structure 64 , a second dielectric layer 71 , a contact structure 81 , and a metal structure 89 .

[0051] Specifically, the active area 401 is defined in the substrate 40. In this embodiment, a gate structure 49 is formed on the surface of the substrate 40, and the active area 401 is defined in the substrate 40 between two adjacent gate structures 49. The novel memory of the 3D structure also includes: a contact layer 41, which covers the surface of the substrate 40 and exposes the gate structure 49. Specifically, the material of the contact layer 41 is metal silicide. The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491.

[0052] Specifically, the first dielectric layer 51 covers the surface of the substrate 40, and a groove 510 (such as a groove 510) is formed in the first dielectric layer 51, which penetrates the first dielectric layer 51 in a direction perpendicular to the surface of the substrate 40 and exposes a portion of the active area 401. Figure 5B shown).

[0053] Specifically, the storage unit 60 is continuously distributed on the inner wall of the groove 510, and the storage unit 60 includes a first electrode layer 61, a storage layer 62, and a second electrode layer 63 which are sequentially stacked, and at the bottom of the groove 510, the first electrode layer 61 is in contact with the active area 401. The lead-out structure 64 covers the second electrode layer 63 and fills the groove 510.

[0054] Specifically, the second dielectric layer 71 covers the first dielectric layer 51, all the storage units 60 and all the lead-out structures 64, and a contact hole 701 (such as a hole 702) is formed in the second dielectric layer 71, penetrating the second dielectric layer 71 in a direction perpendicular to the surface of the substrate 40 and exposing a portion of the lead-out structure 64. Figure 7B shown).

[0055] Specifically, the contact structure 81 fills the contact hole 701 and contacts the lead-out structure 64. The metal structure 89 is located on the surface of the second dielectric layer 71 and contacts the contact structure 81.

[0056] In this embodiment, the materials of the first electrode layer 61 and the second electrode layer 63 are both titanium nitride, the material of the storage layer 62 is ferroelectric material or phase change material, the material of the first dielectric layer 51 and the second dielectric layer 71 is oxide (for example, silicon oxide), the material of the contact structure 81 is metal tungsten, and the material of the metal structure 89 is selected from aluminum, copper, or aluminum-copper alloy.

[0057] In this embodiment, the top surface of the contact structure 81 is flush with the top surface of the second dielectric layer 71 .

[0058] In this embodiment, the novel memory of the 3D structure further includes: a connection structure 82, which is formed by the same process as the contact structure 81; the connection structure 82 penetrates the second dielectric layer 71 and the first dielectric layer 51 in a direction perpendicular to the surface of the substrate 40, and the connection structure 82 is spaced apart from the contact structure 81. A portion of the connection structure 82 is used to contact the substrate 40 (specifically, to contact the contact layer 41 above another active area 401 without a storage unit in the substrate 40), and a portion of the connection structure 82 is used to contact the gate structure 49. Through the contact structure 81 and the connection structure 82, the lead-out structure on the upper electrode (second electrode layer) of the storage unit and the active area / gate structure without a storage unit are led out. The metal structure 89 is also in one-to-one contact with the connection structure 82. The metal structure 89 serves as a pad.

[0059] In this embodiment, the storage units 60 are continuously distributed on the inner wall of the trench 510 and a portion of the surface of the first dielectric layer 51 adjacent to the trench 510. Specifically, the first electrode layer 61, the storage layer 62 and the second electrode layer 63 have the same shape.

[0060] In this embodiment, after forming a gate structure (further forming a contact layer), a memory cell is directly formed on the active area, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell is led out through a lead-out structure with a larger size, thereby improving the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components; the lead-out structure and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and the mask process; and the memory cell with a 3D structure continuously distributed on the inner wall of the groove increases the effective area of ​​the phase change.

[0061] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0062] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a novel memory with a 3D structure, characterized in that: The method comprises the following steps: Forming a semiconductor substrate, the semiconductor substrate comprising a substrate, an active region defined in the substrate; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the substrate, and a groove is formed in the first dielectric layer, penetrating the first dielectric layer in a direction perpendicular to the surface of the substrate and exposing a portion of the active area; A storage unit and a lead-out structure are formed in a 3D structure, wherein the storage unit is continuously distributed on the inner wall of the groove, and the storage unit comprises a first electrode layer, a storage layer and a second electrode layer which are stacked in sequence, and at the bottom of the groove, the first electrode layer contacts the active area, and the lead-out structure covers the second electrode layer and fills the groove; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer, all the storage units and all the lead-out structures, and a contact hole penetrating the second dielectric layer in a direction perpendicular to the substrate surface and exposing a portion of the lead-out structure is formed in the second dielectric layer; as well as A contact structure and a metal structure are formed, wherein the contact structure fills the contact hole and contacts the lead-out structure, and the metal structure is located on the surface of the second dielectric layer and contacts the contact structure.

2. The method according to claim 1, characterized in that The storage units are continuously distributed on the inner wall of the trench and a portion of the surface of the first dielectric layer adjacent to the trench.

3. The method according to claim 1, characterized in that The step of forming the first dielectric layer specifically includes: forming a first etch stop layer covering the surface of the substrate, forming the first dielectric layer covering the first etch stop layer, and forming a first protective layer covering the first dielectric layer; The first etch barrier layer is used as an etch stop layer, and the first protection layer and the first dielectric layer are etched to form the groove.

4. The method according to claim 1, characterized in that: The steps of forming the storage unit and the lead-out structure of the 3D structure specifically include: Depositing a first electrode material layer, a storage material layer and a second electrode material layer in sequence on the inner wall of the groove and the surface of the first dielectric layer; Depositing a lead-out material layer covering the second electrode material layer and filling the groove; The first electrode material layer, the storage material layer, the second electrode material layer and the lead-out material layer are patterned to form the first electrode layer, the storage layer, the second electrode layer which are continuously distributed on the inner wall of the groove and stacked in sequence, and the lead-out structure which covers the second electrode layer and fills the groove.

5. The method according to claim 1, characterized in that The step of forming the second dielectric layer specifically includes: forming a second etch stop layer covering the first dielectric layer, all the storage units and all the lead-out structures, forming the second dielectric layer covering the second etch stop layer, and forming an etch protection layer covering the second dielectric layer; The second etch barrier layer is used as an etch stop layer, and the etch protection layer and the second dielectric layer are etched to form the contact hole.

6. The method according to claim 1, characterized in that The steps of forming the contact structure and the metal structure specifically include: Depositing a metal material and planarizing it to form the contact structure in the contact hole, wherein the top surface of the contact structure is flush with the top surface of the second dielectric layer; A metal material is deposited on the surface of the second dielectric layer and patterned to form the metal structure.

7. The method according to claim 1, characterized in that A gate structure is also formed on the surface of the substrate, and the active region is defined in the substrate between two adjacent gate structures; the step of forming a 3D structure memory cell further includes: A contact layer is formed, wherein the contact layer covers the surface of the substrate and exposes the gate structure.

8. The method according to claim 1, characterized in that: A connection structure is formed while forming the contact structure. The connection structure penetrates the second dielectric layer and the first dielectric layer in a direction perpendicular to the substrate surface, and the connection structure is spaced apart from the contact structure.

9. The method according to claim 1, characterized in that: The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the first dielectric layer and the second dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

10. A new type of memory with 3D structure, characterized in that: include: A substrate having an active region defined therein; A first dielectric layer covering the surface of the substrate, wherein a groove is formed in the first dielectric layer and penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate and exposes a portion of the active area; A storage unit is continuously distributed on the inner wall of the groove, and the storage unit includes a first electrode layer, a storage layer and a second electrode layer which are sequentially stacked, and the first electrode layer is in contact with the active area at the bottom of the groove; A lead-out structure covering the second electrode layer and filling the groove; A second dielectric layer, covering the first dielectric layer, all the storage units and all the lead-out structures, wherein a contact hole is formed in the second dielectric layer and penetrates the second dielectric layer in a direction perpendicular to the substrate surface and exposes a portion of the lead-out structure; A contact structure, filling the contact hole and contacting the lead-out structure; as well as The metal structure is located on the surface of the second dielectric layer and is in contact with the contact structure.

11. The novel 3D structured memory according to claim 10, characterized in that: The storage units are continuously distributed on the inner wall of the trench and a portion of the surface of the first dielectric layer adjacent to the trench.

12. The novel 3D structured memory according to claim 10, characterized in that: The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxides, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

13. The novel 3D structured memory according to claim 10, characterized in that: Also includes: A gate structure is formed on the surface of the substrate, and the active area is defined in the substrate between two adjacent gate structures; The contact layer covers the surface of the substrate and exposes the gate structure.

14. The novel 3D structured memory according to claim 13, characterized in that: The material of the contact layer is metal silicide.

15. The novel 3D structured memory according to claim 10, characterized in that: The substrate surface is covered with a first etch stop layer, the first dielectric layer surface is covered with a first protective layer, the lead-out structure surface away from the first dielectric layer is covered with a second protective layer, and the first protective layer and the second protective layer surface are covered with a second etch stop layer.

16. The novel 3D structured memory according to claim 15, characterized in that: The materials of the first etch stop layer and the second etch stop layer are both silicon nitride, and the materials of the first protection layer and the second protection layer are both silicon oxynitride.

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