SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with fast recovery and low power consumption characteristics

Abstract

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with fast recovery and low power consumption characteristics, and belongs to the technical field of semiconductors. The device includes: a drain metal contact; the substrate is formed on the contact surface of the drain electrode metal; the drift region is formed on the surface of the substrate; the NCSL is formed on the surface of the drift region; the first Pbase is formed on the surface of the NCSL; the first source region is formed on the surface of the first Pbase; the second Pwell is formed on the surface of the drift region; the second P + region is formed on the surface of the second Pwell; the first P-well is formed on the surface of the drift region; the first P + region is formed on the surface of the first Pwell; the MOS channel diode is formed on the surface of the second P-well; the L-shaped split gate is formed on the surfaces of the MOS channel diode and the NCSL; and a source metal contact formed on the top of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a SiC MOSFET device with fast recovery and low power consumption characteristics. Background Art

[0002] With the rise of new energy, electric vehicles, smart grids and other emerging fields, people's demand for power devices that can withstand high voltage, radiation, high frequency and low power consumption is increasing day by day. SiC materials have unique advantages such as wide bandgap, high breakdown electric field and high electron saturation drift velocity, which can simultaneously achieve the three characteristics of "high withstand voltage", "low on-resistance" and "high frequency". In recent years, trench SiC MOSFET has received more and more attention due to its compact cell design and weakened junction field effect transistor (JFET) effect. Trench SiC MOSFET with good gate oxide reliability has been proven and successfully manufactured.

[0003] However, today's trench SiC MOSFET still has the problems of high on-state voltage drop (about 2-3V) and bipolar degradation of the parasitic body diode, which will lead to large freewheeling losses and reduced device reliability. To solve this problem, researchers often solve this problem by externally integrating anti-parallel Schottky barrier diodes (SBDs), but this will increase the module size and module capacitance. Therefore, internal integration of freewheeling diodes has become a common and concerned solution for researchers, such as internal integration of SBDs, heterojunction diodes, and trench diodes. However, SBDs have large reverse leakage currents at high temperatures, and heterojunction diodes have complex interface states, which has prevented them from being widely adopted. The excellent performance of trench diodes is a good solution. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a SiC MOSFET device with fast recovery and low power consumption characteristics, the device integrates an L-type split gate and a low-barrier MOS channel diode, reduces the gate-source capacitance of the device by wrapping the main gate polysilicon with the source auxiliary gate polysilicon, optimizes the switching characteristics of the device, reduces the gate-source capacitance of the device by the insulating medium between the source auxiliary gate polysilicon and the main gate polysilicon, and reduces the requirements of the device on the driving circuit. The low-barrier MOS channel diode shields the conduction of the device body diode in the case of reverse conduction, avoids the bipolar degradation effect, and improves the third quadrant characteristics of the device.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A SiC MOSFET device with fast recovery and low power consumption characteristics, comprising:

[0007] Drain metal contact;

[0008] a substrate formed on the drain metal contact surface;

[0009] a drift region formed on the surface of the substrate;

[0010] N_CSL formed on the surface of the drift region;

[0011] A first P_base formed on the surface of the N_CSL;

[0012] A first source region formed on the surface of the first P_base;

[0013] A second P_well formed on the surface of the drift region and located on one side of the N_CSL;

[0014] A second P+ region formed on the surface of the second P_well;

[0015] A first P-well formed on the surface of the drift region and located on the other side of the N_CSL;

[0016] A first P+ region formed on the surface of the first P_well;

[0017] A MOS channel diode formed on the surface of the second P-well and located between the N_CSL and the second P+ region;

[0018] an L-shaped split gate formed on the surface of the MOS channel diode and N_CSL and adjacent to the first P_base and the first source region; and

[0019] The source metal contact is formed on the top of the device.

[0020] The second P_well, the second P+ region, the source metal contact, the first P+ region and the first P_well form a source trench structure, and the source trench structure covers the top of the device.

[0021] Furthermore, the L-type split gate includes source auxiliary gate polysilicon, main gate polysilicon and an insulating dielectric layer. The insulating dielectric layer is respectively adjacent to the MOS channel diode, N_CSL, the first P_base, the first source region and the source metal contact; the source auxiliary gate polysilicon and the main gate polysilicon are both located in the insulating dielectric layer, wrapped by the insulating dielectric layer, and separated by the insulating dielectric.

[0022] The source auxiliary gate polysilicon is in an L-shaped structure, the main gate polysilicon is in a rounded rectangular structure, and the inner side surfaces of the main gate polysilicon and the source auxiliary gate polysilicon are aligned.

[0023] The source auxiliary gate polysilicon is placed below the main gate polysilicon in the form of an L-shaped split gate, which has the effect of shielding the gate-drain capacitance, and the thicker L-shaped insulating medium between the source auxiliary gate polysilicon and the main gate polysilicon plays a role in shielding the gate-source capacitance, thereby reducing the gate-drain capacitance and gate-source capacitance of the device; in addition, the L-shaped insulating medium located at the lower right of the source auxiliary gate polysilicon can also make the second P-base inverted to form a MOS channel diode when the device is turned on in the third quadrant, thereby shielding the conduction of the body diode.

[0024] Furthermore, the MOS channel diode includes a second source region and a second P-base. The second source region is adjacent to the second P+ region, and the second P_base is located between the second source region and the N_CSL; through the MOS channel diode, when the device operates in the third quadrant, the electron barrier from the N_CSL to the second source region can be approximated to a low-barrier MOS channel diode to shield the conduction of the body diode and avoid the bipolar degeneration effect.

[0025] The source auxiliary gate polysilicon is the gate of the diode, the source metal contact is the source of the diode, the drain metal contact is the drain of the diode, and the insulating dielectric layer is the gate oxide layer of the diode.

[0026] When the device operates in the third quadrant, a low-barrier MOS channel diode can be realized by adjusting the concentration, length and thickness of the second P_base, or by adjusting the bottom thickness of the insulating dielectric layer.

[0027] The beneficial effects of the present invention are as follows: the present invention proposes a SiCMOSFET device with fast recovery and low power consumption characteristics. Compared with the traditional asymmetric trench SiC MOSFET device, the present invention improves the voltage resistance of the device through the source trench structure; the gate-source capacitance and gate-drain capacitance of the device are greatly reduced through the L-type separated gate, which significantly improves the switching characteristics of the device, reduces the switching loss, and reduces the requirements of the device for the driving circuit; the body diode is shielded by the low-barrier MOS channel diode, which can significantly improve the third quadrant performance of the device and avoid the bipolar degradation effect.

[0028] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 A schematic diagram of the structure of a SiC MOSFET device with fast recovery and low power consumption characteristics provided by one embodiment of the present invention;

[0031] Figure 2 for Figure 1 An equivalent circuit diagram of the device;

[0032] Figure 3 To compare the static characteristic diagrams of the device of the present invention and the conventional asymmetric trench SiC MOSFET device at different N_CSL region concentrations;

[0033] Figure 4 In the blocking state, the device of the present invention and the conventional asymmetric trench SiC MOSFET device are ds = 800V, the maximum electric field strength comparison of the gate oxide layer;

[0034] Figure 5 The total current density comparison between the device of the present invention and the conventional asymmetric trench SiC MOSFET device under forward conduction;

[0035] Figure 6 The reverse conduction curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET device are compared in the third quadrant;

[0036] Figure 7 In the third quadrant, the device of the present invention and the conventional asymmetric trench SiC MOSFET device are ds =-100A, comparison of the hole current density diagram of the device;

[0037] Figure 8 Comparison of reverse recovery characteristic curves of the device of the present invention and a conventional asymmetric trench SiC MOSFET device;

[0038] Fig. 9 Comparison of capacitance characteristic curves of the device of the present invention and a conventional asymmetric trench SiC MOSFET device;

[0039] Fig.10 Comparison of gate charge characteristic curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET device;

[0040] Fig.11 The switching process curves of the device of the present invention and the traditional asymmetric trench SiC MOSFET device are compared. Fig.11 (a) is a schematic diagram of the closing process of the two devices. Fig.11 (b) is a schematic diagram of the opening process of the two devices;

[0041] Fig.12 The switching loss curves of the device of the present invention and the traditional asymmetric trench SiC MOSFET device are compared. Fig.12 (a) is the schematic diagram of the shutdown process loss. Fig.12 (b) is a schematic diagram of the loss during the opening process;

[0042] Fig.13 V gs =-5V, V ds = 0V, the relationship between the length of the integrated low-barrier MOS trench diode and the conduction band energy distribution at the SiC / oxide interface;

[0043] Fig.14 V gs =-5V, V ds = 0V, the relationship between the thickness of the integrated low-barrier MOS trench diode and the conduction band energy distribution at the SiC / oxide interface;

[0044] Fig.15 V gs =-5V, V ds = 0V, the relationship between the right P_base region concentration of the integrated low-barrier MOS trench diode and the conduction band energy distribution at the SiC / oxide interface;

[0045] Fig.16 V gs =-5V, V ds Relationship between size and conduction band energy distribution at SiC / oxide interface;

[0046] Fig.17 Schematic diagram of the main process flow of the SiC MOSFET device of the present invention;

[0047] Figure numerals: 1-drain metal contact region, 2-N+ substrate, 3-N-drift region, 4-right P_well, 5-right P+ region, 6-right N+ source region, 7-right P_base, 8-source auxiliary gate polysilicon, 9-source metal contact region, 10-insulating dielectric layer, 11-main gate polysilicon, 12-left P_base, 13-left N+ source region, 14-left P+ region, 15-left P_well, 16-N_CSL. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0049] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0050] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0051] like Figure 1 As shown, a SiCMOSFET device with fast recovery and low power consumption characteristics is provided in one embodiment of the present invention. The device can be divided into four parts according to the structural characteristics, namely, a basic structure, an L-type separated gate structure, a source groove structure and a MOS channel diode structure.

[0052] The device structure is asymmetric, with double trenches, L-type separated gate and MOS channel diode. The device structure specifically includes: drain metal contact area 1, N+ substrate 2, N- drift area 3, right P_well4, right P+ area 5, right N+ source area 6, right P_base7, source auxiliary gate polysilicon 8, source metal contact area 9, insulating dielectric layer 10, main gate polysilicon 11, left P_base12, left N+ source area 13, left P+ area 14, left P_well15, N_CSL16.

[0053] The basic structure includes: a drain metal contact region 1, an N+ substrate 2, an N-drift region 3, a left P_base 12, a left N+ source region 13, and an N_CSL 16.

[0054] The drain metal contact region 1 is located on the lower surface of the N+ substrate 2; the N+ substrate 2 is located on the lower surface of the N-drift region 3 and the upper surface of the drain metal contact region 1, respectively, and its thickness is 3 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 2×10 19 cm -3 .

[0055] The N-drift region 3 is located on the upper surface of the N+ substrate 2 and the lower surfaces of the right P_well4, the left P_well15 and the N_CSL16. Its thickness is 11 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 6×10 15 cm -3 .

[0056] The left P_base12 is located on the upper surface of the left P_well15 and N_CSL16 and the lower surface of the left N+ source region 13. At the same time, the side surface is in contact with the source metal contact region 9 and the insulating dielectric layer 10. Its thickness is 1μm and its width is 0.7μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 2×10 17 cm -3 .

[0057] The left N+ source region 13 is located on the upper surface of the left P_base 12 and the lower surface of the source metal contact region 9, and the side surface is in contact with the source metal contact region 9 and the insulating dielectric layer 10. Its thickness is 0.25μm and its width is 0.7μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 .

[0058] N_CSL16 is located on the upper surface of N-drift region 3 and the lower surface of left P_base12 and insulating dielectric layer 10. At the same time, the left side is in contact with the left P_well15, and the right side is in contact with the right P_base7 and the right P_well region 4. Its shape is an irregular rectangle with a thickness of 1.5 μm, a lower width of 1.1 μm, and an upper width of 0.6 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 8×10 16 cm -3 .

[0059] The L-type split gate structure includes: source auxiliary gate polysilicon 8, main gate polysilicon 11, and insulating dielectric layer 10.

[0060] The source auxiliary gate polysilicon 8 is in an L-shaped structure and is wrapped by an insulating dielectric layer 10 . The thickness is 1.87 μm, the lower width is 0.9 μm, the upper width is 0.5 μm, and the material is pure polysilicon.

[0061] The main gate polysilicon 11 has a rounded rectangular structure, with its right side aligned with the left side of the source auxiliary gate polysilicon 8 and also wrapped by the insulating dielectric layer 10 . The thickness is 1.6 μm, the width is 0.2 μm, and the material is pure polysilicon.

[0062] The insulating dielectric layer 10 wraps the source auxiliary gate polysilicon 8 and the main gate polysilicon 11, and is located at the upper right corner of N_CSL16, the upper surface of the right P_base7 and the right N+ source region 6, and contacts the source metal contact region 9 on the top, and contacts the left P_base12 and the left N+ source region 13 on the left side, with a thickness of 0.05μm on the left side and 0.05μm on the right side. In the insulating dielectric layer 10, the main gate and the source auxiliary gate are separated by an L-shaped insulating dielectric layer, and its thickness (i.e., the distance between the main gate and the source auxiliary gate) is 0.2μm; the right side and the bottom side of the source auxiliary gate are also separated from the source metal contact region 9, N_CSL16, the right N+ source region 6 and the right P_base7 by an L-shaped insulating dielectric layer, and its thickness (i.e., the distance between the source auxiliary gate and the edge of the insulating dielectric layer 10) is 0.03μm.

[0063] The source trench structure includes: a right P_well 4 , a right P+ region 5 , a source metal contact region 9 , a left P+ region 14 , and a left P_well 15 .

[0064] Among them, the right P_well4 is located on the upper surface of the N-drift region 3 and the lower surface of the right P+ region 5, the right N+ source region 6 and the right P_base7. The left side is in contact with the N_CSL16. Its thickness is 0.6μm and its width is 1μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 18 cm -3 .

[0065] The right P+ region 5 is located on the upper surface of the N-drift region 3 and the lower surface of the source metal contact region 9. The left side is in contact with the right N+ source region 6. Its thickness is 0.25μm and its width is 0.2μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 .

[0066] The source metal contact area 9 has an inverted concave structure and is inverted on the top of the device. It is located on the upper surfaces of the right P+ area 5, the right P_base7, the insulating dielectric layer 10, the left N+ source area 13, the left P_well15, and the left P+ area 14, and is in contact with the side surfaces of the insulating dielectric layer 10, the left N+ source area 13, the left P_base12, and the left P_well15.

[0067] The left P+ region 14 is located at the upper left corner of the left P_well 15, and contacts the source metal contact region 9. Its thickness is 0.25 μm and its width is 0.2 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 ;

[0068] The left P_well 15 presents an L-shaped structure, located on the upper surface of the N-drift region 3 and the source metal contact region 9 and the lower surface of the left P_base 12, and the upper left corner is in contact with the left P+ region 14. Its thickness is 1.5μm, the lower side width is 0.5μm, and the upper side width is 0.1μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 18 cm -3 .

[0069] The MOS channel diode structure comprises: a right N+ source region 6 and a right P_base 7.

[0070] The right N+ source region 6 is located on the upper surface of the right P_well 4 and the lower surface of the source metal contact region 9 and the insulating dielectric layer 10. The left side is in contact with the right P_base 7, and the right side is in contact with the right P+ region 5. The thickness is 0.25 μm and the width is 0.4 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 .

[0071] The right P_base7 is located on the upper surface of the right P_well4 and the lower surface of the insulating dielectric layer 10, the left side is in contact with the N_CSL16, and the right side is in contact with the right N+ source region 6. Its thickness is 0.25μm and its width is 0.4μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 4×10 16 cm -3 .

[0072] like Figure 2 The equivalent circuit diagram of the device of the present invention is shown in FIG. Figure 2 It can be seen that the asymmetric trench SiC MOSFET device actually integrates a MOS channel diode regulated by a potential barrier to shield the conduction of the body diode.

[0073] Figure 3 The figure shows the performance of pulling the N_CSL region of the device of the present invention and the traditional asymmetric trench SiC MOSFET device at different concentrations. The N_CSL concentrations of the two devices with the best static characteristics are selected for subsequent simulations. The static characteristics are judged by the Baliga figure of merit BFOM. The larger the value, the better the static characteristics of the device. Among them, the N_CSL concentration of the device of the present invention is selected as 8×10 16 cm -3 The N_CSL concentration of the conventional asymmetric trench SiC MOSFET device is selected as 5×10 16 cm -3 According to the final static characteristics, it can be found that the breakdown voltage of the device of the present invention is higher than that of the conventional asymmetric trench SiC MOSFET device, but the conduction characteristics are slightly worse than those of the conventional asymmetric trench SiC MOSFET device.

[0074] like Figure 4 As shown, the device of the present invention and the conventional asymmetric trench SiC MOSFET device are both in the forward blocking state, V ds When =800V, the maximum electric field strength of the gate oxide layer of the device. It can be seen that the gate oxide layer strength of the device is lower than 3MV / cm, which can ensure the long-term reliability of the gate oxide layer of the device.

[0075] like Figure 5 As shown, the total current distribution diagram of the two devices is shown when both the device of the present invention and the traditional asymmetric trench SiC MOSFET device are in the forward conduction state. It can be seen that due to the source trench structure adopted in the device of the present invention, the left P_well expands wider to the right, thereby narrowing the conduction channel, and since the device of the present invention adopts an L-type split gate structure, the source auxiliary gate cannot produce an electron aggregation effect compared to the main gate under the forward conduction condition, so the conduction characteristics are slightly worse than those of the traditional asymmetric trench SiC MOSFET device.

[0076] like Figure 6 As shown, the reverse conduction curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET device are in the third quadrant. It can be seen that when I ds = -100A, the V of the conventional asymmetric trench SiC MOSFET device ds =-2.92V, while the V ds =-2.34V, which realizes the effect of shielding the body diode with a low-barrier MOS channel diode under reverse conduction and eliminates the bipolar degeneration effect.

[0077] like Figure 7As shown, the device of the present invention and the conventional asymmetric trench SiC MOSFET device are in the third quadrant, I ds = -100A, the hole current distribution diagrams of the two devices show that the conventional asymmetric trench SiC MOSFET device realizes freewheeling through body diode conduction, its conduction mode is bipolar, and the hole current is distributed in the entire device, while the device of the present invention conducts through a low-barrier MOS trench diode, its conduction mode is unipolar electron conduction, and the hole current is less distributed in the entire device. Compared with the conventional asymmetric trench SiC MOSFET device, the device of the present invention has a ds = Reverse conduction voltage drop V at -100A cut-in A decrease of 19.8%.

[0078] like Figure 8 The figure shows the reverse recovery characteristics of the device of the present invention and the traditional asymmetric trench SiC MOSFET device. In the device of the present invention, due to the presence of the low-barrier MOS trench diode, the body diode is inhibited from turning on during the reverse conduction process, which greatly reduces the injection efficiency of the body diode holes, thereby reducing the reverse recovery charge, reducing the reverse recovery loss, and improving the reverse recovery performance of the device. Figure 8 It can be seen that the reverse recovery time of the conventional asymmetric trench SiC MOSFET device is 86.1834ns, while the reverse recovery time of the device of the present invention is 54.5827ns, which is 36.67% less than that of the conventional device; the reverse recovery current peak value of the conventional asymmetric trench SiC MOSFET device is -47.75A / cm 2 , while the peak reverse recovery current of the device of the present invention is -34.08A / cm 2 , which is 27.66% less than that of traditional devices; the reverse recovery charge of traditional asymmetric trench SiC MOSFET devices is 2.4855uC / cm 2 The reverse recovery charge of the device of the present invention is 1.13479uC / cm 2 , compared with traditional devices, it is reduced by 54.34%.

[0079] like Fig. 9 As shown in FIG. 1 , the capacitance characteristics of the device of the present invention and the conventional asymmetric trench SiC MOSFET device are compared. As can be seen from the figure, compared with the conventional device, the C iss Down 50.85%, C rss Down 79.61%, C oss The device of the present invention achieves the above optimization of parasitic capacitance mainly through the shielding effect of the L-type split gate and the isolation effect of the gate oxide layer between the main gate and the source auxiliary gate.

[0080] like Fig.10 As shown in FIG. 1 , the gate charge characteristics of the device of the present invention and the conventional asymmetric trench SiC MOSFET device are compared. Fig.10 It can be seen that the gate-drain charge of the traditional asymmetric trench SiC MOSFET device is 59.94nC / cm 2 , V gs = Gate charge at 15V is 765.75nC / cm 2 The gate-drain charge of the device of the present invention is 35.11nC / cm 2 , V gs = Gate charge at 15V is 418.65nC / cm 2 , achieving a 41.42% decrease in gate-drain charge, V gs =15V, the gate charge decreased by 45.33%, which significantly improved the switching performance of the device.

[0081] like Fig.11 As shown in FIG. 1 , the switching process of the device of the present invention and the conventional asymmetric trench SiC MOSFET device is compared. Fig.12 As shown, there is a comparison of the losses generated during the switching process of the device of the present invention and the conventional asymmetric trench SiC MOSFET device, wherein the losses are obtained by multiplying the voltage by the current during the switching process. Fig.12 (a) is a schematic diagram of the loss generated during the turn-off process of the two devices. It can be seen that the turn-off loss of the traditional asymmetric trench SiC MOSFET device is 1.67mJ / cm 2 The turn-off loss of the device of the present invention is 0.758231 mJ / cm 2 , achieving a 54.6% reduction in turn-off losses. Fig.12 (b) is a schematic diagram of the loss generated during the turn-on process of the two devices. It can be seen that the turn-on loss of the traditional asymmetric trench SiC MOSFET device is 1.37mJ / cm 2 The turn-on loss of the device of the present invention is 0.0364336 mJ / cm 2 , achieving a 97.34% reduction in turn-on losses.

[0082] like Fig.13 As shown, V gs =-5V, V ds=0V, the relationship between the length of the integrated low-barrier MOS trench diode and the conduction band energy distribution at the SiC / oxide interface. From the figure, it can be seen that the shorter the length of the MOS trench diode, the smaller the potential energy that the electrons need to cross, and the smaller the turn-on voltage of the MOS trench diode. However, when the length of the MOS trench diode becomes too narrow, it will cause premature punch-through breakdown in the forward blocking state, resulting in a significant drop in the breakdown voltage. In order to keep consistent with the right length of the traditional asymmetric trench SiC MOSFET device, L_rbase = 0.4um is finally used as the final size.

[0083] like Fig.14 As shown, V gs =-5V, V ds =0V, the relationship between the thickness of the integrated low-barrier MOS channel diode and the conduction band energy distribution at the SiC / oxide interface. It can be seen from the figure that the thicker the MOS channel diode is, the smaller the potential energy that electrons need to cross, and the smaller the turn-on voltage of the MOS channel diode is. However, this will lead to a decrease in the device withstand voltage under forward blocking conditions, so H_rbase=0.25um is ultimately used as the final size.

[0084] like Fig.15 As shown, V gs =-5V, V ds =0V, the relationship between the doping concentration of the right P_base region of the integrated low-barrier MOS trench diode and the conduction band energy distribution at the SiC / oxide interface. From the figure, it can be seen that the lower the doping concentration of the right P_base region of the MOS trench diode, the smaller the potential energy that the electrons need to cross, and the smaller the turn-on voltage of the MOS trench diode. However, the reduction of the doping concentration of the right P_base region will also lead to premature punch-through breakdown in the forward blocking condition, thereby significantly reducing the breakdown voltage, and finally P_rbase_doping=7e16cm -3 as the final parameter.

[0085] like Fig.16 As shown, V gs =-5V, V ds The relationship between the size and the conduction band energy distribution at the SiC / oxide interface. From this figure, it can be seen that as V sd The increase of V sd After >2V, the electrons are almost not blocked by potential barriers, and the MOS channel diode is turned on.

[0086] like Fig.17As shown, it is the manufacturing process flow of the device of the present invention. Considering the feasibility of the process, most of the process steps are compatible with the general manufacturing process of the conventional asymmetric trench SiC MOSFET, including epitaxial growth, N+ source and P well implantation, trench etching, P base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition and metallization. The difference is that in the process flow of this embodiment, the gate trench needs to be subjected to multiple polysilicon gate deposition, trenching and gate oxidation to form an L-shaped split gate, and the source is also grooved, and ion implantation is required at the bottom and sidewalls of the source trench to reduce the electric field peak at the corner of the oxide layer.

[0087] Table 1 below shows a comparison of key performance indicators of conventional asymmetric trench SiC MOSFET devices and the device of the present invention, including the on-resistance R on , breakdown voltage BV, reverse conduction voltage drop V cut-in , reverse recovery charge Q trr , reverse recovery time t rr , reverse recovery current peak I rm , gate-drain charge Q gd , gate charge Q g , turn-off loss E off and turn-on loss E on It can be seen that compared with the conventional asymmetric trench SiC MOSFET device, the device of the present invention has better characteristics than the conventional device except that the conduction characteristic is slightly insufficient.

[0088] Table 1

[0089]

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A SiC MOSFET device with fast recovery and low power consumption characteristics, characterized in that: The device includes: Drain metal contact; a substrate formed on the drain metal contact surface; a drift region formed on the surface of the substrate; N_CSL formed on the surface of the drift region; A first P_base formed on the surface of the N_CSL; A first source region formed on the surface of the first P_base; A second P_well formed on the surface of the drift region and located on one side of the N_CSL; A second P+ region formed on the surface of the second P_well; A first P-well formed on the surface of the drift region and located on the other side of the N_CSL; A first P+ region formed on the surface of the first P_well; A MOS channel diode formed on the surface of the second P-well and located between the N_CSL and the second P+ region; an L-shaped split gate formed on the surface of the MOS channel diode and N_CSL and adjacent to the first P_base and the first source region; and The source metal contact is formed on the top of the device.

2. The SiC MOSFET device according to claim 1, characterized in that: The MOS channel diode includes a second source region and a second P-base; the second source region is adjacent to the second P+ region, and the second P_base is located between the second source region and the N_CSL; through the MOS channel diode, when the device operates in the third quadrant, the electron potential barrier from the N_CSL to the second source region becomes a low-barrier MOS channel diode to shield the conduction of the body diode.

3. The SiC MOSFET device according to claim 2, characterized in that: When the device works in the third quadrant, a low-barrier MOS channel diode is realized by adjusting the concentration, length and thickness of the second P_base.

4. The SiC MOSFET device according to claim 1, characterized in that: The L-shaped split gate includes a source auxiliary gate polysilicon, a main gate polysilicon and an insulating dielectric layer; the insulating dielectric layer is respectively adjacent to the MOS channel diode, N_CSL, the first P_base, the first source region and the source metal contact; the source auxiliary gate polysilicon and the main gate polysilicon are both located in the insulating dielectric layer and separated by the insulating dielectric.

5. The SiC MOSFET device according to claim 4, characterized in that: The source auxiliary gate polysilicon is in an L-shaped structure, and the main gate polysilicon is in a rounded rectangular structure; the main gate polysilicon is aligned with the inner side surface of the source auxiliary gate polysilicon, and the gate-source capacitance is shielded by the insulating medium between the main gate polysilicon and the source auxiliary gate polysilicon.

Images