Groove MOS (Metal Oxide Semiconductor) device and preparation method of groove MOS device

Abstract

The invention discloses a groove MOS device and a preparation method of the groove MOS device, an epitaxial layer in the groove MOS device comprises a first epitaxial layer and a second epitaxial layer which are laminated, the first epitaxial layer has a first doping type, and the second epitaxial layer has a second doping type; the trench gate structure is located in the epitaxial layer, the surface, close to the substrate, of the trench gate structure is in contact with the first epitaxial layer, and the trench gate structure comprises a gate electrode and a gate oxide layer; the Schottky diode structure is located on one side of the trench gate structure in the first direction and comprises a first injection region, an insulation region and a doped region, the insulation region and the doped region are arranged in a laminated mode, the insulation region is located on one side, close to the substrate, of the doped region, the insulation region and the doped region are both in contact with the trench gate structure, the first injection region is located in the doped region, and the second injection region is located in the doped region. The first injection region and the doped region have different doping types. The problem that the performance of an MOS device is limited by a parasitic diode in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a trench MOS device and a method for preparing the trench MOS device. Background Art

[0002] Power MOSFET has the characteristics of low forward voltage drop, high switching speed, and easy gate control, making it an important semiconductor device in power electronic applications. Power MOSFET is a basic building block in high-power semiconductor devices, such as conductivity modulated bipolar transistors. In some circuits based on power supplies, including switching power supplies, adjustable speed drives, etc., excessive current will flow through the parasitic PN junction diode of the power MOSFET during the device's operating cycle. When used as a front-stage switch of a power converter, the body diode of the power MOSFET acts as a freewheeling diode and flows half of the current during the power conversion cycle. The stored charge of the drift region diode causes the power MOSFET to generate additional reverse recovery current, so the parasitic PN junction body diode limits the device's safe operating area (Service-Oriented Architecture, referred to as SOA), turn-off loss and switching speed. When the MOSFET is used as a synchronous rectifier, it is very important that the current does not pass through the body diode when the device is turned off. The presence of the parasitic diode restricts the control circuit and limits the speed and power consumption of the rectifier. Summary of the invention

[0003] The present application provides a trench MOS device and a method for preparing the trench MOS device to solve the problem in the related art that the parasitic diode limits the performance of the MOS device.

[0004] According to one aspect of the present application, a trench MOS device is provided, comprising: a substrate; an epitaxial layer, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer in a stacked arrangement, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface away from the substrate; at least one trench gate structure, the trench gate structure being located in the epitaxial layer, the surface of the trench gate structure away from the substrate being located in the first surface, the trench gate structure being close to the surface of the substrate and in contact with the first epitaxial layer, the trench gate structure comprising a gate and a gate oxide layer, the gate oxide layer being located at the gate at The gate oxide layer is located on two surfaces opposite to each other in a first direction and on a side of the gate electrode close to the substrate, the first direction is parallel to the first surface; a Schottky diode structure, the Schottky diode structure is located on one side of the trench gate structure in the first direction, the Schottky diode structure includes a first injection region, an insulating region and a doping region, the insulating region and the doping region are stacked, the insulating region is located on a side of the doping region close to the substrate, the insulating region and the doping region are both in contact with the trench gate structure, the first injection region is located in the doping region, and the first injection region and the doping region have different doping types.

[0005] Optionally, the gate oxide layer includes a first region and a second region, the first region is located on a side of the gate away from the Schottky diode structure, the second region is located on a side of the gate close to the substrate, the first region has a first thickness in the first direction, the second region has a second thickness in the second direction, the first thickness is less than the second thickness, wherein the second direction is perpendicular to the first surface.

[0006] Optionally, the doping region has the second doping type, and the first implantation region has the first doping type.

[0007] Optionally, a bottom surface of the Schottky diode structure and a bottom surface of the trench gate structure are located in the same surface.

[0008] Optionally, the device further includes: a second implantation region, the second implantation region is located in the second epitaxial layer, and the second implantation region is in contact with a surface of the trench gate structure away from the Schottky diode structure, and the second implantation region has the first doping type.

[0009] Optionally, the second implantation region has the same doping concentration as the first implantation region.

[0010] Optionally, the device further includes: a plurality of conductive parts, wherein the plurality of conductive parts are respectively in contact with the first injection region, the doping region, the second injection region and the gate, wherein isolation regions are provided between the plurality of conductive parts.

[0011] According to another aspect of the present application, a method for preparing a trench MOS device is provided, which is used to prepare any one of the trench MOS devices, and the preparation method includes: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer including a first epitaxial layer and a second epitaxial layer arranged in a stacked manner, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, and the epitaxial layer having a first surface facing away from the substrate; forming at least one trench gate structure in the epitaxial layer, the surface of the trench gate structure facing away from the substrate is located in the first surface, the trench gate structure is in contact with the first epitaxial layer near the surface of the substrate, and the trench gate structure The structure includes a gate and a gate oxide layer, wherein the gate oxide layer is respectively located on two surfaces of the gate that are opposite to each other in a first direction and the gate oxide layer is located on a side of the gate close to the substrate, and the first direction is parallel to the first surface; a Schottky diode structure is formed on one side of the trench gate structure, and the Schottky diode structure includes a first injection region, an insulating region and a doping region, wherein the insulating region and the doping region are stacked, the insulating region is located on a side of the doping region close to the substrate, and both the insulating region and the doping region are in contact with the trench gate structure, the first injection region is located in the doping region, and the first injection region and the doping region have different doping types.

[0012] Optionally, the step of forming the trench gate structure includes: forming a first trench in the epitaxial layer by an etching process, the bottom surface of the first trench exposing the first epitaxial layer; forming a first insulating layer covering the sidewalls and the bottom surface in the first trench, and the remaining area in the first trench is a second trench; forming the gate and the second insulating layer on the sidewalls of the second trench, wherein the first insulating layer located on the side of the gate close to the substrate, the first insulating layer located on the side of the gate, and the second insulating layer located on the other side of the gate constitute the gate oxide layer.

[0013] Optionally, the remaining area in the second trench is a third trench, and the steps of forming the Schottky diode structure include: forming the doped region in the third trench; forming the first implanted region in the doped region using an ion implantation process, wherein the doped region and the first implanted region have different doping types.

[0014] By applying the technical solution of the present application, a trench MOS device is provided. In the trench MOS device, since the doping region and the first injection region have different doping types, a Schottky Barrier Diode (SBD) can be formed. The Schottky diode is located in the epitaxial layer on one side of the trench gate, and the Schottky diode structure is integrated inside the device, that is, the parasitic diode outside the device is replaced by the Schottky diode structure inside the device, which improves the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode, and can effectively improve the switching speed of the device and reduce the power consumption of the device, thereby enhancing the performance reliability of the MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a trench MOS device according to an embodiment of the present application;

[0017] Figure 2 is a flow chart of a method for preparing a trench MOS device provided according to an embodiment of the present application;

[0018] Figure 3 It is a schematic diagram of a cross-sectional structure of a substrate provided in a method for preparing a trench MOS device provided in an embodiment of the present application;

[0019] Figure 4 is Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the epitaxial layer is shown;

[0020] Figure 5 is Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the first trench is formed in the epitaxial layer shown;

[0021] Figure 6 is Figure 5 The schematic cross-sectional structure diagram of the substrate after the first insulating layer and the second trench are formed on the bottom surface and the sidewall of the first trench;

[0022] Figure 7 is Figure 6 The schematic cross-sectional structure diagram of the substrate after the gate and the second insulating layer are formed on the sidewalls of the second trench;

[0023] Figure 8 A schematic diagram of a basic structure obtained in each step of the method for preparing a Schottky diode structure provided in an embodiment of the present application is shown;

[0024] Fig. 9 is Figure 7 A schematic diagram of the cross-sectional structure of the substrate after the doping region is formed in the trench shown;

[0025] Fig.10 is Fig. 9 A schematic diagram of the cross-sectional structure of the substrate after the first implantation region is formed in the doping region shown;

[0026] Fig.11 is Fig.10 The schematic cross-sectional structure diagram of the substrate after the second implantation region is formed in the first epitaxial layer is shown;

[0027] Fig.12 is Fig.11 A schematic diagram of the cross-sectional structure of the substrate after a dielectric material layer is formed on the substrate shown;

[0028] Fig.13 is Fig.12 The cross-sectional structure diagram of the substrate after a plurality of through holes are formed in the dielectric material layer is shown.

[0029] The above drawings include the following reference numerals:

[0030] 10. substrate; 20. epitaxial layer; 201. first surface; 21. first epitaxial layer; 22. second epitaxial layer; 30. trench gate structure; 31. gate; 311. gate material region; 32. gate oxide layer; 321. first region; 322. second region; 40. Schottky diode structure; 41. first implantation region; 42. insulating region; 43. doping region; 50. second implantation region; 60. conductive portion; 61. first conductive portion; 611 , a first through hole; 62, a second conductive portion; 621, a second through hole; 63, a third conductive portion; 631, a third through hole; 64, a fourth conductive portion; 641, a fourth through hole; 65, a conductive layer; 70, an insulating portion; 71, a dielectric material layer; 81, a first groove; 82, a second groove; 83, a third groove; 84, a fourth groove; 91, a first insulating layer; 911, a first insulating region; 92, a second insulating layer; 921, a second insulating region. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As described in the background technology, in the prior art, a parasitic PN junction diode is provided in a MOSFET device. However, the stored charge of the drift region diode causes the power MOSFET to generate additional reverse recovery current, so the parasitic PN junction body diode limits the safe operating area (SOA), turn-off loss and switching speed of the device. When the MOSFET is used as a synchronous rectifier, it is very important that the current does not pass through the body diode when the device is turned off. The presence of the parasitic diode restricts the control circuit and limits the speed and power consumption of the rectifier. In order to solve the above problems, the present application provides a trench MOS device and a method for preparing a trench MOS device.

[0035] According to an embodiment of the present application, a trench MOS device is provided, such as Figure 1As shown, the MOS device includes: a substrate 10; an epitaxial layer 20, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 which are stacked, the first epitaxial layer 21 has a first doping type, the second epitaxial layer 22 has a second doping type, and the epitaxial layer 20 has a first surface 201 away from the substrate 10; at least one trench gate structure 30, the trench gate structure 30 is located in the epitaxial layer 20, the surface of the trench gate structure 30 away from the substrate 10 is located in the first surface 201, the surface of the trench gate structure 30 close to the substrate 10 is in contact with the first epitaxial layer 21, the trench gate structure 30 includes a gate 31 and a gate oxide layer 32, the gate oxide layer 32 is respectively located at the gate 31 at the first On two surfaces opposite to each other in direction A, the gate oxide layer 32 is located on a side of the gate 31 close to the substrate 10, and the first direction A is parallel to the first surface 201; a Schottky diode structure 40, the Schottky diode structure 40 is located on one side of the trench gate structure 30 in the first direction A, the Schottky diode structure 40 includes a first injection region 41, an insulating region 42 and a doping region 43, the insulating region 42 and the doping region 43 are stacked, the insulating region 42 is located on a side of the doping region 43 close to the substrate 10, the insulating region 42 and the doping region 43 are both in contact with the trench gate structure 30, the first injection region 41 is located in the doping region 43, and the first injection region 41 and the doping region 43 have different doping types.

[0036] In the above trench MOS device, since the doping region and the first implantation region have different doping types, a Schottky diode (SBD) can be formed. The Schottky diode is located in the epitaxial layer on one side of the trench gate, and the Schottky diode structure is integrated inside the device, that is, the parasitic diode outside the device is replaced by the Schottky diode structure inside the device, which improves the problems of the parasitic body diode, such as excessive forward turn-on voltage drop and long reverse recovery time, and can effectively improve the switching speed of the device and reduce the power consumption of the device, thereby enhancing the performance reliability of the MOS device.

[0037] Specifically, the materials of the substrate, epitaxial layer and doped region include silicon carbide, silicon, gallium nitride, gallium oxide, gallium arsenide and aluminum nitride, and those skilled in the art can reasonably select them according to actual needs, and no specific limitation is made without application. The materials of the gate oxide layer and the insulating region include but are not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide and indium tin oxide, and those skilled in the art can reasonably select them according to actual needs, and no specific limitation is made without application.

[0038] Specifically, the SBD composed of the first implantation region and the doping region is current isolated from the epitaxial layer by the insulating region, which controls the current direction and prevents the risk of leakage caused by the increase of voltage at the bottom of the Schottky diode structure after the trench MOS device is turned on.

[0039] In some optional embodiments, such as Figure 1 As shown, the gate oxide layer 32 includes a first region 321 and a second region 322, the first region 321 is located on the side of the gate 31 away from the Schottky diode structure 40, and the second region 322 is located on the side of the gate 31 close to the substrate 10, the first region 321 has a first thickness in a first direction A, and the second region 322 has a second thickness in a second direction B, and the first thickness is less than the second thickness, wherein the second direction B is perpendicular to the first surface 201.

[0040] Specifically, in the trench MOS device, electric field concentration is likely to occur at the bottom of the trench gate due to the gate oxide quality and the trench corner, resulting in deterioration of the breakdown characteristics of the gate oxide layer at the bottom of the trench. In the above embodiment, by increasing the thickness of the first region of the gate oxide layer located at the bottom of the gate, the voltage resistance performance of the bottom of the trench is increased, which not only realizes the protection of the gate, but also avoids the voltage resistance failure of the gate oxide at the bottom of the trench, thereby improving the reliability of the trench gate structure, and further increasing the reliability of the trench MOS device.

[0041] In some optional embodiments, the thickness of the insulating region in the first direction is greater than or equal to the thickness of the first region of the gate oxide layer in the first direction. By increasing the thickness of the insulating region, the breakdown voltage at the bottom of the Schottky diode structure is further improved, thereby increasing the reliability of the MOS device.

[0042] In some optional embodiments, the doped region has the second doping type, and the first implanted region has the first doping type.

[0043] Specifically, in an embodiment of the present application, if the first doping type is P-type, the second doping type is N-type, or the first doping type is N-type, the second doping type is P-type, wherein N-type doping is the addition of pentavalent elements into the semiconductor material, and the pentavalent elements include but are not limited to phosphorus, arsenic and antimony; P-type doping is the addition of trivalent elements into the semiconductor material, and the trivalent elements include but are not limited to boron, aluminum and gallium. The specific doping elements are not specifically limited in this application.

[0044] Furthermore, in the above-mentioned embodiment, the doping region and the second epitaxial layer have the same doping type, and the doping concentration of the doping region can be adjusted so that the Schottky diode structure has different breakdown voltages. Exemplarily, the second doping type is P-type, the first doping type is N-type, the doping concentration of the doping region is greater than the doping concentration of the second epitaxial layer, and the breakdown voltage of the Schottky diode structure is greater than the breakdown voltage of the MOS device. Another exemplary embodiment, the second doping type is P-type, the first doping type is N-type, the doping concentration of the doping region is less than the doping concentration of the second epitaxial layer, and the breakdown voltage of the Schottky diode structure is less than the breakdown voltage of the MOS device. Those skilled in the art can make adjustments according to product performance, and this is not specifically limited in this field.

[0045] In addition, the first implantation region and the second epitaxial layer have different doping types, which can reduce the number of ion implantation processes during the preparation of the device, simplify the preparation process, and reduce the preparation cost.

[0046] In some optional embodiments, the bottom surface of the Schottky diode structure and the bottom surface of the trench gate structure are located in the same surface.

[0047] Specifically, when the bottom surface of the Schottky diode structure and the trench gate structure have the same bottom surface, the trench gate structure and the Schottky diode structure can be formed in the same trench in terms of process, and the insulating region and the gate oxide layer are formed in the same process, which simplifies the preparation process and reduces the preparation cost. At the same time, the trench gate structure and the Schottky diode structure are formed in the same trench, so that the Schottky diode structure is integrated in the trench cell structure, which reduces the chip area and further reduces the manufacturing cost.

[0048] In some optional embodiments, such as Figure 1 As shown, the device further includes a second implantation region 50 , which is located in the second epitaxial layer 22 and contacts a surface of the trench gate structure 30 away from the Schottky diode structure 40 , and has a first doping type.

[0049] Specifically, the second injection region and the second epitaxial layer have different doping types, and the second injection region and the second epitaxial layer are both in contact with the gate oxide of the trench gate structure 30, that is, the second injection region, the second epitaxial layer and the trench gate structure 30 constitute a MOS structure, wherein, by controlling the magnitude of the voltage applied to the gate, a conductive channel is formed in the area where the second epitaxial layer contacts the gate oxide layer, thereby controlling the flow of electrons (or holes).

[0050] In some optional embodiments, the second implantation region has the same doping concentration as the first implantation region.

[0051] Specifically, the second injection region has the same doping type and the same doping concentration as the first injection region. In the preparation process, the same ion implantation process can be used to form the second injection region and the first injection region in the second epitaxial layer and the doping region, respectively, thereby reducing the number of multiple ion implantations in the preparation process of traditional trench MOS devices, simplifying the preparation process, and improving the reliability of MOS devices.

[0052] In some optional embodiments, such as Figure 1 As shown, the device further includes a plurality of conductive parts 60 , which are respectively in contact with the first implantation region 41 , the doping region 43 , the second implantation region 50 and the gate 31 , wherein isolation regions are provided between the plurality of conductive parts.

[0053] Specifically, the plurality of conductive portions 60 may include a first conductive portion 61, a second conductive portion 62, a third conductive portion 63 and a fourth conductive portion 64, wherein the first conductive portion 61 contacts the first injection region 41, and the second conductive portion 62 contacts the doping region 43, that is, the first conductive portion 61 and the second conductive portion 62 are respectively the positive and negative electrodes of the Schottky diode structure 40, and have the function of transmitting current. The third conductive portion 63 contacts the gate 31 to provide a gate voltage to the gate. The fourth conductive portion 64 contacts the second injection region 50 to serve as a source electrode of the MOS structure.

[0054] Among them, the doped region has a first length in the first direction, and the midline in the second direction where the point of 1 / 2 of the first length is located is the first midline, and the doped region is located on the side of the first midline away from the trench gate structure, so that a better conductive path can be formed between the first conductive part and the second conductive part of the formed Schottky diode structure to facilitate electrode prevention.

[0055] In some optional embodiments, such as Figure 1 As shown, the trench MOS device further includes a conductive layer 65 . The conductive layer 65 is located on a side of the substrate 10 away from the epitaxial layer 20 to serve as a drain electrode of the MOS structure.

[0056] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0057] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact, so as to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, and the material of the conductive layer is a Ni / Ti / Ni / Ag structure, wherein the first conductive part contacts the first injection region to form an ohmic contact, the second conductive part contacts the doped region to form an ohmic contact, the third conductive part contacts the gate to form an ohmic contact, the fourth conductive part 64 contacts the second injection region 50 to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0058] In some optional embodiments, such as Figure 1 As shown, the MOS device further includes an insulating portion 70 , which is located in the spacing region. The insulating portion 70 serves to isolate the plurality of conductive portions 60 .

[0059] Specifically, the material of the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0060] According to another aspect of the present application, a method for preparing a trench MOS device is provided, which is used to prepare any trench MOS device, such as Figure 2 As shown, the preparation method comprises:

[0061] Step S101: providing a substrate;

[0062] Step S102: forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer which are stacked, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, and the epitaxial layer having a first surface facing away from the substrate;

[0063] Step S103: forming at least one trench gate structure in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is respectively located on two surfaces of the gate that are opposite in a first direction and the gate oxide layer is located on a side of the gate close to the substrate, and the first direction is parallel to the first surface;

[0064] Step S104: forming a Schottky diode structure on one side of the trench gate structure, the Schottky diode structure comprising a first injection region, an insulating region and a doping region, the insulating region and the doping region being stacked, the insulating region being located on a side of the doping region close to the substrate, the insulating region and the doping region both being in contact with the trench gate structure, the first injection region being located in the doping region, and the first injection region and the doping region having different doping types.

[0065] By adopting the above-mentioned preparation method of the embodiment of the present application, on the basis of the traditional trench MOS device, multiple epitaxial processes are used to form the epitaxial layer and the doped region, and a first injection region of different doping types is formed in the doped region, that is, a Schottky diode structure is integrated in the MOS device, and the Schottky diode is located in the epitaxial layer on one side of the trench gate, so that the Schottky diode structure is integrated inside the device, that is, the parasitic diode outside the device is replaced by the Schottky diode structure inside the device, and the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode are improved, which can effectively improve the switching speed of the device and reduce the power consumption of the device, and enhance the performance reliability of the MOS device. In addition, the trench gate structure and the Schottky diode structure are formed in the same trench, that is, the integrated SBD structure is located in the trench cell structure, which reduces the chip area and reduces the manufacturing cost.

[0066] The following will describe in more detail the exemplary embodiments of the method for preparing the trench MOS device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0067] First, if Figure 3 As shown, step S101 is performed: providing a substrate 10 .

[0068] Specifically, the materials of the substrate 10 include silicon carbide, silicon, gallium nitride, gallium oxide, gallium arsenide, aluminum nitride and the like, and those skilled in the art can reasonably select them according to actual needs, and no specific limitation is made without application. The substrate has a first doping type.

[0069] Exemplarily, the substrate includes a doped SiC substrate to form an ohmic contact at the source, which can reduce the forward voltage drop of the diode structure and increase the breakdown voltage.

[0070] After providing the substrate, as Figure 4 As shown, step S102 is performed: an epitaxial layer 20 is formed on one side of the substrate.

[0071] Specifically, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 which are stacked. The first epitaxial layer 21 has a first doping type, and the second epitaxial layer 22 has a second doping type.

[0072] In other optional embodiments, the process of forming the first epitaxial layer 21 and the second epitaxial layer 22 includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0073] After forming the epitaxial layer, as Figures 5 to 7 As shown, step S103 is performed: forming a trench gate structure 30 .

[0074] Specifically, the steps of forming the trench gate structure may include: first, Figure 5 As shown, a first trench 81 is formed in the epitaxial layer 20 by an etching process, and the bottom surface of the first trench 81 exposes the first epitaxial layer 21; then, as shown in Figure 6 As shown in FIG. 1 , a first insulating layer 91 covering the sidewalls and the bottom surface is formed in the first trench 81, and the remaining area in the first trench 81 is the second trench 82; then, as shown in FIG. Figure 7As shown, a gate 31 and a second insulating layer 92 are formed on the sidewall of the second trench 82, wherein the first insulating layer 91 located on the side of the gate 31 close to the substrate 10, the first insulating layer 91 located on the side of the gate 31, and the second insulating layer 92 located on the other side of the gate 31 constitute the gate oxide layer 32. The insulating layer located at the bottom of the second trench 82 constitutes the insulating region 42, and the above-mentioned insulating layer may include only the first insulating layer, or may include the first insulating layer and the second insulating layer, which is not specifically limited in this application.

[0075] Among them, when the above-mentioned insulating layer only includes the first insulating layer, the thickness of the insulating region is less than or equal to the thickness of the first region in the gate oxide layer; when the above-mentioned insulating layer includes the first insulating layer and the second insulating layer, the thickness of the insulating region is greater than the thickness of the first region in the gate oxide layer.

[0076] In some specific embodiments, such as Figure 8 As shown, the steps of forming the trench gate structure may include:

[0077] Step S1031: Figure 8 As shown in (a), a first trench 81 is formed in the epitaxial layer 20 by an etching process, and the bottom surface of the first trench 81 exposes the first epitaxial layer 21, wherein: Figure 8 (a) with Figure 5 The same preparation steps;

[0078] Step S1032: Figure 8 As shown in (b), an insulating material is filled in the first trench 81 by a deposition process to form a first insulating region 911;

[0079] Step S1033: Figure 8 As shown in (c), a second trench 82 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region constitutes a first insulating layer 91, wherein: Figure 8 (c) with Figure 6 The same preparation steps;

[0080] Step S1034: Figure 8 As shown in (d), a deposition process is used to fill the second trench 82 with a gate material to form a gate material region 311;

[0081] Step S1035: Figure 8 As shown in (e), a fourth trench 84 is formed in the gate material region 311 by an etching process, and the remaining gate material constitutes the gate 31;

[0082] Step S1034: Figure 8 As shown in (f), an insulating material is filled in the fourth trench 84 by a deposition process to form a second insulating region 921;

[0083] Step S1036: Figure 8 As shown in (g), a trench is formed in the second insulating region 921 by an etching process, and the remaining second insulating region constitutes a second insulating layer 92, wherein: Figure 8 (g) with Figure 7 The preparation steps are the same.

[0084] Specifically, the above-mentioned etching process includes but is not limited to dry etching and wet etching, wherein dry etching includes physical etching, chemical etching and chemical-physical etching, and physical etching includes ion beam etching, plasma etching, reactive ion etching, etc. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0085] After the trench gate structure is formed, step S104 is performed: forming a Schottky diode structure.

[0086] Specifically, the steps of forming the Schottky diode structure include: first, Fig. 9 As shown in FIG. 8 , the remaining area in the second trench is the third trench 83, and the doped region 43 is formed in the third trench 83; then, as shown in FIG. Fig.10 As shown, the first implantation region 41 is formed in the doping region 43 by using an ion implantation process, wherein the doping region 43 and the first implantation region 41 have different doping types.

[0087] In the above preparation method, the Schottky diode structure and the trench gate structure are formed in the same first trench, that is, the integrated Schottky diode structure is located in the trench cell structure, which reduces the chip area and reduces the manufacturing cost.

[0088] The process of forming the doped region includes but is not limited to a deposition process and an epitaxial growth process.

[0089] In some optional embodiments, such as Fig.11 As shown, the preparation method further includes step S105: forming a second implantation region 50.

[0090] Specifically, the process of forming the second implantation region includes an ion implantation process.

[0091] In some optional embodiments, the second injection region has the same doping type and doping concentration as the first injection region, and the first injection region and the second injection region can be formed by the same ion implantation process, thereby reducing the number of ion implantation processes in traditional MOS devices and simplifying the preparation process.

[0092] In some optional implementations, the preparation method further includes step S106: forming a conductive portion.

[0093] Specifically, the steps of forming the conductive part include: first, Fig.12 As shown, in Fig.11 A dielectric material layer 71 is formed on the substrate as shown; then, Fig.13 As shown, a plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by an etching process, wherein the plurality of through holes include a first through hole 611, a second through hole 621, a third through hole 631 and a fourth through hole 641, the first through hole 611 exposes the first implantation region 41, the second through hole 621 exposes the doped region 43, the third through hole 631 exposes the gate 31, and the fourth through hole 641 exposes the second implantation region 50; then, as shown in Figure 1 As shown, a deposition process is used to form multiple conductive parts in multiple through holes, a first conductive part 61 is formed in the first through hole 611, a second conductive part 62 is formed in the second through hole 621, a third conductive part 63 is formed in the third through hole 631, and a fourth conductive part 64 is formed in the fourth through hole 641. The remaining dielectric material layer 71 constitutes the insulating part 70.

[0094] In the above embodiment, Figure 1 As shown, the preparation method further includes step S107: forming a conductive layer 65.

[0095] Specifically, a deposition process is used to deposit a conductive material on a side of the substrate 10 facing away from the epitaxial layer 20 to form the conductive layer 65 .

[0096] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0097] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact, so as to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, and the material of the conductive layer is a Ni / Ti / Ni / Ag structure, wherein the first conductive part contacts the first injection region to form an ohmic contact, the second conductive part contacts the doped region to form an ohmic contact, the third conductive part contacts the gate to form an ohmic contact, the fourth conductive part 64 contacts the second injection region 50 to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0098] Specifically, the material of the dielectric material or the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0099] The trench MOS device formed by the method for preparing the trench MOS device of the present application will be described below in conjunction with the embodiments.

[0100] The method for preparing a trench MOS device provided in this embodiment comprises the following steps:

[0101] Provide an N-type SiC substrate 10, such as Figure 3 As shown;

[0102] A first N-type epitaxial layer 21 and a second P-type epitaxial layer 22 are formed on an N-type SiC substrate 10 by using a double epitaxial growth process. The first N-type epitaxial layer 21 and the second P-type epitaxial layer 22 constitute an epitaxial layer 20. Figure 4 As shown;

[0103] A first trench 81 is formed in the epitaxial layer 20 by an etching process. Figure 8 (a) as shown;

[0104] The first trench 81 is filled with silicon oxide by a deposition process to form a first insulating region 911. Figure 8 (b) as shown;

[0105] The second trench 82 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region constitutes the first insulating layer 91. Figure 8 (c) as shown;

[0106] The second trench 82 is filled with polysilicon material by a deposition process to form a gate material region 311, such as Figure 8 (d) as shown;

[0107] A fourth trench 84 is formed in the gate material region 311 by an etching process, and the remaining gate material region constitutes the gate 31. Figure 8 (e) as shown;

[0108] The fourth trench 84 is filled with silicon oxide by a deposition process to form a second insulating region 921. Figure 8 (f) as shown;

[0109] The third trench 83 is formed in the second insulating region 921 by an etching process, and the remaining second insulating region constitutes the second insulating layer 92. Figure 8 (g) as shown;

[0110] The third trench 83 is filled with P-type SiC by an epitaxial growth process to form a doped region 43. Fig. 9 As shown;

[0111] An ion implantation process is used to simultaneously form an N-type second implantation region 50 and an N-type first implantation region 41 in the second epitaxial layer 22 and the doping region 43 near the trench gate structure, as shown in FIG. Fig.11 As shown;

[0112] The deposition process is used in Fig.11 A silicon oxide layer is formed on the substrate as shown to form a dielectric material layer 71, as shown in FIG. Fig.12 As shown;

[0113] A plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by etching process, wherein the plurality of through holes include a first through hole 611, a second through hole 621, a third through hole 631 and a fourth through hole 641, wherein the first through hole 611 exposes the first implantation region 41, the second through hole 621 exposes the doped region 43, the third through hole 631 exposes the gate 31, and the fourth through hole 641 exposes the second implantation region 50. Fig.13 As shown;

[0114] A deposition process is used to fill the plurality of through holes with Ni / Ti / TiN / Al material layers to form a plurality of conductive portions, wherein a first conductive portion 61 is formed in the first through hole 611, a second conductive portion 62 is formed in the second through hole 621, a third conductive portion 63 is formed in the third through hole 631, and a fourth conductive portion 64 is formed in the fourth through hole 641. Figure 1 As shown;

[0115] A conductive layer 65 of a Ni / Ti / Ni / Ag structure is formed on the side of the substrate 10 away from the epitaxial layer 20 by a deposition process. Figure 1 shown.

[0116] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0117] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A trench MOS device, characterized in that: include: substrate; An epitaxial layer, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer which are stacked, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, and the epitaxial layer having a first surface facing away from the substrate; at least one trench gate structure, the trench gate structure is located in the epitaxial layer, the surface of the trench gate structure facing away from the substrate is located in the first surface, the surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is respectively located on two surfaces of the gate that are opposite in a first direction and the gate oxide layer is located on a side of the gate close to the substrate, and the first direction is parallel to the first surface; A Schottky diode structure, wherein the Schottky diode structure is located on one side of the trench gate structure in the first direction, the Schottky diode structure comprises a first injection region, an insulating region and a doping region, the insulating region and the doping region are stacked, the insulating region is located on a side of the doping region close to the substrate, the insulating region and the doping region are both in contact with the trench gate structure, the first injection region is located in the doping region, and the first injection region and the doping region have different doping types.

2. The trench MOS device according to claim 1, characterized in that: The gate oxide layer includes a first region and a second region, the first region is located on a side of the gate away from the Schottky diode structure, the second region is located on a side of the gate close to the substrate, the first region has a first thickness in the first direction, the second region has a second thickness in the second direction, the first thickness is less than the second thickness, wherein the second direction is perpendicular to the first surface.

3. The trench MOS device according to claim 1, characterized in that: The doped region has the second doping type, and the first implanted region has the first doping type.

4. The trench MOS device according to claim 1, characterized in that: The bottom surface of the Schottky diode structure and the bottom surface of the trench gate structure are located in the same surface.

5. The trench MOS device according to claim 1, characterized in that: The device further comprises: A second implantation region, wherein the second implantation region is located in the second epitaxial layer and contacts a surface of the trench gate structure away from the Schottky diode structure, and the second implantation region has the first doping type.

6. The trench MOS device according to claim 5, characterized in that: The second implantation region has the same doping concentration as the first implantation region.

7. The trench MOS device according to claim 5, characterized in that: The device further includes: a plurality of conductive parts, wherein the plurality of conductive parts are respectively in contact with the first injection region, the doping region, the second injection region and the gate, wherein isolation regions are provided between the plurality of conductive parts.

8. A method for preparing a trench MOS device, characterized in that: Used to prepare the trench MOS device according to any one of claims 1 to 7, the preparation method comprising: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer which are stacked, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, and the epitaxial layer having a first surface facing away from the substrate; At least one trench gate structure is formed in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is respectively located on two surfaces of the gate that are opposite in a first direction and the gate oxide layer is located on a side of the gate close to the substrate, and the first direction is parallel to the first surface; A Schottky diode structure is formed on one side of the trench gate structure, and the Schottky diode structure includes a first injection region, an insulating region and a doping region, the insulating region and the doping region are stacked, the insulating region is located on a side of the doping region close to the substrate, the insulating region and the doping region are both in contact with the trench gate structure, the first injection region is located in the doping region, and the first injection region and the doping region have different doping types.

9. The preparation method according to claim 8, characterized in that: The step of forming the trench gate structure comprises: Forming a first trench in the epitaxial layer by an etching process, wherein a bottom surface of the first trench exposes the first epitaxial layer; forming a first insulating layer covering the sidewalls and the bottom surface in the first trench, and the remaining area in the first trench is a second trench; The gate and the second insulating layer are formed on the sidewalls of the second trench, wherein the first insulating layer located on the side of the gate close to the substrate, the first insulating layer located on the side of the gate, and the second insulating layer located on the other side of the gate constitute the gate oxide layer.

10. The preparation method according to claim 9, characterized in that: The remaining area in the second trench is a third trench, and the steps of forming the Schottky diode structure include: forming the doped region in the third trench; The first implantation region is formed in the doping region by using an ion implantation process, wherein the doping region and the first implantation region have different doping types.

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