HEMT device and preparation method thereof

Abstract

The invention provides an HEMT device and a preparation method thereof, the HEMT device comprises a semiconductor structure, a gate structure, a source electrode, a drain electrode, a strain compensation layer and a source field plate structure, the semiconductor structure comprises a substrate, a buffer layer, a channel layer and a barrier layer; the gate structure comprises a cap layer located on the upper surface of the barrier layer. The source electrode and the drain electrode are located on the opposite sides of the gate structure in the X direction and electrically connected with the barrier layer. The strain compensation layer comprises a first strain compensation layer and a second strain compensation layer, the first strain compensation layer is located on the upper surface of the barrier layer between the source and the gate structure and is adjacent to the gate structure, and the second strain compensation layer is located on the upper surface of the barrier layer between the drain and the gate structure and is spaced from the gate structure by a preset distance; the source field plate structure is electrically connected with the source electrode and comprises a first field plate, a second field plate and a third field plate which are arranged at intervals. Through the arrangement of the strain compensation layer and the source field plate structure, the on resistance of the device is reduced, and the voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a HEMT device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), as a typical representative of the third generation wide bandgap semiconductor materials, has the advantages of large bandgap width, high breakdown electric field, and high electron saturation drift velocity. As a typical representative of wide bandgap semiconductor power devices, gallium nitride high electron mobility transistor (HEMT) shows great potential in high-frequency, high-voltage, and high-power applications. For AlGaN / (Al)GaN high electron mobility transistor (HEMT) devices, on-resistance and breakdown voltage are their key performance parameters. Low on-resistance can increase the current output capacity of the device, with lower energy consumption and better transmission performance.

[0003] like Figure 1 and Figure 2 The diagrams are respectively a schematic diagram of a cross-sectional structure of a HEMT device and another schematic diagram of a cross-sectional structure of a HEMT device, including a semiconductor structure 01, a substrate 011, a buffer layer 012, a channel layer 013, a barrier layer 014, a gate structure 02, a cap layer 021, a gate 022, a source 03, a drain 04 and a passivation layer 05, wherein the source and the drain form an ohmic contact with the barrier layer, the gate and the barrier layer form a Schottky contact, or a PN junction is formed between the cap layer and the barrier layer. The purpose of the ohmic contact is to reduce the contact resistance, suppress the current collapse effect, and form a passivation layer above the barrier layer between the source and the drain. However, when the device is operating in the cut-off state, the electric field below the metal gate edge near the drain is relatively concentrated. When the electric field value exceeds the critical breakdown voltage of the material, the carriers in the channel are driven by the high electric field and are continuously accelerated and collision ionized. The current density below the edge of the metal gate continues to increase, and finally breaks down prematurely, resulting in a large gap between the breakdown voltage of the device and the theoretical limit value of the gallium nitride material. The on-resistance of the device is also relatively high, which in turn leads to higher energy consumption of the device.

[0004] Therefore, there is an urgent need to find a HEMT device that can increase the breakdown voltage of the device and reduce the on-resistance of the device. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a HEMT device and a method for preparing the same, so as to solve the problems of high on-resistance and low breakdown voltage of the HEMT device in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a HEMT device, comprising:

[0007] A semiconductor structure comprising a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence;

[0008] A gate structure, comprising a cap layer located on an upper surface of the barrier layer and electrically connected to the barrier layer;

[0009] A source electrode and a drain electrode, respectively located on the upper surface of the barrier layer at opposite sides of the gate structure along the X direction and both electrically connected to the barrier layer;

[0010] a strain compensation layer, comprising a first strain compensation layer and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is located on an upper surface of the barrier layer between the source electrode and the gate structure and is adjacent to a side wall of the gate structure, and the second strain compensation layer is located on an upper surface of the barrier layer between the drain electrode and the gate structure, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance;

[0011] A source field plate structure is electrically connected to the source electrode, and includes a first field plate, at least one second field plate and a third field plate which are sequentially arranged upwards and spaced apart from each other.

[0012] Optionally, the gate structure further includes a gate located on an upper surface of the cap layer and electrically connected to the cap layer.

[0013] Optionally, the first strain compensation layer includes aluminum elements and nitrogen elements, and the second strain compensation layer includes aluminum elements and nitrogen elements.

[0014] Optionally, the first strain compensation layer and the second strain compensation layer have the same thickness.

[0015] Optionally, at least two of the second strain compensation layers have different lengths along the X direction.

[0016] Optionally, projections of ends of the first field plate, the second field plate and the third field plate away from the source along the Y direction are all located between the gate structure and the drain, and the X direction is perpendicular to the Y direction.

[0017] Optionally, the projection of the end of the first field plate away from the source along the Y direction is located between the second strain compensation layer close to the gate structure and the gate structure, the projection of the end of the second field plate away from the source along the Y direction is located between two adjacent second strain compensation layers, and the projection of the end of the third field plate away from the source along the Y direction is located between the second strain compensation layer close to the drain and the drain.

[0018] Optionally, no less than three second strain compensation layers are provided between the gate structure and the drain, and an end of the second field plate away from one end of the source corresponds to the top of the gap between two adjacent second strain compensation layers, and in the direction away from the Y direction, the lengths of the second field plates stacked in sequence at intervals in the X direction gradually increase.

[0019] Optionally, the first field plate, the second field plate and the third field plate have the same thickness.

[0020] The present invention also provides a method for preparing a HEMT device, comprising the following steps:

[0021] A semiconductor structure is provided, comprising a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence;

[0022] forming a gate structure including a cap layer, wherein the cap layer is located on the upper surface of the barrier layer and is electrically connected to the barrier layer, and forming a strain compensation material layer covering the exposed surface of the barrier layer;

[0023] Etching the strain compensation material layer to obtain a strain compensation layer, wherein the strain compensation layer includes a first strain compensation layer located at an opposite side of the gate structure along the X direction and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is adjacent to the gate structure, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance;

[0024] forming a source electrode electrically connected to the barrier layer on a side of the first strain compensation layer away from the gate structure, and forming a drain electrode electrically connected to the barrier layer on a side of the second strain compensation layer away from the gate structure;

[0025] A source field plate structure electrically connected to the source electrode is formed, wherein the source field plate structure comprises a first field plate, at least one second field plate and a third field plate which are sequentially arranged upwards and spaced apart from each other.

[0026] As described above, the HEMT device and the preparation method thereof of the present invention are provided by arranging the strain compensation layer on the upper surface of the barrier layer between the gate structure and the source and between the gate structure and the drain, wherein the strain compensation layer includes the first strain compensation layer and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is located between the gate structure and the source and is adjacent to the gate structure, and the second strain compensation layer is located between the gate structure and the drain, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance, thereby improving the two-dimensional electron gas density of the channel region of the gate structure close to the source side and below the second strain compensation layer, and then The on-resistance of the device is reduced; by setting the source field plate structure electrically connected to the source, and the projections of the endpoints of the first field plate, the second field plate and the third field plate in the source field plate structure away from the source along the Y direction are respectively located between the gate structure and the second strain compensation layer close to the gate structure, between two adjacent second strain compensation layers, and between the drain and the second strain compensation layer close to the drain, the peak values ​​of the channel electric field on the side of the gate structure close to the drain, between two adjacent second strain compensation layers, and on the side of the drain close to the gate structure are reduced, thereby optimizing the electric field in the channel of the device, improving the breakdown voltage of the device, and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a HEMT device.

[0028] Figure 2 Shown is a schematic diagram of the cross-sectional structure of another HEMT device.

[0029] Figure 3 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention.

[0030] Figure 4 Display as Figure 3 A two-dimensional electrical density variation diagram of the channel region between the second strain compensation layer close to the gate structure and the second strain compensation layer close to the drain of the HEMT device.

[0031] Figure 5 The process flow chart of the HEMT device manufacturing method of the present invention is shown.

[0032] Figure 6 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming the gate structure.

[0033] Figure 7 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming a strain compensation material layer.

[0034] Figure 8 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming a strained material layer.

[0035] Fig. 9 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after the first passivation layer is formed.

[0036] Fig.10 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming the contact hole.

[0037] Fig.11 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming the source and drain.

[0038] Fig.12 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming the first field plate.

[0039] Fig.13 It is a schematic diagram showing the cross-sectional structure of the HEMT device of the present invention after forming the second field plate.

[0040] Description of Figure Numbers

[0041] 01 Semiconductor Structure

[0042] 011 Substrate

[0043] 012 Buffer layer

[0044] 013 Channel layer

[0045] 014 Barrier layer

[0046] 02 Gate structure

[0047] 021 Cap layer

[0048] 022 Gate

[0049] 03 Source

[0050] 04 Drain

[0051] 05 Passivation layer

[0052] 1 Semiconductor structure

[0053] 11 Substrate

[0054] 12 Buffer layer

[0055] 13 Channel layer

[0056] 14 Barrier layer

[0057] 2 Gate structure

[0058] 21 Cap layer

[0059] 22 Gate

[0060] 3 Source

[0061] 4 Drain

[0062] 5 Strain compensation layer

[0063] 50 layers of strain compensation material

[0064] 51 First strain compensation layer

[0065] 52 Second strain compensation layer

[0066] 6 Source field plate structure

[0067] 61 First Board

[0068] 62 Second Board

[0069] 63 Third Board

[0070] 7 Passivation layer

[0071] 7a First passivation layer

[0072] 7b Second passivation layer

[0073] 7c Third passivation layer

[0074] 7d Fourth passivation layer

[0075] 71 Contact hole

[0076] 72 First through hole

[0077] 73 Second through hole

[0078] 74 Third through hole DETAILED DESCRIPTION

[0079] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] See also Figures 3 to 13It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0081] Embodiment 1

[0082] This embodiment provides a HEMT device, such as Figure 3 , which is a schematic diagram of the cross-sectional structure of the HEMT device, including a semiconductor structure 1, a gate structure 2, a source 3, a drain 4, a strain compensation layer 5 and a source field plate structure 6, wherein the semiconductor structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13 and a barrier layer 14 stacked in sequence; the gate structure 2 includes a cap layer 21 located on the upper surface of the barrier layer 14 and electrically connected to the barrier layer 14, the source 3 and the drain 4 are respectively located on the upper surface of the barrier layer 14 on the opposite side of the gate structure 2 along the X direction and are both electrically connected to the barrier layer 14; the strain compensation layer 5 includes a first strain compensation layer 51 and a plurality of second strain compensation layers 52 arranged at intervals, the first strain compensation layer 51 is located on the upper surface of the barrier layer 14 between the source 3 and the gate structure 2 and is adjacent to the gate structure 2, the second strain compensation layer 52 is located on the upper surface of the barrier layer 14 between the drain 4 and the gate structure 2, and the second strain compensation layer 52 close to the gate structure 2 is spaced apart from the gate structure 2 by a preset distance; the source field plate structure 6 is electrically connected to the source 3, and the source field plate structure 6 includes a first field plate 61, at least one second field plate 62 and a third field plate 63 which are arranged in sequence upward at intervals.

[0083] Specifically, the material of the substrate 11 includes sapphire, SiC, Si, GaN, diamond, Al2O3 or other suitable materials.

[0084] Specifically, while ensuring device performance, the shape, size and thickness of the substrate 11 can be selected according to actual conditions and are not limited here.

[0085] Specifically, the material of the buffer layer 12 includes AlN, AlGaN, GaN, InN or other suitable semiconductor layer materials.

[0086] Specifically, the buffer layer 12 can be a single-layer structure or a composite layer structure, and when the buffer layer 12 is a single-layer structure, the size and thickness of the buffer layer 12 can be set according to actual conditions while ensuring device performance, and are no longer restricted here; when the buffer layer 12 is a composite layer, the size and thickness of each film layer in the buffer layer 12 can be set according to actual conditions while ensuring device performance, and are no longer restricted here.

[0087] Specifically, the material of the channel layer 13 includes a nitride-based semiconductor or other suitable semiconductor materials, such as nitride and III-V group compounds (such as GaN, Al x Ga 1-x N、In x Ga 1-x N, etc.).

[0088] Specifically, while ensuring device performance, the shape, size and thickness of the channel layer 13 can be selected according to actual conditions and are not limited here.

[0089] Specifically, the material of the barrier layer 14 includes a nitride-based semiconductor or other suitable semiconductor materials, such as nitride and III-V compound (such as In x Al y Ga 1-x-y N、In x Al 1-x N、Al x Ga 1-x N、In x Ga 1-x N, AlN, etc.

[0090] Specifically, under the condition of ensuring the device performance, the thickness of the barrier layer 14 can be selected according to actual conditions and is not limited here.

[0091] Specifically, due to the difference in material properties between the channel layer 13 and the barrier layer 14, a polarization effect is generated at the interface between the channel layer 13 and the barrier layer 14, and then a two-dimensional electron gas (2DEG) is generated, that is, electrons gather in a narrow and deep quantum well at the interface between the channel layer 13 and the barrier layer 14.

[0092] Specifically, the cap layer 21 is used to deplete the two-dimensional electron gas density generated at the interface between the barrier layer 14 and the channel layer 13 below the cap layer 21. The material of the cap layer 21 includes a P-type doped III-V compound semiconductor material or other suitable semiconductor materials. In this embodiment, a P-type GaN layer is used as the cap layer 21.

[0093] Specifically, a PN junction is formed between the cap layer 21 and the barrier layer 14 , and the direction of the built-in electric field of the PN junction between the cap layer 21 and the barrier layer 14 points from the barrier layer 14 to the cap layer 21 .

[0094] Specifically, while ensuring device performance and depletion of the two-dimensional electron gas density in the channel region below the cap layer 21, the shape, size, thickness and doping concentration of the cap layer 21 can be selected according to actual conditions and are not limited here.

[0095] As an example, the gate structure 2 further includes a gate 22 located on the upper surface of the cap layer 21 and electrically connected to the cap layer 21 .

[0096] Specifically, the gate 22 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0097] As an example, the first strain compensation layer 51 includes aluminum, nitrogen or other suitable elements. For example, the first strain compensation layer 51 may be an AlN layer containing only aluminum and nitrogen.

[0098] Specifically, the first strain compensation layer 51 is used to adjust the density of the two-dimensional electron gas layer below the first strain compensation layer 51 , thereby increasing the two-dimensional electron gas density in the channel region of the gate structure 2 close to the source 3 side.

[0099] Specifically, under the condition of ensuring the performance of the device, the size of the first strain compensation layer 51 can be selected according to actual conditions and is not limited here.

[0100] Specifically, the thickness of the first strain compensation layer 51 is not greater than the thickness of the cap layer 21. While ensuring device performance and the thickness of the first strain compensation layer 51 is less than the thickness of the cap layer 21, the thickness of the first strain compensation layer 51 can be selected according to actual conditions and is no longer limited here.

[0101] As an example, the second strain compensation layer 52 includes aluminum, nitrogen or other suitable elements. In this embodiment, the first strain compensation layer 51 and the second strain compensation layer 52 are made of the same material, that is, the element type in the first strain compensation layer 51 is the same as the element type in the second strain compensation layer 52, and the proportion of each element is the same.

[0102] Specifically, the number of the second strain compensation layers 52 between the gate structure 2 and the drain electrode 4 is not less than 2. In this embodiment, two second strain compensation layers 52 are disposed between the gate structure 2 and the drain electrode 4.

[0103] As an example, the first strain compensation layer 51 and the second strain compensation layer 52 have the same thickness.

[0104] Specifically, the second strain compensation layer 52 is used to regulate the two-dimensional electron gas density in the channel region below the second strain compensation layer 52 to increase the two-dimensional electron gas density in the channel region below the second strain compensation layer 52, and then increase the two-dimensional electron gas density in the channel region of the drain 4 close to the gate structure 2 side.

[0105] Specifically, under the condition of ensuring device performance, the length of the second strain compensation layer 52 between the gate structure 2 and the drain 4 can be selected according to actual conditions and is not limited here.

[0106] As an example, the lengths of at least two of the second strain-compensating layers 52 along the X direction are different.

[0107] Specifically, under the condition of ensuring device performance, the lengths of the second strain compensation layers 52 between the gate structure 2 and the drain 4 along the X direction may also be the same. In this embodiment, the lengths of the two second strain compensation layers 52 along the X direction are the same.

[0108] Specifically, while ensuring device performance, the distance between two adjacent second strain compensation layers 52 can be selected according to actual conditions and is no longer restricted here; the distance between the second strain compensation layer 52 close to the gate structure 2 and the gate structure 2 can be selected according to actual conditions and is no longer restricted here.

[0109] Specifically, under the condition of ensuring device performance, the second strain compensation layer 52 close to the drain 4 may be adjacent to the drain 4 or spaced apart from the drain 4. In this embodiment, the second strain compensation layer 52 close to the drain 4 is spaced apart from the drain 4.

[0110] Specifically, the material of the source electrode 3 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the drain electrode 4 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0111] Specifically, while ensuring device performance, the distance between the source 3 and the gate structure 2 can be selected according to actual conditions and is not limited here; the distance between the drain 4 and the gate structure 2 can be selected according to actual conditions and is not limited here.

[0112] Specifically, the source field plate structure 6 is used to reduce the peak value of the electric field in the channel region between the gate structure 2 and the drain 4 , and optimize the electric field distribution in the channel region.

[0113] As an example, the projections of the ends of the first field plate 61 , the second field plate 62 and the third field plate 63 away from the source 3 along the Y direction are all located between the gate structure 2 and the drain 4 , and the X direction is perpendicular to the Y direction.

[0114] As an example, the projection of the end of the first field plate 61 away from the source 3 along the Y direction is located between the second strain compensation layer 52 close to the gate structure 2 and the gate structure 2, the projection of the end of the second field plate 62 away from the source 3 along the Y direction is located between two adjacent second strain compensation layers 52, and the projection of the end of the third field plate 63 away from the source 3 along the Y direction is located between the second strain compensation layer 52 close to the drain 4 and the drain 4.

[0115] As an example, the first field plate 61 , the second field plate 62 , and the third field plate 63 have the same thickness.

[0116] Specifically, while ensuring device performance, the thicknesses of the first field plate 61, the second field plate 62, and the third field plate 63 in the source field plate structure 6 may be different or not completely the same. For example, the thicknesses of the first field plate 61, the second field plate 62, and the third field plate 63 may be different. The first field plate 61 and the second field plate 62 may have the same thickness, while the second field plate 62 and the third field plate 63 may have different thicknesses. The first field plate 61 and the third field plate 63 may have the same thickness, while the first field plate 61 and the second field plate 62 may have different thicknesses. The second field plate 62 and the third field plate 63 may have the same thickness, while the first field plate 61 and the second field plate 62 may have different thicknesses.

[0117] As an example, no less than three second strain compensation layers 52 are provided between the gate structure 2 and the drain 4, and above the gap between two adjacent second strain compensation layers 52 corresponds to an end of the second field plate 62 away from one end of the source 3, and in the direction away from the Y direction, the lengths of the second field plates 52 stacked in sequence increase gradually in the X direction, that is, when no less than three second strain compensation layers 52 are provided between the gate structure 2 and the drain 4, the number of gaps between two adjacent second strain compensation layers 52 is the same as the number of the second field plates 62 stacked in sequence upward, and the lengths of the second field plates 62 stacked in sequence upward gradually increase.

[0118] Specifically, when no less than three second strain compensation layers 52 are provided between the gate structure 2 and the drain 4 , the number of the second field plates 62 may be less than the number of gaps between two adjacent second strain compensation layers 52 while ensuring device performance.

[0119] Specifically, the source field plate structure 6 is provided with a plurality of second field plates 62. While ensuring device performance, the thicknesses of different second field plates 62 can be the same or different, and the distance between two adjacent second field plates 62 can be the same or different; the thicknesses of the first field plate 61, the second field plate 62 and the third field plate 63 can be the same or different.

[0120] Specifically, while ensuring device performance, the distances between the lower surface of the first field plate 61 and the upper surface of the gate structure 2, the upper surface of the first field plate 61 and the lower surface of the second field plate 62, and the upper surface of the second field plate 62 and the lower surface of the third field plate 63 may be the same or different.

[0121] Specifically, the source field plate structure 6 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0122] Specifically, the device is further provided with a passivation layer 7 for suppressing the current collapse effect of the device, and the passivation layer 7 includes a first passivation layer 7a, a second passivation layer 7b, a third passivation layer 7c and a fourth passivation layer 7d, wherein the first passivation layer 7a covers the barrier layer 14, the gate structure 2, and the exposed surface of the strain compensation layer 5, and the first passivation layer 7a is provided with a contact hole 71 penetrating the first passivation layer 7a and exposing the barrier layer 14, and the source 3 and the drain 4 respectively fill the contact hole 71, and the second passivation layer 7b covers the upper surface of the first passivation layer 7a and the exposed surface of the source 3, and the second passivation layer 7b is provided with a first through hole 72 penetrating the second passivation layer 7b and exposing the source 3, and the first field plate 61 is located at The third passivation layer 7c covers the upper surface of the second passivation layer 7b and the exposed surface of the first field plate 61. The third passivation layer 7c is provided with a second through hole 73 penetrating the third passivation layer 7c and exposing the first field plate 61. The second field plate 62 is located on the upper surface of the third passivation layer 7c and fills the second through hole 73. The fourth passivation layer 7d covers the upper surface of the third passivation layer 7c and the exposed surface of the second field plate 62. The fourth passivation layer 7d is provided with a third through hole 74 penetrating the third passivation layer 7c and exposing the second field plate 62. The third field plate 63 is located on the upper surface of the fourth passivation layer 7d and fills the third through hole 74.

[0123] Specifically, when a plurality of second field plates 62 are provided in the device, the third passivation layer 7c is also correspondingly provided with the third passivation layer 7c and the second through holes 73 having the same number as the second field plates 62, and the third passivation layer 7c and the second field plates 62 are alternately stacked in sequence along a direction away from the Y direction, each second field plate 62 fills the corresponding second through hole 73, the third passivation layer 7c located above each second field plate 62 in the third passivation layer 7c covers the exposed surface of the second field plate 62, the third passivation layer 7c located at the bottom layer covers the exposed surface of the second passivation layer 7b and the first field plate 61, and the fourth passivation layer 7d covers the second field plate 62 located at the top layer and the exposed surface of the third passivation layer 7c located at the top layer.

[0124] Specifically, the material of the first passivation layer 7a includes silicon oxide, silicon nitride or other suitable dielectric materials; the material of the second passivation layer 7b includes silicon oxide, silicon nitride or other suitable dielectric materials; the material of the third passivation layer 7c includes silicon oxide, silicon nitride or other suitable dielectric materials; the material of the fourth passivation layer 7d includes silicon oxide, silicon nitride or other suitable dielectric materials.

[0125] Specifically, while ensuring device performance, the thickness of the first passivation layer 7a can be selected according to actual conditions and is no longer restricted here; the thickness of the second passivation layer 7b can be selected according to actual conditions and is no longer restricted here; the thickness of the third passivation layer 7c can be selected according to actual conditions and is no longer restricted here; the thickness of the fourth passivation layer 7d can be selected according to actual conditions and is no longer restricted here.

[0126] Specifically, Figure 4 As shown, Figure 3 A diagram of the change in the two-dimensional electron gas density in the channel region between the second strain compensation layer 52 near the gate structure 2 and the second strain compensation layer 52 near the drain 4 of the HEMT device, wherein region A refers to the channel region below the second strain compensation layer 52 near the gate structure 2, region B refers to the channel region below the gap between two adjacent second strain compensation layers 52, and region C refers to the channel region below the second strain compensation layer 52 near the drain 4. It can be seen from the figure that the two-dimensional electron density in the channel region below the second strain compensation layer 52 is significantly higher than the two-dimensional electron gas density in the channel region below the gap between two adjacent second strain compensation layers 52, that is, the two-dimensional electron gas density in the region where the second strain compensation layer 52 is provided is greater than the two-dimensional electron gas density in the region where the second strain compensation layer 52 is not provided.

[0127] Specifically, since the two-dimensional electron gas density of the gate structure 2 near the drain 4 side in the HEMT device is relatively high, the two-dimensional electron gas density of the channel region of the gate structure 2 near the source 3 side is improved by setting the first strain compensation layer 51, and a plurality of second strain compensation layers 52 arranged at intervals are set between the gate structure 2 and the drain 4 to improve the two-dimensional electron gas density in the channel region below the second strain compensation layer 52 between the gate structure 2 and the drain 4, thereby improving the migration speed of the two-dimensional electron gas in the device and reducing the on-resistance of the device.

[0128] Specifically, by providing the source field plate structure 6 electrically connected to the source electrode 3, and the projection of the end of the first field plate 61 in the source field plate structure 6 away from the source electrode 3 along the Y direction is located between the gate structure 2 and the second strain compensation layer 52 close to the gate structure 2, the electric field strength of the gate structure 2 close to the drain electrode 4 is effectively reduced, and the electric field peak of the gate structure 2 close to the drain electrode 4 is reduced, and the projection of the end of the second field plate 62 away from the source electrode 3 along the Y direction is located between two adjacent second strain compensation layers. The source field plate structure 6 is disposed between the gate structure 2 and the drain 4, so that the electric field peak value of the channel region below the mutually adjacent edges of two adjacent second strain compensation layers 52 can be reduced. The projection of the end of the third field plate 63 away from the source 3 along the Y direction is located between the second strain compensation layer 52 close to the drain 4 and the drain 4, so that the electric field peak value of the channel region at the edge of the second strain compensation layer 52 close to the drain 4 can be reduced. That is, the arrangement of the source field plate structure 6 can optimize the channel electric field distribution between the gate structure 2 and the drain 4, thereby improving the breakdown voltage of the device.

[0129] Specifically, due to the arrangement of the strain compensation layer 5 and the source field plate structure 6 , the current collapse effect of the device and the hot electron effect at the drain 4 are alleviated, thereby improving the performance of the device.

[0130] The HEMT device of this embodiment is provided with the first strain compensation layer 51 on the upper surface of the barrier layer 14 between the gate structure 2 and the source 3 to improve the two-dimensional electron gas density of the channel region of the gate structure 2 close to the source 3 side, and a plurality of second strain compensation layers 52 spaced apart from the gate structure 2 are provided between the gate structure 2 and the drain 4 to improve the two-dimensional electron gas density of the channel region below the second strain compensation layers 52 between the gate structure 2 and the drain 4, while the two-dimensional electron gas density of the channel region below the gate structure 2 close to the drain 4 side remains unchanged, thereby making the channel region below the gate structure 2 close to the drain 4 side and the channel region below the drain 4 have different two-dimensional electron gas densities, thereby improving the migration speed of the two-dimensional electron gas and reducing the on-resistance of the device; The source field plate structure 6 electrically connected to the source electrode 3 is provided, and the projection of the end of the first field plate 61 in the source field plate structure 6 away from the source electrode 3 along the Y direction is located between the gate structure 2 and the second strain compensation layer 52 close to the gate structure 2, the projection of the end of the second field plate 62 away from the source electrode 3 along the Y direction is located between two adjacent second strain compensation layers 52, and the projection of the end of the third field plate 63 away from the source electrode 3 along the Y direction is located between the drain electrode 4 and the second strain compensation layer 52 close to the drain electrode 4, thereby reducing the electric field peak value of the channel region of the gate structure 2 close to the drain electrode 4, between two adjacent second strain compensation layers 52, and the drain electrode 4 close to the gate structure 2, thereby optimizing the electric field distribution in the channel of the device and improving the breakdown voltage of the device.

[0131] Embodiment 2

[0132] This embodiment provides a method for preparing a HEMT device, such as Figure 5 FIG. 1 is a process flow chart of the method for preparing the HEMT device, comprising the following steps:

[0133] S1: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence;

[0134] S2: forming a gate structure including a cap layer, wherein the cap layer is located on the upper surface of the barrier layer and is electrically connected to the barrier layer, and forming a strain compensation material layer covering the exposed surface of the barrier layer;

[0135] S3: etching the strain compensation material layer to obtain a strain compensation layer, wherein the strain compensation layer includes a first strain compensation layer located at an opposite side of the gate structure along the X direction and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is adjacent to the gate structure, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance;

[0136] S4: forming a source electrode electrically connected to the barrier layer on a side of the first strain compensation layer away from the gate structure, and forming a drain electrode electrically connected to the barrier layer on a side of the second strain compensation layer away from the gate structure;

[0137] S5: forming a source field plate structure electrically connected to the source electrode, wherein the source field plate structure comprises a first field plate, at least one second field plate and a third field plate which are sequentially arranged upwards and spaced apart from each other.

[0138] See also Figure 6 to Figure 7 , perform step S1 and step S2: provide a semiconductor structure 1, the semiconductor structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13 and a barrier layer 14 stacked in sequence; form a gate structure 2 including a cap layer 21, the cap layer 21 is located on the upper surface of the barrier layer 14 and is electrically connected to the barrier layer 14, and form a strain compensation material layer 50 covering the exposed surface of the barrier layer 14.

[0139] Specifically, the substrate 11 in the semiconductor structure 1 is used to provide a process platform for forming a device, the buffer layer 12 is used to reduce the lattice mismatch and thermal mismatch between the material of the substrate 11 and the material of the channel layer 13 to improve the quality of the formed channel layer 13, and a quantum well is formed at the interface between the barrier layer 14 and the channel layer 13, and then a two-dimensional electron gas is generated at the interface between the barrier layer 14 and the channel layer 13.

[0140] Specifically, Figure 6 , which is a schematic diagram of a cross-sectional structure after the gate structure 2 is formed, and the gate structure 2 further includes a gate 22 located on the upper surface of the cap layer 21 and electrically connected to the cap layer 21 .

[0141] Specifically, forming the gate structure 2 includes the following steps: forming a cap material layer and a gate material layer stacked in sequence on the upper surface of the barrier layer 14; forming a patterned photoresist layer on the upper surface of the gate material layer, and etching the gate material layer and the cap material layer in sequence based on the patterned photoresist layer to obtain the gate structure 2.

[0142] Specifically, the method of forming the cap material layer includes physical vapor deposition, chemical vapor deposition or other suitable methods; the method of forming the gate material layer includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0143] Specifically, under the condition of ensuring the performance of the device, the thickness of the cap material layer can be selected according to actual conditions and is not limited here.

[0144] Specifically, the method of forming the photoresist layer and patterning the photoresist layer is a commonly used photoresist manufacturing and developing method, which will not be described in detail here.

[0145] Specifically, the method of etching the gate material layer includes dry etching, wet etching or other suitable methods; the method of etching the cap material layer includes dry etching, wet etching or other suitable methods.

[0146] Specifically, after forming the gate structure 2 and before forming the strain compensation material layer 50 , the method further includes a step of removing the photoresist layer.

[0147] Specifically, the method for removing the photoresist layer is a commonly used photoresist removal method, which will not be described in detail here.

[0148] Specifically, Figure 7 , which is a schematic diagram of a cross-sectional structure after forming the strain compensation material layer 50 , the method of forming the strain compensation material layer 50 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0149] Please see again Figures 8 to 13 , performing the step S3, the step S4 and the step S5: etching the strain compensation material layer 50 to obtain a strain compensation layer 5, the strain compensation layer 5 comprising a first strain compensation layer 51 located at the opposite side of the gate structure 2 along the X direction and a plurality of second strain compensation layers 52 arranged at intervals, the first strain compensation layer 51 being adjacent to the gate structure 2, and the second strain compensation layer 52 close to the gate structure 2 being spaced apart from the gate structure 2 by a preset distance; forming a source electrode 3 electrically connected to the barrier layer 14 on a side of the first strain compensation layer 51 away from the gate structure 2, and forming a drain electrode 4 electrically connected to the barrier layer 14 on a side of the second strain compensation layer 52 away from the gate structure 2; forming a source field plate structure 6 electrically connected to the source electrode 3, the source field plate structure 6 comprising a first field plate 61, at least one second field plate 62 and a third field plate 63 arranged in sequence upward at intervals.

[0150] Specifically, the method of etching the strain compensation material layer 50 includes dry etching, wet etching or other suitable methods.

[0151] Specifically, Figure 8 , which is a schematic diagram of the cross-sectional structure after the strain compensation layer 5 is formed. Under the condition of ensuring the device performance, the side of the first strain compensation layer 51 away from the gate structure 2 can be adjacent to the source 3 .

[0152] Specifically, the thickness of the first strain compensation layer 51 formed is smaller than the thickness of the cap layer 21 ; the thickness of the second strain compensation layer 52 formed is smaller than the thickness of the cap layer 21 .

[0153] Specifically, Fig. 9 As shown, it is a schematic diagram of the cross-sectional structure after the first passivation layer 7a is formed. After the strain compensation layer 5 is formed and before the source 3 and the drain 4 are formed, it also includes the step of forming the first passivation layer 7a covering the strain compensation layer 5, the barrier layer 14 and the exposed surface of the gate structure 2.

[0154] Specifically, the method of forming the first passivation layer 7a includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0155] Specifically, the material of the first passivation layer 7a includes silicon oxide, silicon nitride or other suitable dielectric materials.

[0156] Specifically, Fig.10 , which is a schematic diagram of the cross-sectional structure after the contact hole 71 is formed. After the first passivation layer 7a is formed and before the source 3 and the drain 4 are formed, the step of forming the contact hole 71 penetrating the first passivation layer 7a and exposing the barrier layer 14 is also included.

[0157] Specifically, the method of forming the contact hole 71 includes dry etching, wet etching or other suitable methods.

[0158] Specifically, under the condition of ensuring the device performance, the opening size of the contact hole 71 can be selected according to actual conditions and is not limited here.

[0159] Specifically, Fig.11 , which is a schematic diagram of the cross-sectional structure after the source electrode 3 and the drain electrode 4 are formed, wherein the source electrode 3 and the drain electrode 4 are respectively filled with different contact holes 71 .

[0160] Specifically, the method for forming the source 3 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the drain 4 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0161] Specifically, Fig.12 and Fig.13, which are schematic diagrams of the cross-sectional structure after the first field plate 61 is formed and schematic diagrams of the cross-sectional structure after the second field plate 62 is formed, respectively. The formation of the source field plate structure 6 includes the following steps: forming a second passivation layer 7b covering the first passivation layer 7a, the source 3 and the upper surface of the drain 4, and forming a first through hole 72 penetrating the second passivation layer 7b and exposing the upper surface of the source 3 in the second passivation layer 7b; forming a first field plate 61 located on the upper surface of the second passivation layer 7b and filling the first through hole 72, and an end of the first field plate 61 away from one end of the source 3 is located directly above the gap between the gate structure 2 and the second strain compensation layer 52 close to the gate structure 2; forming a third passivation layer 7c covering the exposed surface of the first field plate 61 and the upper surface of the second passivation layer 7b, and forming a second through hole 73 penetrating the third passivation layer 7c and exposing the first field plate 61 in the third passivation layer 7c; forming a first through hole 73 located on the third passivation layer 7c and filling the first through hole 72; a second field plate 62 is formed on the upper surface of the passivation layer 7c and fills the second through hole 73, and the end of the second field plate 62 away from the source 3 is located directly above the gap between two adjacent second strain compensation layers 52; a fourth passivation layer 7d is formed to cover the exposed surface of the second field plate 62 and the upper surface of the third passivation layer 7c, and a third through hole 74 is formed in the fourth passivation layer 7d to penetrate the fourth passivation layer 7d and expose the second field plate 62; a second field plate 63 is formed on the upper surface of the fourth passivation layer 7d and fills the third through hole 74, and the end of the third field plate 63 away from the source 3 is located directly above the gap between the drain 4 and the second strain compensation layer 52 close to the drain 4, the first field plate 61, the second field plate 62 and the third field plate 63 constitute the source field plate structure 6, and the first passivation layer 7a, the second passivation layer 7b, the third passivation layer 7c and the fourth passivation layer 7d constitute the passivation layer 7.

[0162] Specifically, when a plurality of the second field plates 62 are formed in the device, the third passivation layer 7c also includes the same number of the third passivation layers 7c and the second through holes 73 as the second field plates 62, and the third passivation layer 7c and the second field plates 62 are overlapped in sequence along a direction away from the Y direction, and the corresponding second through holes 73 are formed before the second field plates 62 are formed, and the bottom surface of each of the second through holes 73 exposes the field plate covered by the third passivation layer 73.

[0163] Specifically, the method for forming the second passivation layer 7b includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method for forming the third passivation layer 7c includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method for forming the fourth passivation layer 7d includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0164] Specifically, the method for forming the first through hole 72 includes dry etching, wet etching or other suitable methods; the method for forming the second through hole 73 includes dry etching, wet etching or other suitable methods; the method for forming the third through hole 74 includes dry etching, wet etching or other suitable methods.

[0165] Specifically, the method for forming the first field plate 61 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the second field plate 62 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the third field plate 63 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0166] Specifically, by forming the first strain compensation layer 51 between the gate structure 2 and the source 3, and forming a plurality of second strain compensation layers 52 spaced apart between the gate structure 2 and the drain 4, and the second strain compensation layers 52 are spaced apart from the gate structure 2, the two-dimensional electron gas density in the channel region of the gate structure 2 close to the source 3 and below the second strain compensation layer 52 is improved, and then the two-dimensional electron gas density in the channel region of the gate structure 2 close to the drain 4 is different from the two-dimensional electron gas density in the channel region below the second strain compensation layer 52, thereby reducing the on-resistance of the device.

[0167] Specifically, by forming the source field plate structure 6 electrically connected to the source 3, and utilizing the arrangement of the end points of the first field plate 61, the second field plate 62, and the third field plate 63 away from the source 3, the electric field peaks in the channel regions of the gate structure 2 close to the drain 4, between two adjacent second strain compensation layers 52, and the drain 4 close to the second strain compensation layer 52 are reduced, thereby optimizing the channel electric field of the device and thereby improving the breakdown resistance of the device.

[0168] The method for preparing the HEMT device of the present embodiment reduces the on-resistance of the device while improving the breakdown resistance of the device by forming the strain compensation layer 5 located on the upper surface of the barrier layer 14 and the source field plate structure 6 electrically connected to the source 3, and selecting the positions of the first field plate 61, the second field plate 62 and the third field plate 63 in the source field plate structure 6 away from the end points of the source 3.

[0169] In summary, the HEMT device and the preparation method thereof of the present invention are provided with strain compensation layers including a first strain compensation layer and a second strain compensation layer on the upper surface of the barrier layer between the gate structure and the source and between the gate structure and the drain, respectively, and the first strain compensation layer is adjacent to the gate structure, and the plurality of second strain compensation layers are arranged at intervals, and the second strain compensation layer close to the gate structure is spaced apart from the gate structure by a preset distance, thereby increasing the two-dimensional electron gas density of the channel region close to the source side of the gate structure and below the second strain compensation layer, thereby reducing the on-resistance of the device; and by providing a source field plate structure electrically connected to the source, and the projections of the end points of the first field plate, the second field plate and the third field plate in the source field plate structure away from the source along the Y direction are respectively located between the gate structure and the second strain compensation layer close to the gate structure, between two adjacent second strain compensation layers, and between the drain and the second strain compensation layer close to the drain, thereby reducing the peak values ​​of the channel electric field of the gate structure close to the drain side, between two adjacent second strain compensation layers, and the drain close to the gate structure side, thereby optimizing the electric field in the channel of the device and improving the breakdown voltage of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0170] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A HEMT device, characterized in that: include: A semiconductor structure comprising a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; A gate structure, comprising a cap layer located on an upper surface of the barrier layer and electrically connected to the barrier layer; A source electrode and a drain electrode, respectively located on the upper surface of the barrier layer at opposite sides of the gate structure along the X direction and both electrically connected to the barrier layer; a strain compensation layer, comprising a first strain compensation layer and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is located on an upper surface of the barrier layer between the source electrode and the gate structure and is adjacent to a side wall of the gate structure, and the second strain compensation layer is located on an upper surface of the barrier layer between the drain electrode and the gate structure, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance; A source field plate structure is electrically connected to the source electrode, and includes a first field plate, at least one second field plate and a third field plate which are sequentially arranged upwards and spaced apart from each other.

2. The HEMT device according to claim 1, characterized in that: The gate structure also includes a gate located on the upper surface of the cap layer and electrically connected to the cap layer.

3. The HEMT device according to claim 1, characterized in that: The first strain compensation layer includes aluminum and nitrogen elements, and the second strain compensation layer includes aluminum and nitrogen elements.

4. The HEMT device according to claim 1, characterized in that: The first strain compensation layer and the second strain compensation layer have the same thickness.

5. The HEMT device according to claim 1, characterized in that: At least two of the second strain compensation layers have different lengths along the X direction.

6. The HEMT device according to claim 1, characterized in that: Projections of the ends of the first field plate, the second field plate and the third field plate away from one end of the source along the Y direction are all located between the gate structure and the drain, and the X direction is perpendicular to the Y direction.

7. The HEMT device according to claim 6, characterized in that: The projection of the end of the first field plate away from the source along the Y direction is located between the second strain compensation layer close to the gate structure and the gate structure, the projection of the end of the second field plate away from the source along the Y direction is located between two adjacent second strain compensation layers, and the projection of the end of the third field plate away from the source along the Y direction is located between the second strain compensation layer close to the drain and the drain.

8. The HEMT device according to claim 6, characterized in that: No less than three second strain compensation layers are arranged between the gate structure and the drain, an end of the second field plate away from one end of the source corresponds to the top of the gap between two adjacent second strain compensation layers, and in the direction away from the Y direction, the lengths of the second field plates stacked in sequence at intervals in the X direction gradually increase.

9. The HEMT device according to claim 1, characterized in that: The first field plate, the second field plate and the third field plate have the same thickness.

10. A method for preparing a HEMT device, characterized in that: The following steps are involved: A semiconductor structure is provided, comprising a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; forming a gate structure including a cap layer, wherein the cap layer is located on the upper surface of the barrier layer and is electrically connected to the barrier layer, and forming a strain compensation material layer covering the exposed surface of the barrier layer; Etching the strain compensation material layer to obtain a strain compensation layer, wherein the strain compensation layer includes a first strain compensation layer located at an opposite side of the gate structure along the X direction and a plurality of second strain compensation layers arranged at intervals, wherein the first strain compensation layer is adjacent to the gate structure, and the second strain compensation layer close to the gate structure is spaced from the gate structure by a preset distance; forming a source electrode electrically connected to the barrier layer on a side of the first strain compensation layer away from the gate structure, and forming a drain electrode electrically connected to the barrier layer on a side of the second strain compensation layer away from the gate structure; A source field plate structure electrically connected to the source electrode is formed, wherein the source field plate structure comprises a first field plate, at least one second field plate and a third field plate which are sequentially arranged upwards and spaced apart from each other.

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