Oxide semiconductor layer, semiconductor device, and method for manufacturing semiconductor device

Abstract

The invention relates to an oxide semiconductor layer, a semiconductor device, and a method of manufacturing the semiconductor device. Provided is an oxide semiconductor layer that can be used in a semiconductor device having good electrical characteristics. In addition, the invention provides a semiconductor device and a manufacturing method of the semiconductor device. The present invention is an oxide semiconductor layer containing indium formed on a substrate, the oxide semiconductor layer being formed so as to be parallel or substantially parallel to the surface of the substrate, the oxide semiconductor layer having a first region, a second region on the first region, and a third region on the second region, the first region is substantially vertically located at 0 nm or more and 3 nm or less from a surface on which the oxide semiconductor layer is to be formed, and bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are confirmed in each of the first region, the second region, and the third region when a cross-section of the oxide semiconductor layer is observed by a transmission electron microscope.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also a form of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), CPU (Central Processing Unit), memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer to form a chip and having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, Patent Document 3 discloses a transistor having a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the top surface of an oxide semiconductor.

[0009] In addition, CAAC-IGZO as a crystalline oxide semiconductor is disclosed in Non-Patent Document 1. In addition, Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO and the like.

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0012] [Patent Document 3] International Patent Application Publication No. 2016-125052

[0013] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO: FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp. 50-150 Summary of the invention

[0014] One of the purposes of one embodiment of the present invention is to provide an oxide semiconductor layer that can be used in a semiconductor device such as a transistor. Another purpose of one embodiment of the present invention is to provide an oxide semiconductor layer that can be used in a semiconductor device having good electrical characteristics. Another purpose of one embodiment of the present invention is to provide an oxide semiconductor layer that can be used in a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a novel oxide semiconductor layer. Another purpose of one embodiment of the present invention is to provide a novel method for manufacturing an oxide semiconductor layer.

[0015] One of the purposes of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with small unevenness in the electrical characteristics of transistors. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. In addition, one of the purposes of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0016] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not need to achieve all of the above purposes. Purposes other than the above can be extracted from the description of the specification, drawings, and claims.

[0017] One embodiment of the present invention is an oxide semiconductor layer containing indium formed on a substrate, the oxide semiconductor layer being formed in a manner parallel or approximately parallel to the surface of the substrate, the oxide semiconductor layer having a first region, a second region on the first region, and a third region on the second region, the first region being approximately vertically located at a distance of more than 0 nm and less than 3 nm from a formed surface of the oxide semiconductor layer, and when a cross-section of the oxide semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in each of the first region, the second region, and the third region.

[0018] In the above oxide semiconductor layer, preferably, the second region includes zinc, and the second region includes a crystal, and a c-axis of the crystal is substantially parallel to a normal direction of a formed surface of the oxide semiconductor layer.

[0019] In addition, in the above oxide semiconductor layer, the c-axis orientation ratio in the second region is preferably higher than the c-axis orientation ratio in the first region.

[0020] In addition, in the above oxide semiconductor layer, the c-axis orientation ratio in the third region is preferably higher than the c-axis orientation ratio in the first region.

[0021] In the above oxide semiconductor layer, it is preferred that the indium content in the first region is higher than that in the second region, and the indium content in the third region is higher than that in the second region.

[0022] In the above-mentioned oxide semiconductor layer, it is preferable that the oxide semiconductor layer is formed on an insulator, and the insulator has an amorphous structure.

[0023] Another embodiment of the present invention is a semiconductor device, which includes a first insulator on a substrate, an oxide semiconductor layer on the first insulator, a second insulator on the oxide semiconductor layer, and a conductor on the second insulator, the first insulator and the oxide semiconductor layer are formed in a manner parallel or approximately parallel to the surface of the substrate, the oxide semiconductor layer contains indium, the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region, the first region is approximately vertically located at a distance of more than 0 nm and less than 3 nm from a formed surface of the oxide semiconductor layer, and when a cross-section of the oxide semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in each of the first region, the second region, and the third region.

[0024] In the above semiconductor device, preferably, the second region includes zinc, and the second region includes a crystal, wherein a c-axis of the crystal is substantially parallel to a normal direction of a surface on which the oxide semiconductor layer is formed.

[0025] Furthermore, in the above semiconductor device, the c-axis orientation ratio in the second region is preferably higher than the c-axis orientation ratio in the first region.

[0026] Furthermore, in the above semiconductor device, the c-axis orientation ratio in the third region is preferably higher than the c-axis orientation ratio in the first region.

[0027] In the above semiconductor device, preferably, the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0028] Furthermore, in the above semiconductor device, the first insulator preferably has an amorphous structure.

[0029] Preferably, the semiconductor device further includes a third insulator covering the first insulator and the oxide semiconductor layer, an opening reaching the oxide semiconductor layer is formed in the third insulator, and the second insulator and the conductor are arranged in the opening.

[0030] Furthermore, in the above semiconductor device, the second insulator is preferably in contact with the third region.

[0031] In addition, another embodiment of the present invention is a method for manufacturing a semiconductor device, which includes an oxide semiconductor layer including first to third metal oxides, first to third insulators and a conductor, and the manufacturing method includes the following steps: depositing a first insulator on a substrate; depositing an oxide semiconductor layer on the first insulator; heat treating the oxide semiconductor layer; processing the first insulator and the oxide semiconductor layer into an island shape; depositing a third insulator in a manner covering the first insulator and the oxide semiconductor layer; forming an opening in the third insulator that reaches the oxide semiconductor layer; forming a second insulator in the opening; forming a conductor on the second insulator in the opening; in the deposition process of the oxide semiconductor layer, depositing the first metal oxide, depositing the second metal oxide on the first metal oxide, and depositing the third metal oxide on the second metal oxide; both the first metal oxide and the third metal oxide are deposited using a precursor and an oxidant containing indium and using the ALD method; the second metal oxide is deposited using a sputtering target containing indium using a sputtering method.

[0032] In the above method for manufacturing a semiconductor device, preferably, the sputtering target contains zinc, and the sputtering method is performed in an oxygen-containing atmosphere.

[0033] In the method for manufacturing a semiconductor device, the heating temperature of the substrate in the ALD method is preferably 100° C. or higher and 350° C. or lower.

[0034] In the method for manufacturing the semiconductor device, preferably, when observing a cross section of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

[0035] In the above method for manufacturing a semiconductor device, preferably, no clear boundary is observed between the first metal oxide and the second metal oxide, and no clear boundary is observed between the second metal oxide and the third metal oxide.

[0036] In the method for manufacturing a semiconductor device, the temperature of the heat treatment is preferably 350° C. or higher and 550° C. or lower.

[0037] According to one embodiment of the present invention, an oxide semiconductor layer that can be used in a semiconductor device such as a transistor can be provided. In addition, according to one embodiment of the present invention, an oxide semiconductor layer that can be used in a semiconductor device having good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, an oxide semiconductor layer that can be used in a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a novel oxide semiconductor layer can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing an oxide semiconductor layer can be provided.

[0038] According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having low power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having small non-uniformity in the electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device having high productivity can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel display device can be provided.

[0039] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figures 1A to 1D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention;

[0041] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention;

[0042] FIG. 3A to FIG. 3E is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention;

[0043] 4A to 4D is a cross-sectional view of a metal oxide according to one embodiment of the present invention;

[0044] FIG. 5A to FIG. 5D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention;

[0045] FIG. 6A to FIG. 6C is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention;

[0046] Fig. 7A is a plan view showing an example of a semiconductor device, FIG. 7B to FIG. 7D is a cross-sectional view showing an example of a semiconductor device;

[0047] Fig. 8A and Figure 8B is a cross-sectional view showing an example of a semiconductor device;

[0048] Fig.9A is a plan view showing an example of a semiconductor device, FIG. 9B to FIG. 9D is a cross-sectional view showing an example of a semiconductor device;

[0049] Fig. 10A is a plan view showing an example of a semiconductor device, FIG. 10B to FIG. 10D is a cross-sectional view showing an example of a semiconductor device;

[0050] Fig.11A and Fig. 11B is a cross-sectional view showing an example of a semiconductor device;

[0051] Fig. 12A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 12B to FIG. 12D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0052] Fig.13A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 13B to FIG. 13D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0053] Fig.14A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 14B to FIG. 14D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0054] Fig.15A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 15B to FIG. 15D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0055] Fig.16A1 , Fig.16A2 , Fig.16B1 , Figure 16B2 , Fig.16C1 , Fig.16C2 , Fig.16D1 and Fig.16D2is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0056] Fig.17A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 17B to FIG. 17D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0057] Fig.18A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 18B to FIG. 18D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0058] Fig.19A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 19B to FIG. 19D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0059] Fig. 20 is a block diagram illustrating a structural example of a semiconductor device;

[0060] FIG. 21A to FIG. 21H is a diagram illustrating an example of a circuit configuration of a memory cell;

[0061] Fig. 22 is a cross-sectional view showing an example of a semiconductor device;

[0062] Fig.23A and Fig. 23B is a perspective view illustrating a structural example of a semiconductor device;

[0063] Fig.24 is a cross-sectional view showing an example of a semiconductor device;

[0064] Fig.25 is a block diagram illustrating a CPU;

[0065] Fig.26A and Fig.26B is a three-dimensional diagram of a semiconductor device;

[0066] Fig.27A and Fig.27B is a three-dimensional diagram of a semiconductor device;

[0067] Fig.28A and Fig.28B is a diagram showing various levels of class storage devices;

[0068] Fig.29A and Fig.29B is a diagram showing an example of an electronic device, FIG. 29C to FIG. 29E is a diagram showing an example of a large computer;

[0069] Fig.30is a diagram showing an example of a space device;

[0070] Fig.31 is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0071] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0072] Note that in the structure of the invention described below, the same symbols are used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0073] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0074] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0075] In addition, depending on the situation or condition, the “film” and the “layer” may be interchanged. For example, the “conductive layer” may be replaced with the “conductive film”. In addition, the “insulating film” may be replaced with the “insulating layer”. In addition, the “oxide semiconductor film” may be replaced with the “oxide semiconductor layer”. In addition, depending on the situation or condition, the “conductor” may be replaced with the “conductive layer” or the “conductive film”. In addition, depending on the situation or condition, the “insulator” may be replaced with the “insulating layer” or the “insulating film”. In addition, depending on the situation or condition, the “oxide semiconductor” may be replaced with the “oxide semiconductor layer” or the “oxide semiconductor film”.

[0076] In addition, in this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state where the angle formed by two straight lines is greater than -20 degrees and less than 20 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 70 degrees and less than 110 degrees.

[0077] The opening includes, for example, a groove, a slit, etc. In addition, a region where the opening is formed may be referred to as an opening portion.

[0078] Furthermore, the drawings used in this specification and the like show the case where the side wall of the insulator in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the formed surface, but the side wall may also be tapered.

[0079] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to a substrate surface or a formed surface. For example, it is preferable to have a region in which the angle formed by the inclined side surface and the substrate surface or the formed surface (hereinafter, sometimes referred to as a taper angle) is less than 90°. Note that the side surface and the substrate surface of a constituent element do not necessarily have to be completely flat, and may be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0080] Implementation Method 1

[0081] In this embodiment, an oxide semiconductor layer of one embodiment of the present invention is described. Preferably, the oxide semiconductor layer of one embodiment of the present invention is used as a semiconductor layer of a transistor. When the oxide semiconductor layer of one embodiment of the present invention is used as a semiconductor layer of a transistor, the oxide semiconductor layer has a channel formation region. In addition, the oxide semiconductor layer preferably has a source region and a drain region.

[0082] [Oxide semiconductor layer]

[0083] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide layer for the oxide semiconductor layer, the defect state density in the semiconductor layer can be reduced. Therefore, the reliability of a transistor using an oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device equipped with the transistor can be improved.

[0084] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which multiple crystallites (typically, multiple crystallites having a hexagonal crystal structure) have a c-axis orientation and the multiple crystallites are connected without orientation on the ab plane. When a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal part. Therefore, it can also be said that the oxide semiconductor layer having a CAAC structure has a layered crystal part.

[0085] The polycrystalline structure has a grain boundary. In addition, when a heat treatment is performed after the oxide semiconductor layer of the polycrystalline structure is formed, a tiny gap (also called nanocrack or microcrack) or a tiny space (also called nanospace or microspace) may be formed between the crystal parts. If a tiny gap or a tiny space is formed in the oxide semiconductor layer, the resistance of the oxide semiconductor layer becomes higher. This is because the resistance of the tiny gap or the tiny space is very high, for example, the resistance is infinite. When an oxide semiconductor layer with a tiny gap or a tiny space is used in the channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode becomes higher. Therefore, this will have a negative impact on the initial characteristics or reliability of the transistor. The CAAC structure does not observe a clear grain boundary on the ab plane, so a semiconductor device with high reliability can be realized. In addition, since there are few grain boundaries, the barrier to carrier conduction in the channel of the transistor is small, and an increase in the on-state current can be expected.

[0086] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of a plurality of the above methods.

[0087] There is no particular restriction on the crystallinity of the semiconductor material included in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes includes one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a partially crystalline region). When the oxide semiconductor layer has crystallinity, the degradation of transistor characteristics can sometimes be suppressed.

[0088] As the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In the case where the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0089] As a metal oxide according to one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as Indium-based materials include indium-based materials such as quartz and tin-based materials, which are also referred to as AZO, indium-based materials such as indium-aluminum-zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium-based materials such as indium-tin-zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium-based materials such as indium-titanium-zinc oxide (In-Ti-Zn oxide), indium-gallium-zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium-gallium-tin-zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium-gallium-aluminum-zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, indium-based materials such as indium-tin oxide (also referred to as ITSO), gallium-tin oxide (Ga-Sn oxide), and aluminum-tin oxide (Al-Sn oxide) containing silicon may be cited.

[0090] When the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide is increased, the transistor can obtain a large on-state current and high frequency characteristics.

[0091] Note that the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0092] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphine, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0093] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. As a result, the variation of the electrical characteristics of the transistor can be suppressed, and the reliability can be improved.

[0094] In addition, by increasing the ratio of the number of atoms of the element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0095] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0096] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using two deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method. The oxide semiconductor layer formed by two deposition methods can also be referred to as Hybrid OS.

[0097] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. In addition, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0098] In the manufacture of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is deposited using a first deposition method. The metal oxide formed at this time preferably has a CAAC structure. For example, a metal oxide film deposited using a sputtering method tends to have crystallinity.

[0099] When the metal oxide is formed using the first deposition method, a mixed layer is sometimes formed at the interface between the metal oxide and the layer as the formed surface. For example, when the sputtering method is used as the first deposition method, the mixed layer is sometimes formed due to particles released from a target material or the like (also referred to as sputtered particles) or energy supplied to the substrate side by the sputtered particles or the like. The mixed layer may hinder the crystallization of the metal oxide.

[0100] For example, when an insulating layer containing silicon, such as silicon oxide, is used as a formation surface, when a metal oxide is formed on the silicon oxide using the first deposition method, silicon may be mixed into the metal oxide. The impurities such as silicon mixed into the metal oxide may block the crystallization of the metal oxide.

[0101] Therefore, in one embodiment of the present invention, before forming the metal oxide using the first deposition method, the metal oxide is formed using the second deposition method. That is, after forming the metal oxide as the first layer using the second deposition method, the metal oxide is formed as the second layer on the first layer using the first deposition method. At this time, as the second deposition method, it is preferred to use a deposition method that causes less damage to the formed surface than the first deposition method. By using a deposition method that causes less damage to the formed surface as the second deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that is the formed surface of the oxide semiconductor layer can be suppressed. In addition, in the second layer, the mixing of impurities such as silicon can be suppressed, so it is possible to further improve the crystallinity. For example, compared with the sputtering method, the atomic layer deposition (ALD: Atomic Layer Deposition) method and the chemical vapor deposition (CVD: Chemical Vapor Deposition) method can suppress damage to the formed surface, so it is suitable as the second deposition method.

[0102] In addition, as the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of the CAAC structure is sometimes formed. By forming a second layer with high crystallinity on the first layer with low crystallinity or performing a heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the core. As a result, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the formed surface can sometimes be improved.

[0103] In the oxide semiconductor layer of one embodiment of the present invention, it is preferred that the metal oxide is first formed on the surface to be formed by using the second deposition method, and then the metal oxide is formed thereon by using the first deposition method.

[0104] Examples of the first deposition method include a sputtering method and a pulsed laser deposition (PLD: Pulsed Laser Deposition) method.

[0105] As the second deposition method, for example, ALD method, plasma CVD (PECVD: Plasma EnhancedCVD) method, thermal CVD method, optical CVD method, metal organic CVD (MOCVD: Metal Organic CVD) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, etc. can be cited. The MBE method is a deposition method for growing a thin film having a crystal structure reflecting the crystal system of the substrate, and can be said to be one of the deposition methods that causes less damage to the formed surface. In addition, as the second deposition method, a wet method can be used. The wet method is one of the deposition methods that causes less damage to the formed surface. As a wet method, for example, a spray coating method can be cited.

[0106] As an example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer using a second deposition method and then forming a metal oxide as a second layer using a first deposition method. Specifically, the ALD method can be used as the second deposition method, and the sputtering method can be used as the first deposition method. In addition, the metal oxide formed using the first deposition method preferably has a CAAC structure.

[0107] In addition, a third layer may also be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals with the crystals of the second layer as nuclei or seeds. Therefore, even if a deposition method that is easy to have crystallinity is not used as a deposition method for the third layer, the third layer can be crystallized. Here, for example, by using a deposition method with higher coverage than the second layer as the third layer, both high crystallinity and high coverage can be achieved in the entire oxide semiconductor layer. In addition, for example, by using a deposition method that causes less damage than the second layer when forming the third layer, damage to the second layer can be reduced, so that high crystallinity can be achieved in the entire oxide semiconductor layer.

[0108] Furthermore, by providing the first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, thereby obtaining extremely excellent crystallinity. Therefore, it can be expected that the third layer crystallized with the second layer as a core or seed will also form a layer with extremely excellent crystallinity.

[0109] In addition, the third layer is the uppermost layer of the oxide semiconductor layer. When the oxide semiconductor layer is used as a semiconductor layer of a transistor described later, the third layer is, for example, a layer in contact with a gate insulating layer. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility when the transistor is in an on state can be improved.

[0110] As an example, an oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following steps: after forming a metal oxide as a first layer using a second deposition method, forming a metal oxide as a second layer using a first deposition method, and forming a metal oxide as a third layer using a second deposition method. Specifically, the ALD method can be used as the second deposition method, and the sputtering method can be used as the first deposition method. In addition, the metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method is a deposition method having higher coverage than the sputtering method. By using the ALD method as the deposition method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be used to well cover steps, openings, etc. with a high aspect ratio.

[0111] As the sputtering method, there can be cited an RF sputtering method using a high frequency power supply as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0112] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0113] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit very thin films; it can deposit on structures with high aspect ratios or surfaces with large steps; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantitative determination of these elements can be performed by X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but because one or both of the conditions of high substrate temperature during deposition and impurity removal treatment are used, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0114] Unlike a deposition method in which particles released from a target material are deposited, the ALD method is a deposition method in which a film is formed by a reaction on the surface of the object being processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object being processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film that covers the surface of an opening with a high aspect ratio.

[0115] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since the thermal CVD method does not use plasma, the plasma damage to the object to be processed can be reduced. In addition, in the thermal CVD method, no plasma damage is generated during deposition, so a film with fewer defects can be obtained.

[0116] In addition, when the CVD method is used, a film of any composition can be deposited by adjusting the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0117] [Method for producing oxide semiconductor layer]

[0118] The oxide semiconductor 30 as an oxide semiconductor layer can be manufactured, for example, by forming an oxide semiconductor 30a on the layer 29 as a formation surface by an ALD method, forming an oxide semiconductor 30b on the oxide semiconductor 30a by a sputtering method, and forming an oxide semiconductor 30c on the oxide semiconductor 30b by an ALD method. Here, when the layer 29 is deposited on the substrate, the layer 29 and the oxide semiconductor 30 can be formed in parallel or substantially parallel to the substrate surface.

[0119] Furthermore, after forming the oxide semiconductor 30, heat treatment is preferably performed. By performing the heat treatment, the crystallinity of the oxide semiconductor 30 can be improved. Here, the heat treatment is not limited to heat treatment. For example, it can also be heat applied during the manufacturing process.

[0120] Layer 29 is an insulating film, for example, an insulating film of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, etc. Alternatively, layer 29 may be a film as an insulator included in a semiconductor device as described later.

[0121] Alternatively, the layer 29 may be a conductive film. For example, the oxide semiconductor 30 may be formed on a conductive film used as an electrode of a semiconductor device.

[0122] The layer 29 may not have crystallinity. In other words, the layer 29 may have an amorphous structure. In addition, when the layer 29 has crystallinity, it may have a crystal structure with a low lattice matching with the metal oxide included in the oxide semiconductor 30 .

[0123] Reference Figures 1A to 2D An example of a method for manufacturing the oxide semiconductor 30 is described.

[0124] First, an oxide semiconductor 30a ( Figure 1A Next, an oxide semiconductor 30b is formed on the oxide semiconductor 30a ( Figure 1B ).

[0125] The oxide semiconductor 30 b is preferably formed by sputtering. In addition, the oxide semiconductor 30 b preferably has a composition suitable for forming a CAAC structure.

[0126] It is preferable to form the oxide semiconductor 30a by a deposition method that causes less damage to the surface to be formed than by a deposition method of the oxide semiconductor 30b. Here, the oxide semiconductor 30a is formed by an ALD method.

[0127] In the case of depositing a metal oxide film using a sputtering method, alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface sometimes occurs due to damage to the formed surface. In the case of alloying, it is difficult to improve the crystallinity of the alloyed region even when performing the heat treatment described later. In addition, there is the following concern: by using an oxide semiconductor layer having an alloyed region for a transistor, a negative impact is brought to the initial characteristics or reliability of the transistor. Therefore, it is preferred to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer as the formed surface.

[0128] In the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention, an oxide semiconductor 30a is formed on the layer 29, and then an oxide semiconductor 30b is formed by sputtering. At this time, the oxide semiconductor 30a is preferably formed by a deposition method that causes little damage to the formed surface. By forming the oxide semiconductor 30a between the oxide semiconductor 30b and the layer 29 using a deposition method that causes little damage to the formed surface, alloying of components contained in the oxide semiconductor 30 and components contained in the layer 29 can be suppressed, thereby further improving the crystallinity of the oxide semiconductor 30.

[0129] By adopting the above structure, the thickness of the alloyed region can be reduced or reduced to the extent that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm. In addition, Figure 1A and Figure 1B An example is shown in which no alloyed region is formed between the layer 29 and the oxide semiconductor 30 a .

[0130] In addition, the thickness of the alloyed region can be calculated by performing a line analysis of the composition of the region and its periphery using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0131] For example, the EDX line analysis is performed on the above-mentioned region and its periphery with the direction perpendicular to the formed surface of the oxide semiconductor 30a as the depth direction. Next, in the distribution of the quantitative values ​​of each element relative to the depth direction obtained by the analysis, the depth at which the quantitative value of the metal (In when the oxide semiconductor 30a contains In) which is the main component of the oxide semiconductor 30a but not the main component of the layer (here, layer 29) as the formed surface reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the oxide semiconductor 30a. In addition, the depth at which the quantitative value of the element (e.g., Si) which is the main component of the layer as the formed surface but not the main component of the oxide semiconductor 30a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer as the formed surface. Through the above steps, the thickness of the alloyed region can be calculated.

[0132] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm.

[0133] For example, when a silicon oxide layer is used as the layer 29 and the oxide semiconductor 30 formed on the layer 29 is subjected to SIMS analysis, the depth at which the silicon concentration reaches 50% of the maximum concentration in the layer 29 is regarded as the interface, and the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 , preferably reduced to 5.0×10 20 atoms / cm 3 , more preferably reduced to 1.0×10 20 atoms / cm 3 The distance between the depth of and the interface is thickness t_s2. Thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0134] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0135] In addition, by reducing the thickness of the alloyed region, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm in a substantially vertical direction from the formed surface of the oxide semiconductor 30.

[0136] Note that the CAAC structure may be confirmed near the formed surface by observation using TEM. For example, when a cross section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface may be confirmed near the formed surface.

[0137] Alternatively, a diagram showing the crystal orientation can sometimes be used to evaluate the CAAC structure near the formed surface. For example, a cross-sectional TEM image is obtained, and each region in the cross-sectional TEM image is subjected to a fast Fourier transform (FFT: Fast Fourier Transform) to produce an FFT pattern, and the crystal axis direction of each region is calculated, so that a diagram showing the crystal orientation can be obtained. The FFT pattern reflects the same reciprocal space information as the electron diffraction pattern. For example, a region where the angle formed by the calculated crystal axis direction of each region and the formed surface is preferably greater than 70° and less than 110° can be regarded as a CAAC structure.

[0138] In addition, when the oxide semiconductor 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of the CAAC structure may be formed. Figure 1A In the manufacturing stage shown, the oxide semiconductor 30 a may have a region whose crystallinity is lower than that of the oxide semiconductor 30 b .

[0139] Here, a method of forming an In-M-Zn oxide as the oxide semiconductor 30a by using the ALD method will be described. In addition, the details of forming a metal oxide by using the ALD method will be described later.

[0140] First, a source gas including a precursor containing indium is introduced into the chamber to adsorb the precursor onto the surface of the layer 29. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0141] Next, the introduction of the source gas is stopped, the chamber is purged, and the remaining precursors and reaction products are discharged from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are separated while indium is adsorbed to the substrate, thereby forming a layer formed by bonding indium and oxygen (hereinafter referred to as the first layer). As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidant is stopped, the chamber is purged, and the remaining reactants and reaction products are discharged from the chamber.

[0142] Next, a source gas including a precursor containing the element M is introduced into the chamber to be adsorbed onto the first layer. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0143] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed to the substrate, thereby forming a layer (hereinafter referred to as the second layer) in which the element M and oxygen are bonded. Next, the introduction of the oxidant is stopped, and the chamber is purged to exhaust the remaining reactants and reaction products from the chamber.

[0144] Next, a source gas including a precursor containing zinc is introduced into the chamber so as to be adsorbed onto the second layer. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0145] Here, in a thermal ALD method using triethylindium as a precursor containing indium, triethylgallium as a precursor containing gallium, and diethylzinc as a precursor containing zinc, for example, the substrate heating temperature is 100°C to 350°C, preferably 150°C to 300°C.

[0146] Next, the introduction of the source gas is stopped, the chamber is purged, and the remaining precursors and reaction products are exhausted from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer formed by bonding zinc and oxygen (hereinafter referred to as the third layer). Next, the introduction of the oxidant is stopped, the chamber is purged, and the remaining reactants and reaction products are exhausted from the chamber.

[0147] Next, the first layer is formed again on the third layer by the above method. By repeating the above method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0148] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0149] After the oxide semiconductor 30 a is formed by the ALD method, an In—M—Zn oxide is formed as the oxide semiconductor 30 b on the oxide semiconductor 30 a by the sputtering method.

[0150] Here, when the oxide semiconductor 30b is formed by sputtering, the mixed layer 31 is formed on the surface or near the surface of the oxide semiconductor 30a. In addition, due to sputtered particles or energy supplied to the substrate side by the sputtered particles when the oxide semiconductor 30b is formed, a tiny crystalline region may be formed in the mixed layer 31. In the subsequent heat treatment process, at least a part of the oxide semiconductor 30a may be crystallized using the mixed layer 31 or the tiny crystalline region formed in the mixed layer 31 as a nucleus.

[0151] As a target material for the sputtering method, In-M-Zn oxide can be used. For example, when a metal oxide is formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0152] In some cases, a metal oxide with higher crystallinity can be formed as the flow rate ratio of the oxygen gas to the entire deposition gas used in the formation (hereinafter also referred to as the oxygen flow rate ratio) is higher.

[0153] In the case of forming a metal oxide by sputtering, an oxygen-excess metal oxide can sometimes be formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 30% and less than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide in a channel formation region can obtain higher reliability. Note that one embodiment of the present invention is not limited to this. An oxygen-deficient metal oxide is formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 1% and less than 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide in a channel formation region can have a higher field effect mobility.

[0154] When the metal oxide is formed by sputtering, the composition of the metal oxide after formation may be different from that of the sputtering target. In particular, the zinc content of the metal oxide after formation may be reduced to about 50% of the zinc content in the sputtering target.

[0155] When the oxide semiconductor 30b is deposited by sputtering, the substrate is preferably heated. When a metal oxide is formed, a metal oxide with high crystallinity can sometimes be formed by increasing the substrate temperature (stage temperature) when the metal oxide is formed. When the oxide semiconductor 30b is deposited by sputtering, the substrate heating temperature is preferably, for example, 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0156] Through the above process, Figure 1B As shown, an oxide semiconductor 30 a may be formed on the layer 29 and an oxide semiconductor 30 b may be formed on the oxide semiconductor 30 a .

[0157] Next, an oxide semiconductor 30c ( Figure 1C Here, the oxide semiconductor 30 c is formed by the ALD method. The formation method of the oxide semiconductor 30 a can be referred to for the formation of the oxide semiconductor 30 c by the ALD method.

[0158] When an oxide semiconductor 30c having a CAAC structure and having lower crystallinity than that of the CAAC structure is formed by the ALD method on the oxide semiconductor 30b having the CAAC structure, the oxide semiconductor 30c sometimes grows epitaxially with the oxide semiconductor 30b as a core. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c sometimes includes a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed in the entire oxide semiconductor 30c.

[0159] Next, a heat treatment step may be performed.

[0160] The heat treatment temperature can be, for example, above 100°C and below 800°C, preferably above 250°C and below 650°C, and more preferably above 350°C and below 550°C. Typically, it can be 400°C±25°C (above 375°C and below 425°C). In addition, the treatment time can be below 10 hours, above 1 minute and below 5 hours, or above 1 minute and below 2 hours. In addition, when using an RTA device, the treatment time can be, for example, above 1 second and below 5 minutes. Through this heat treatment, it can be expected that the voids in the atomic-level crystalline portion of the CAAC structure of the oxide semiconductor 30b are repaired by the oxide semiconductor 30c (in other words, each crystalline molecule formed using the ALD method).

[0161] There is no particular limitation on the heating device used for heat treatment, and there may be a device that utilizes heat conduction or heat radiation from a heating element such as a resistance heating element to heat the object to be treated. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device may be used. The LRTA device is a device that utilizes radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp to heat the object to be treated. The GRTA device is a device that uses high-temperature gas for heat treatment.

[0162] Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c is sometimes improved. In addition, after deposition using the ALD method, when the region is formed only below the oxide semiconductor 30c, the region sometimes expands upward due to the heat treatment process ( Figure 1D ) That is, by performing this heat treatment, a region having a CAAC structure may be formed in the entire oxide semiconductor 30c.

[0163] In addition, by this heat treatment step, the oxide semiconductor 30 b may be further repaired by the oxide semiconductor 30 c (in other words, each crystal molecule formed by the ALD method) filling the gaps between the atomic-level crystal parts of the CAAC structure of the oxide semiconductor 30 b.

[0164] In addition, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by the heat treatment step ( Figure 1D ). It can be expected that CAAC formation is easily caused by using the mixed layer 31 formed in the oxide semiconductor 30a when the oxide semiconductor 30b is deposited as a core or a seed. The CAAC formation region in the oxide semiconductor 30a is preferably large, preferably reaching the vicinity of the layer 29.

[0165] In addition, since CAAC is formed from the upper part to the lower part of the oxide semiconductor 30a, it is not limited by the material or crystallinity of the layer 29, and it is possible to reach the vicinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a with high crystallinity can be formed. Therefore, the method for manufacturing an oxide semiconductor layer of one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0166] Figures 1A to 1D : is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention. Figures 1A to 1DIt can also be viewed as a schematic diagram of a deposition model of a metal oxide showing one embodiment of the present invention. Figures 1A to 1D As shown, the oxide semiconductor 30a and the oxide semiconductor 30c respectively use the oxide semiconductor 30b with high crystallinity as a core or a seed to improve crystallinity. Specifically, the crystallinity of the oxide semiconductor 30a is sometimes improved by heat treatment when the oxide semiconductor 30b is deposited or after the oxide semiconductor 30c is deposited. In addition, the crystallinity of the oxide semiconductor 30c is sometimes improved by heat treatment when the oxide semiconductor 30c is deposited or after the oxide semiconductor 30c is deposited. In addition, the above-mentioned heat treatment plays an auxiliary role in improving crystallinity.

[0167] Thus, in a metal oxide deposition method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductor 30a and oxide semiconductor 30c) can be improved by using the highly crystalline oxide semiconductor 30b (i.e., CAAC) as a core or seed. Thus, the crystallinity of the entire oxide semiconductor can be improved. In other words, the upper and lower oxide semiconductors are solid-phase grown using the oxide semiconductor 30b as a core or seed, thereby forming an oxide semiconductor with high crystallinity. The oxide semiconductor formed using the above deposition method, in this CAAC film, can be referred to as axial growth (AxialGrowth) CAAC (AG CAAC).

[0168] In the entire oxide semiconductor 30 including the oxide semiconductor 30 a and the oxide semiconductor 30 c , a region having a CAAC structure preferably exists widely in the entire layer. Figure 2A The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are all shown to be crystallized. The crystals in the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The crystals in the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. As a result, the boundary between the oxide semiconductor 30a and the oxide semiconductor 30b is sometimes not observed. In addition, the boundary between the oxide semiconductor 30b and the oxide semiconductor 30c is sometimes not observed. The oxide semiconductor 30 can sometimes be described as a layer without a clear interface being observed. The oxide semiconductor 30 can sometimes be described as a single layer.

[0169] In addition, a part of the oxide semiconductor 30 a or the oxide semiconductor 30 c may not be crystallized. In addition, a region having lower crystallinity than the CAAC structure may remain in a part of the oxide semiconductor 30 a or the oxide semiconductor 30 c. Figure 2BAs an example, a case is described in which the oxide semiconductor 30 a is not crystallized near the interface with the layer 29 , or a region having lower crystallinity than the CAAC structure remains near the interface. Figure 2C This shows a case where, in the oxide semiconductor 30 c , the vicinity of the surface is not crystallized or a region having lower crystallinity than the CAAC structure remains near the surface. Figure 2D The following situation is shown: the oxide semiconductor 30a and the layer 29 and the oxide semiconductor 30c are not crystallized near the interface, or the oxide semiconductor 30a and the layer 29 and the oxide semiconductor 30c have lower crystallinity than the CAAC structure.

[0170] By improving the crystallinity of the oxide semiconductor layer, the resistance increase of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed or the initial characteristics of the transistor (especially the on-state current) are improved, thereby realizing a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0171] According to the method for manufacturing an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below the metal oxide having the CAAC structure can be improved, so that the entire oxide semiconductor layer has high crystallinity.

[0172] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity as a whole. Therefore, in the oxide semiconductor 30, the boundaries between the stacked films in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are sometimes not confirmed. In particular, after heat treatment, it is sometimes difficult to confirm the boundaries between the stacked films. For example, the presence or absence of the boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM, etc.

[0173] As described above, by using a metal oxide with a high In content ratio for a transistor, the field effect mobility of the transistor can be improved. On the other hand, an oxide semiconductor with a high In content ratio has a tendency to polycrystallize. When a metal oxide with a polycrystalline structure is used for a transistor, it has a negative impact on the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content ratio for one or both of the oxide semiconductor 30a and the oxide semiconductor 30c, a crystal reflecting the orientation of the crystal contained in the oxide semiconductor 30b is formed, thereby suppressing polycrystallization.

[0174] In addition, the lattice mismatch between the crystals included in the oxide semiconductor 30b and the crystals included in the oxide semiconductor 30a or the oxide semiconductor 30c is preferably small. Thus, the oxide semiconductor 30a or the oxide semiconductor 30c can form a crystal that reflects the orientation of the crystals included in the oxide semiconductor 30b. At this time, for example, when the cross-section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0175] As long as the lattice mismatch between the crystal included in the oxide semiconductor 30b and the crystal included in the oxide semiconductor 30a or the oxide semiconductor 30c is small, there is no particular limitation on the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0176] [Composition of Oxide Semiconductor Layer]

[0177] As described above, the oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b can be formed using a sputtering method, for example. The oxide semiconductor 30b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be obtained. In addition, the oxide semiconductor 30b preferably contains an element M in addition to zinc. By making the oxide semiconductor 30b contain the element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor layer can be improved. As the oxide semiconductor 30b, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. In addition, the nearby composition includes a range of ±30% of the desired atomic ratio. As the element M, one or more of gallium, aluminum, and tin are preferably used.

[0178] The oxide semiconductor 30b may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, a composition of In:Zn=2:1 [atomic ratio] or a composition near it, or a composition of In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, a trace amount of element M may also be contained. For example, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it. In addition, for example, it may be a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0179] The oxide semiconductor 30a and the oxide semiconductor 30c can use a metal oxide having a high In ratio. The oxide semiconductor 30a and the oxide semiconductor 30c can be formed, for example, using an ALD method. In addition, it is particularly preferred to use a metal oxide having a higher In ratio than the element M. By using a metal oxide having a high In ratio, when the oxide semiconductor layer is used for a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0180] In addition, the oxide semiconductor 30a and the oxide semiconductor 30c may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, In:Zn=2:1 [atomic ratio] or a composition near it, or In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, the oxide semiconductor 30a and the oxide semiconductor 30c may also contain a trace amount of the element M. Specifically, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0181] Alternatively, the oxide semiconductor 30 a and the oxide semiconductor 30 c may use a metal oxide having a higher In content than the oxide semiconductor 30 b .

[0182] For example, as the oxide semiconductor 30a and the oxide semiconductor 30c, a metal oxide with a higher Ga ratio than the oxide semiconductor 30b may be used. For example, the oxide semiconductor 30a and the oxide semiconductor 30c preferably use a metal oxide with a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide with a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide with a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the Ga ratio, for example, the band gaps of the oxide semiconductors 30a and 30c can sometimes be made larger than the oxide semiconductor 30b. Thus, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c having a large band gap, and the oxide semiconductor 30b is mainly used as a current path (channel). By sandwiching the oxide semiconductor 30b between the oxide semiconductors 30a and 30c, the trap states at the interface of the oxide semiconductor 30b and its vicinity can be reduced. Thus, a buried channel transistor in which the channel is far away from the insulating layer interface can be realized, thereby improving the field effect mobility. Furthermore, the influence of the interface state that may be formed on the back channel side is reduced, and light degradation of the transistor (for example, light negative bias degradation) can be suppressed, thereby improving the reliability of the transistor.

[0183] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the oxide semiconductor 30a and the oxide semiconductor 30c have a composition that does not easily form a CAAC structure when forming a single layer, the entire oxide semiconductor layer including the oxide semiconductor 30a and the oxide semiconductor 30c can have a CAAC structure by causing crystal growth with the oxide semiconductor 30b as a core. Alternatively, the region including at least a portion of each of the oxide semiconductor 30a and the oxide semiconductor 30c to the region of the oxide semiconductor 30b can have a CAAC structure.

[0184] In particular, when the oxide semiconductor 30a and the oxide semiconductor 30c have a composition with a high ratio of In, the crystallinity of the semiconductor layer suitable for the transistor can also be obtained. In the oxide semiconductor layer of one embodiment of the present invention, the reliability can be improved by adopting a CAAC structure with high crystallinity while increasing the ratio of In to improve the turn-on characteristics of the transistor.

[0185] Note that the composition of the oxide semiconductor 30 a and the composition of the oxide semiconductor 30 c may be different.

[0186] Alternatively, the oxide semiconductor 30 a and the oxide semiconductor 30 c may use a metal oxide having the same composition as the oxide semiconductor 30 b . Using the same composition may facilitate CAAC formation after heat treatment.

[0187] In addition, compared with an oxide semiconductor layer having a CAAC structure formed using one deposition method, any one or more of the relative dielectric constant, film density, and film hardness of the oxide semiconductor layer having a CAAC structure formed using the above-mentioned two deposition methods is sometimes higher.

[0188] By using an oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above for the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0189] The composition of the metal oxide used for the oxide semiconductor 30 can be analyzed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low content ratios are sometimes affected by the accuracy of the analysis, and the actual content ratio is different from the content ratio obtained by analysis. For example, when the content ratio of element M is low, the content ratio of element M obtained by analysis is sometimes lower than the actual content ratio.

[0190] [Oxide semiconductor layer of transistor]

[0191] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0192] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, further preferably 10 nm or more and 70 nm or less, further preferably 15 nm or more and 70 nm or less, further preferably 15 nm or more and 50 nm or less, further preferably 20 nm or more and 50 nm or less. In addition, in a transistor used for a more micro-sized semiconductor device, the thickness of the oxide semiconductor 30 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0193] The thickness of the oxide semiconductor 30b is preferably, for example, 200 nm or less. When the oxide semiconductor 30b is layered, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and further preferably 2 nm to 100 nm.

[0194] Alternatively, if the oxide semiconductor 30 b can function as a crystal nucleus, the oxide semiconductor 30 b may exist not as a layer but as a collection of island-shaped regions. In this case, for example, the island-shaped regions included in the oxide semiconductor 30 b exist dispersedly.

[0195] The thickness of the oxide semiconductor 30 a and the oxide semiconductor 30 c is, for example, preferably from 1 nm to 50 nm, more preferably from 1 nm to 30 nm, further preferably from 1 nm to 20 nm, and still more preferably from 2 nm to 20 nm.

[0196] The oxide semiconductor layer according to one embodiment of the present invention includes a metal oxide.

[0197] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0198] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the metal oxide used for the semiconductor layer of the transistor has fewer lattice defects.

[0199] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0200] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0201] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferred to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by setting a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0202] [Impurities in oxide semiconductors]

[0203] Here, the influence of each impurity in the oxide semiconductor is described.

[0204] In the channel formation region of a transistor using an oxide semiconductor as a semiconductor layer, it is preferred that the channel formation region has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source region and the drain region. O ) and impurities, the electrical properties are easily changed and reliability may be reduced. In addition, hydrogen near the oxygen vacancy forms V O H may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor has a normally-on characteristic. Therefore, in the channel formation region, V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0205] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to elements other than the main components of oxide semiconductors. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0206] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0207] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0208] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , and further preferably less than 1×10 18 atoms / cm 3 , and further preferably less than 1×10 17 atoms / cm 3 .

[0209] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0210] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0211] [c-axis orientation]

[0212] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. For example, the crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0213] By performing Fast Fourier Transform (FFT) processing on the TEM image, the crystal orientation can be obtained from the FFT pattern. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects the same reciprocal spatial information as the electron diffraction pattern.

[0214] By performing FFT processing on each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of the region having the layered crystal part. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots.

[0215] The c-axis orientation degree can be calculated by calculating the ratio of the c-axis orientation region in the graph showing the crystal orientation. Here, the c-axis orientation region refers to a region whose orientation coincides with the c-axis and whose difference from the c-axis is preferably within 20°.

[0216] In the oxide semiconductor layer of one embodiment of the present invention, for example, a cross-section or planar TEM observation of the oxide semiconductor layer can be performed to calculate the c-axis orientation. In addition, the region where FFT is performed (also referred to as FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0217] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation degree is preferably 60% or more, more preferably 70% or more, further preferably 80% or more, further preferably 90% or more, and further preferably 95% or more.

[0218] In addition, the c-axis orientation degrees of the region deposited as the oxide semiconductor 30a, the region deposited as the oxide semiconductor 30b, and the region deposited as the oxide semiconductor 30c are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 60% or more, more preferably 70% or more, further preferably 80% or more, further preferably 90% or more, and further preferably 95% or more. In addition, Rc3 is preferably 60% or more, more preferably 70% or more, further preferably 80% or more, further preferably 90% or more, and further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0219] After the oxide semiconductor 30 is manufactured, the boundaries among the oxide semiconductor 30 a , the oxide semiconductor 30 b , and the oxide semiconductor 30 c may not be observed.

[0220] The oxide semiconductor 30 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region, in order from the layer 29 side. Each region is a layered region.

[0221] The first region, the second region, and the third region all have a CAAC structure. In addition, the c-axis orientation of the third region is preferably higher than that of the first region. In addition, the c-axis orientation of the second region is preferably higher than that of the first region. In addition, the c-axis orientation of the third region is preferably greater than 80%, more preferably greater than 90%, and more preferably greater than 95%. In addition, the c-axis orientation of the second region is preferably greater than 80%, more preferably greater than 90%, and more preferably greater than 95%.

[0222] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 29 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 30 .

[0223] Alternatively, the thickness of the layer in each region is, for example, substantially equal.

[0224] [Method for producing metal oxide by ALD method]

[0225] Here, use FIG. 3A to FIG. 3E An example of a method for depositing a three-layered crystal structure metal oxide using the ALD method is described. First, a precursor 611a is introduced into a chamber so that the precursor 611a is adsorbed onto the surface of a substrate 610 (see Figure 3A Hereinafter, this process is sometimes referred to as the first step. Figure 3A As shown, since the precursor 611a is adsorbed onto the surface of the substrate 610, the self-stop mechanism of the surface chemical reaction takes effect and the precursor 611a is no longer adsorbed on the layer of the precursor 611a on the substrate 610. Note that the appropriate range of substrate temperature for the self-stop mechanism of the surface chemical reaction to take effect is also referred to as the ALD window. The ALD window is determined based on the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and is sometimes set to be above 100°C and below 600°C, and preferably above 200°C and below 400°C.

[0226] Next, by introducing an inert gas (argon, helium, nitrogen, etc.) into the chamber, the remaining precursor 611a and the reaction product are exhausted from the chamber (hereinafter, this process is sometimes referred to as the second step). Alternatively, the remaining precursor and the reaction product may be exhausted from the chamber by vacuum exhaust instead of introducing the inert gas into the chamber. The second step is also called purging.

[0227] Next, a reactant 612a (e.g., an oxidant (ozone (O3), oxygen (O2), water (H2O) and their plasma, free radicals, ions, etc.)) is introduced into the chamber to react with the precursor 611a adsorbed on the surface of the substrate 610, so that a part of the components in the precursor 611a is detached while the constituent molecules of the precursor 611a are adsorbed on the substrate 610 (see Figure 3B (This process may be referred to as a third step hereinafter.) As a result, a layer of an oxide 613 a formed by oxidation of a portion of the precursor 611 a is formed on the surface of the substrate 610 .

[0228] Next, the remaining reactant 612a and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust (hereinafter, this process may be referred to as a fourth step).

[0229] Next, a precursor 611b containing a metal element different from the precursor 611a is introduced, and the same process as the first step is performed to make the precursor 611b adsorbed on the surface of the oxide 613a layer (see Figure 3C ). Here, if Figure 3C As shown, since the precursor 611 b is adsorbed onto the layer of the oxide 613 a , the self-stopping mechanism of the surface chemical reaction takes effect and the precursor 611 b is no longer adsorbed onto the layer of the precursor 611 b on the substrate 610 .

[0230] Next, similarly to the second step, the remaining precursor 611 b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0231] Next, as in the third step, a reactant 612b is introduced into the chamber. Here, the reactant 612b may be the same as or different from the reactant 612a (see Figure 3D ). As a result, a layer of oxide 613b formed by oxidation of a portion of the precursor 611b is formed on the layer of oxide 613a.

[0232] Next, similarly to the fourth step, the remaining reactant 612b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0233] Furthermore, by performing the first to fourth steps in the same manner, a layer of oxide 613c can be formed on the layer of oxide 613b. In this way, by repeatedly performing the steps of forming oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of oxides 613a to 613c is repeated can be formed (see Figure 3E). That is, the first to fourth steps can be used as a set to form an oxide layer, and by repeatedly performing this set, a layered crystal structure in which a plurality of oxide layers are stacked can be formed.

[0234] Furthermore, the thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, and preferably 3 nm or more and less than 20 nm.

[0235] Furthermore, when forming a metal oxide having a layered crystal structure, it is preferable to carry out the step while heating the substrate. FIG. 3A to FIG. 3E The process shown. For example, the substrate temperature can be set to be above 200°C and below 600°C, preferably above 300°C and below the decomposition temperature of the precursor. Note that when using multiple precursors of different types and depositing by the ALD method, it is preferred to set the substrate temperature below the decomposition temperature of the lowest precursor among the multiple precursors. Thus, in the deposition by the ALD method, the multiple precursors used can be adsorbed onto the object (for example, a substrate, etc.) without being decomposed.

[0236] By performing the above deposition while heating the substrate within the above temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process from step 1 to step 4. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. In addition, metal atoms and oxygen atoms are rearranged while removing the above impurities, so that the layers of each oxide can be arranged with high order. Thus, a metal oxide with a layered crystal structure with high crystallinity can be formed.

[0237] In order to perform deposition while heating the substrate within the above-mentioned temperature range, the decomposition temperature of the precursor used for the above-mentioned deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, a precursor formed by an inorganic substance (hereinafter referred to as an inorganic precursor) is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed by organic substances (hereinafter referred to as organic precursors), and sometimes their ALD windows are located within the above-mentioned temperature range. In addition, because inorganic precursors do not contain impurities such as hydrogen or carbon, the concentration of impurities such as hydrogen or carbon in the deposited metal oxide can be prevented from increasing.

[0238] Furthermore, it is preferred that the heat treatment be performed after the deposition of the metal oxide. In particular, it is preferred that the heat treatment be performed continuously after the deposition using the ALD method without being exposed to the outside air. The heat treatment may be performed at Figures 1A to 1D Under the conditions described above.

[0239] By performing heat treatment in this way, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. In addition, metal atoms and oxygen atoms are rearranged while removing the above impurities, so that crystallinity can be improved. Thus, a metal oxide with a layered crystal structure with high crystallinity can be formed.

[0240] In addition, it is preferred that microwave treatment is performed in an oxygen-containing atmosphere after the deposition of the above-mentioned metal oxide to reduce the concentration of impurities in the metal oxide. As impurities, hydrogen and carbon can be mentioned in particular. Note that the above shows a structural example of microwave treatment of metal oxide in an oxygen-containing atmosphere, but is not limited to this. For example, microwave treatment can also be performed on an insulating film located near the metal oxide, specifically a silicon oxide film, in an oxygen-containing atmosphere.

[0241] Note that FIG. 3A to FIG. 3E In the above description, a structure in which the stacked structure of oxides 613a to 613c is repeated is described, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more layers of oxides are repeatedly formed may be used.

[0242] In addition, in the description of this specification, when ozone, oxygen, or water is used as a reactant or oxidant, unless otherwise specified, these include plasma states, free radical states, and ion states, and are not limited to gaseous states or molecular states. When deposition is performed using an oxidant in a plasma state, free radical state, or ion state, a plasma ALD apparatus described below may be used.

[0243] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferred to allow the precursor to fully react with the oxidant. For example, a longer pulse time for introducing the oxidant can be set. Alternatively, the oxidant can be introduced multiple times. When the oxidant is introduced multiple times, the same type of oxidant can be introduced, and different types of oxidants can be introduced. For example, it is also possible to introduce water as a first oxidant into the chamber and then perform vacuum exhaust, and introduce ozone or oxygen that does not contain hydrogen into the chamber as a second oxidant and perform vacuum exhaust.

[0244] In this way, by repeatedly introducing the oxidant and the inert gas (or vacuum exhaust) in the chamber for a short period of time, the remaining hydrogen atoms, carbon atoms, chlorine atoms, etc. can be further reliably removed from the precursor adsorbed on the substrate surface and discharged outside the chamber. In addition, by introducing two oxidants, more remaining hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being introduced into the film during deposition, water, hydrogen, etc. contained in the formed film can be reduced.

[0245] The ALD method is a deposition method that uses thermal energy to react precursors and reactants. The temperature required for the reaction of the precursors and reactants is determined according to their temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to be above 100°C and below 600°C, preferably above 200°C and below 600°C, and more preferably above 300°C and below 600°C.

[0246] Furthermore, an ALD method in which the above-mentioned precursor and reactant react and a reactant excited by plasma is introduced into a chamber as a third source gas for processing is sometimes referred to as a plasma ALD method. In this case, a plasma generating device is provided in the introduction portion of the third source gas. When generating plasma, an inductively coupled plasma (ICP) can be used. On the other hand, an ALD method in which a precursor and a reactant react using thermal energy is sometimes referred to as a thermal ALD method.

[0247] In the plasma ALD method, the reactant excited by the plasma in the third step is introduced for deposition. Alternatively, deposition is performed by repeatedly performing the first step to the fourth step while introducing the reactant excited by the plasma (the second reactant). In this case, the reactant introduced in the third step is referred to as the first reactant. In the plasma ALD method, the second reactant used for the third source gas can use the same material as the above-mentioned oxidant. That is, ozone, oxygen and water excited by the plasma can be used as the second reactant. In addition, a nitriding agent can be used as the second reactant in addition to the oxidant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. In addition, a mixed gas of nitrogen (N2) and hydrogen (H2) can be used as a nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as a nitriding agent. By depositing while introducing nitrogen or ammonia excited by plasma, a nitride film such as a metal nitride film can be formed.

[0248] In addition, argon (Ar), helium (He) or nitrogen (N2) may be used as a carrier gas for the second reactant. By using a carrier gas such as argon, helium or nitrogen, it is easy to discharge plasma and generate a second reactant excited by the plasma, so it is preferred. Note that when an oxide film such as a metal oxide film is formed by a plasma ALD method and nitrogen is used as a carrier gas, nitrogen may be mixed into the film and the desired film quality may not be obtained. In this case, it is preferred to use argon or helium as a carrier gas.

[0249] By using the ALD method, a very thin film can be deposited with a uniform thickness, and a high coverage rate can be achieved on a surface having irregularities.

[0250] Here, refer to 4A to 4DThis is an explanation of the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide. Figure 4B and Figure 4D In the diagram, atoms are represented by spheres (circles), and the bonds between metal atoms and oxygen atoms are represented by lines. Figure 4B and Figure 4D In the figure, the c-axis direction in the crystal structure of the In-M-Zn oxide is indicated by the arrow in the figure. In addition, the ab plane direction in the crystal structure of the In-M-Zn oxide is the same as that in Figure 4B and Figure 4D The direction is perpendicular to the c-axis direction indicated by the arrow.

[0251] Figure 4A 6 is a diagram showing an oxide 660 including an In-M-Zn oxide formed on a structure 650. Here, a structure refers to a constituent element constituting a semiconductor device such as a transistor. The structure 650 includes: a substrate; a conductor such as a gate electrode, a source electrode, and a drain electrode; an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film; and a semiconductor such as a metal oxide and silicon. Figure 4A The case where the deposition surface of the structure 650 is arranged in parallel with the substrate (or base, not shown) is shown.

[0252] Figure 4B It is shown Figure 4A This is an enlarged view of the atomic arrangement in the crystal of a portion of region 653 of oxide 660. Figure 4A and Figure 4B The composition of the oxide 660 shown is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4 type structure. In addition, the element M is a +3 valent metal element.

[0253] like Figure 4B As shown, the crystals included in the oxide 660 are repeatedly stacked in sequence, including a layer 621 containing indium (In) and oxygen, a layer 631 containing element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen. The layers 621, 631, and 641 are arranged in a manner substantially parallel to the deposited surface of the structure 650. In other words, the ab plane of the oxide 660 is substantially parallel to the deposited surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposited surface of the structure 650.

[0254] like Figure 4B As shown, the layer 621, the layer 631, and the layer 641 of the crystal are all composed of a metal element and oxygen, and can be arranged with high crystallinity to improve the mobility of the metal oxide.

[0255] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:1:1 [atomic ratio] is not limited to Figure 4B The structure shown in FIG. 6 is a structure of ...

[0256] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] is shown, but its composition formula is In (1+α) M (1-α) O3(ZnO) m (α is a real number greater than 0 and less than 1, and m is a positive number) can also have a layered crystal structure. Figure 4C and Figure 4D An In-M-Zn oxide having a composition of In:M:Zn=1:3:4 [atomic number ratio] is shown.

[0257] Figure 4C is a diagram showing an oxide 662 including an In-M-Zn oxide formed on the structure 650. Figure 4D It is shown Figure 4C An enlarged view of the atomic arrangement in the crystal of a region 654 of a portion of oxide 662 is shown.

[0258] like Figure 4D As shown, the crystal included in the oxide 662 has a layer 622 containing indium (In), element M and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing element M and oxygen. In the oxide 662, as a plurality of layers, a layer 622, a layer 641, a layer 631, and a layer 641 are repeatedly stacked in sequence. The layer 622, the layer 631, and the layer 641 are arranged in a manner substantially parallel to the deposited surface of the structure 650. In other words, the ab plane of the oxide 662 is substantially parallel to the deposited surface of the structure 650, and the c axis of the oxide 662 is substantially parallel to the normal direction of the deposited surface of the structure 650.

[0259] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:3:4 [atomic ratio] is not limited to Figure 4DThe structure shown may be changed within the range of In:M:Zn=1:3:4 [atomic ratio]. For example, the stacking order of layer 622, layer 631, and layer 641 may be changed. In addition, a part of the element M of layer 631 may be replaced by zinc, and a part of the zinc of layer 641 may be replaced by element M. In addition, layer 621 or layer 631 may be formed instead of layer 622.

[0260] Next, refer to FIG. 5A to FIG. 6C Show Figure 4A and Figure 4B Detailed formation method of oxide 660 including In-M-Zn oxide is shown.

[0261] First, a source gas including a precursor containing indium is introduced into the chamber so that the precursor is adsorbed onto the surface of the structure 650 (see Figure 5A Here, the source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing indium, trimethylindium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0262] In addition, as a precursor containing indium, an inorganic precursor that does not contain hydrocarbons can also be used. As an inorganic precursor containing indium, a halogen indium compound such as indium trichloride, indium tribromide, or indium triiodide can be used. The decomposition temperature of indium trichloride is about 500°C or more and about 700°C or less. Therefore, by using indium trichloride, the substrate can be heated at about 400°C or more and about 600°C or less, for example, at 500°C, while deposition is performed using the ALD method.

[0263] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0264] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are desorbed while indium is adsorbed on the substrate, thereby forming a layer 621 formed by bonding indium and oxygen (see Figure 5B As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0265] Next, a source gas including a precursor containing element M is introduced into the chamber so that the precursor is adsorbed onto layer 621 (see Figure 5C). The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. When gallium is used as the element M, as a precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethyl gallium chloride, diethyl gallium chloride, dimethyl gallium isopropoxide, etc. can be used.

[0266] In addition, as a precursor containing gallium, an inorganic precursor that does not contain hydrocarbons may also be used. As an inorganic precursor containing gallium, a halogen gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide may be used. The decomposition temperature of gallium trichloride is about 550°C to about 700°C. Therefore, by using gallium trichloride, the substrate may be heated at about 450°C to about 650°C, for example, at 550°C, while deposition is performed using the ALD method.

[0267] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0268] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed on the substrate, thereby forming a layer 631 formed by bonding the element M and oxygen (see Figure 5D At this time, a part of the oxygen constituting the layer 641 may be adsorbed on the layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0269] Next, a source gas including a zinc precursor is introduced into the chamber so that the precursor is adsorbed onto the layer 631 (see Fig. 6A ). At this time, a portion of the layer 641 formed by bonding zinc and oxygen is sometimes formed. The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing zinc, dimethyl zinc, diethyl zinc, bis (2,2,6,6-tetramethyl-3,5-heptanedione) zinc, zinc acetate, etc. can be used.

[0270] In addition, as a precursor containing zinc, an inorganic precursor that does not contain hydrocarbons can also be used. As an inorganic precursor containing zinc, a halogen-based zinc compound such as zinc dichloride, zinc dibromide, and zinc diiodide can be used. The decomposition temperature of zinc dichloride is about 450°C or more and about 700°C or less. Therefore, by using zinc dichloride, the substrate can be heated at about 350°C or more and about 550°C or less, for example, at 450°C, while deposition is performed using the ALD method.

[0271] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0272] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer 641 formed by bonding zinc and oxygen (see Figure 6B ). Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0273] Next, layer 621 is formed again on layer 641 by the above method (see Figure 6C ). By repeatedly performing the above method, an oxide 660 can be formed on the substrate or the structure.

[0274] Note that the above-mentioned precursor may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. In addition, a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.

[0275] As described above, by forming the oxide 660 using the ALD method, a metal oxide can be formed whose c-axis is oriented approximately parallel to the normal direction of the deposition surface. By adopting this structure, the layered crystals of the oxide semiconductor 30 are approximately parallel to the channel length direction of the transistor 200, so the on-state current of the transistor can be increased.

[0276] Preferably, the substrate is heated while FIG. 5A to FIG. 6C For example, the substrate temperature may be set to 200° C. or higher and 600° C. or lower, preferably 300° C. or higher and lower than the decomposition temperature of the precursor.

[0277] In order to perform deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, an inorganic precursor is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if deposition is performed while heating the substrate as described above, the precursor is not easily decomposed.

[0278] As inorganic precursors, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As mentioned above, the decomposition temperature of these precursors is above 350°C and below 700°C, which is much higher than the decomposition temperature of general organic precursors. However, as mentioned above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. When using multiple precursors of such different types and depositing using the ALD method, it is preferred to set the substrate temperature to be below the lowest decomposition temperature among the decomposition temperatures of the multiple precursors. In the above example, the substrate temperature can be set within a range in which zinc dichloride, which has the lowest decomposition temperature of the precursor, will not decompose. Thus, in a state where other indium trichlorides and gallium trichlorides are not decomposed, they can be adsorbed onto an object (for example, a substrate, etc.).

[0279] Notice, FIG. 5A to FIG. 6C Although an example is shown in which layer 621 is formed as a layer containing indium, layer 631 is formed as a layer containing element M thereon, and layer 641 is formed as a layer containing zinc thereon, this embodiment is not limited thereto. Alternatively, one of layer 631 and layer 641 may be formed, layer 621 may be formed thereon, and the other of layer 631 and layer 641 may be formed thereon. Alternatively, one of layer 631 and layer 641 may be formed, the other of layer 631 and layer 641 may be formed thereon, and layer 621 may be formed thereon.

[0280] In addition, when a metal oxide having an atomic ratio other than In:M:Zn=1:1:1 [atomic ratio] is formed, the above-mentioned layer 621, layer 631, and layer 641 can be appropriately formed according to the atomic ratio. Fig. 6A By repeatedly forming the layer 641 before and after the formation of the layer 631 shown, a stack of the layer 631 and the layer 641 having a desired number of atoms, number of layers, and thickness can be formed between the two layers 621 .

[0281] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0282] Implementation Method 2

[0283] In this embodiment, using 7A to 19D A semiconductor device using the oxide semiconductor described in Embodiment 1 and a method for manufacturing the semiconductor device are described.

[0284] <Structural Example of Semiconductor Device>

[0285] use 7A to 8B A structural example of a semiconductor device will be described. 7A to 7D1 and 2 are a plan view and a cross-sectional view of a semiconductor device (transistor 200 ). Fig. 7A is a plan view of the semiconductor device. FIG. 7B to FIG. 7D is a cross-sectional view of the semiconductor device. Figure 7B It is along Fig. 7A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view along the channel length direction of the transistor 200. Figure 7C It is along Fig. 7A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is also a cross-sectional view along the channel width direction of the transistor 200. Fig.7D It is along Fig. 7A The cross-sectional view of the portion along the dashed line A5-A6 in FIG. 1 is also a cross-sectional view in the channel width direction of the transistor 200. Note that Fig. 7A In the plan view, some components are omitted for clarity. Fig. 8A and Figure 8B An enlarged cross-sectional view of the transistor 200 in the channel length direction is shown.

[0286] Transistor 200 includes a conductor 205 arranged in a manner embedded in an insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, a conductor 242a and a conductor 242b on the oxide semiconductor 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250.

[0287] The oxide semiconductor 230 has a region used as a channel formation region of the transistor 200. In addition, the conductor 260 has a region used as a first gate electrode (also referred to as an upper gate electrode, a top gate electrode) of the transistor 200. The insulator 250 has a region used as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region used as a second gate electrode (also referred to as a lower gate electrode, a bottom gate electrode) of the transistor 200. The insulator 224, the insulator 222, and the insulator 221 all have a region used as a second gate insulator of the transistor 200. The conductor 242a has a region used as one of the source electrode and the drain electrode of the transistor 200. The conductor 242b has a region used as the other of the source electrode and the drain electrode of the transistor 200.

[0288] An insulator 275 is provided on the insulator 271a and the insulator 271b, and an insulator 280 is provided on the insulator 275. An opening that reaches the insulator 222 and the oxide semiconductor 230 is formed in the insulator 280 and the insulator 275, and the opening overlaps with the area between the conductor 242a and the conductor 242b. The insulator 250 and the conductor 260 are arranged inside the openings provided in the insulator 280 and the insulator 275. In addition, an insulator 282 is provided in a manner of contacting the top surface of the insulator 280, the upper end of the insulator 250, and the top surface of the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 214 is provided under the insulator 216 and the conductor 205. In addition, an insulator 212 is provided under the insulator 214. The insulator 212 , the insulator 214 , the insulator 280 , the insulator 282 , the insulator 283 , and the insulator 285 serve as interlayer films.

[0289] Insulator 285, insulator 283, insulator 282, insulator 280, insulator 275, and insulator 271a, an opening is formed to reach conductor 242a, and conductor 240a and insulator 241a are arranged in the opening. Insulator 241a is arranged in contact with the side wall of the opening, and conductor 240a is arranged inside insulator 241a. In addition, insulator 285, insulator 283, insulator 282, insulator 280, insulator 275, and insulator 271b, an opening is formed to reach conductor 242b, and conductor 240b and insulator 241b are arranged in the opening. Insulator 241b is arranged in contact with the side wall of the opening, and conductor 240b is arranged inside insulator 241b. The conductor 240 a and the conductor 240 b are used as through holes for connecting a wiring or the like provided on the transistor 200 to a source or a drain of the transistor 200 .

[0290] Here, the oxide semiconductor 230 corresponds to the oxide semiconductor 30 described in Embodiment 1, and the insulator 224 corresponds to the layer 29 described in Embodiment 1. Therefore, the details of the oxide semiconductor 230 and the insulator 224 can refer to the description of Embodiment 1. In this way, by using the oxide semiconductor 230 of Axial Growth CAAC in the channel formation region of the transistor 200, a transistor with good on-state current, field effect mobility, S value, frequency characteristics, and reliability can be provided.

[0291] In addition, if Fig. 8AAs shown, the oxide semiconductor 230 may include an oxide semiconductor 230a on the insulator 224, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a described in Embodiment 1, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b described in Embodiment 1, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c described in Embodiment 1. Therefore, the details of the oxide semiconductors 230a to 230c can refer to the description of Embodiment 1.

[0292] The oxide semiconductor 230 includes a channel formation region of the transistor 200 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0293] Since the channel formation region has fewer oxygen vacancies or lower impurity concentration than the source region and the drain region, the channel formation region is a high resistance region with low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0294] In addition, due to the large number of oxygen vacancies or the high concentration of impurities such as hydrogen, nitrogen, and metal elements, the source region and the drain region are low-resistance regions with high carrier concentration. That is, the source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentration than the channel formation region.

[0295] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the channel formation region, and it can be, for example, 1×10 -9 cm-3 .

[0296] In the case where the purpose is to reduce the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0297] Therefore, in order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230. In order to reduce the impurity concentration of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element having a concentration of less than 0.1 atomic % can be said to be an impurity.

[0298] In the oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region, but may change continuously in each region. That is, the closer to the channel formation region, the lower the concentration of the metal elements and impurity elements such as hydrogen and nitrogen may be.

[0299] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0300] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V OH. Note that when too much oxygen is supplied to the source region or the drain region, the on-state current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to the source region or the drain region is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the amount of oxygen supplied from the insulator to the oxide semiconductor is too much, it sometimes has a negative impact on the electrical characteristics and reliability of the transistor. Furthermore, there is the following concern: oxygen diffuses into conductors such as gate electrodes, source electrodes, and drain electrodes, and the conductors are oxidized, resulting in a decrease in conductivity.

[0301] Preferably, an insulator having hydrogen barrier properties is first formed near the transistor 200 to reduce the V O H.

[0302] At least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 is preferably used as a hydrogen blocking insulator. In addition, at least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 is preferably used as an impurity blocking insulator. In addition, at least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 is preferably used as an oxygen blocking insulator. Note that all of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 do not necessarily have to be provided. As long as they have sufficient barrier properties against hydrogen, impurities, oxygen, etc., they can be formed by appropriately selecting from insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283. For example, a structure in which insulator 216 and conductor 205 are formed in contact with the top surface of insulator 212 without providing insulator 214 may be adopted.

[0303] Note that in this specification, etc., a blocking insulator refers to an insulator with a barrier property. In this specification, etc., having a barrier property means that the corresponding substance does not diffuse easily (also referred to as the property that the corresponding substance does not easily permeate, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Alternatively, it means that the insulator has the function of capturing or fixing the corresponding substance inside the insulator (also referred to as impurity absorption). In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. -In addition, unless otherwise specified, the impurity recorded as the corresponding substance refers to an impurity in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as the corresponding substance refers to at least one of oxygen atoms, oxygen molecules, etc.

[0304] As an insulator having the function of inhibiting hydrogen diffusion, for example, silicon nitride or silicon oxynitride is preferably used. In addition, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may be used.

[0305] An insulator having a function of suppressing hydrogen diffusion is preferably used as the insulator 212, the insulator 221, the insulator 275, and the insulator 283. For example, silicon nitride having a higher hydrogen barrier property can be used for the insulator 212, the insulator 221, the insulator 275, and the insulator 283.

[0306] As an insulator having the function of capturing or fixing hydrogen, for example, metal oxides such as an oxide containing hafnium, an oxide containing aluminum, an oxide containing aluminum and hafnium (hafnium aluminate), or magnesium oxide are preferably used. The insulator having the function of capturing or fixing hydrogen preferably has an amorphous structure. The above-mentioned metal oxide having an amorphous structure sometimes has the following properties: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the ability of the metal oxide having an amorphous structure to capture or fix hydrogen is high. By adding silicon to the above-mentioned metal oxide, polycrystallization can be suppressed and amorphization can be more easily achieved. Therefore, it is preferred to use a metal oxide (for example, hafnium silicate, aluminum silicate, etc.) to which silicon is added to the above-mentioned metal oxide.

[0307] An insulator having a function of capturing or fixing hydrogen is preferably used as the insulator 214, the insulator 222, and the insulator 282. For example, aluminum oxide may be used as the insulator 214 and the insulator 282. For example, hafnium oxide, which is a high dielectric constant (high-k) material, is preferably used as the insulator 222 used as the second gate insulator.

[0308] In addition, the inorganic insulators cited as the insulator having the function of suppressing the diffusion of hydrogen and the insulator having the function of capturing or fixing hydrogen also have oxygen barrier properties.

[0309] like Fig. 8AAs shown, it is preferable to provide an insulator 212 having a function of suppressing hydrogen diffusion and an insulator 214 having a function of capturing or fixing hydrogen under the transistor 200. By providing the insulator 212 under the transistor 200, it is possible to suppress the diffusion of hydrogen from the lower layer of the transistor 200. In addition, by providing the insulator 214 on the insulator 212, hydrogen included in the insulator 216 and the like can be captured or fixed by the insulator 214. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0310] In addition, if Fig. 8A As shown, an insulator 221 having a function of suppressing hydrogen diffusion and an insulator 222 having a function of capturing or fixing hydrogen are preferably provided at the lower portion of the transistor 200. By providing the insulator 221 at the lower portion of the transistor 200, diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. In addition, by providing the insulator 222 on the insulator 221, hydrogen contained in the insulator 224 or the like can be captured or fixed by the insulator 222. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0311] In addition, if Fig. 8A As shown, the insulator 275 is preferably provided to cover the oxide semiconductor 230, the conductors 242a, the conductors 242b, and the like. By providing the insulator 275 in this way, diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, the conductors 242a, the conductors 242b, and the like can be suppressed.

[0312] In addition, if Fig. 8A As shown, it is preferable to provide an insulator 282 having a function of capturing or fixing hydrogen and an insulator 283 having a function of suppressing the diffusion of hydrogen on the transistor 200. By providing the insulator 283 on the transistor 200, it is possible to suppress the diffusion of hydrogen from the upper layer of the transistor 200. In addition, by providing the insulator 282 under the insulator 283, hydrogen included in the insulator 280 and the like can be captured or fixed by the insulator 282. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0313] In this way, by adopting a structure in which the upper and lower parts of the transistor 200 are surrounded by a hydrogen blocking insulator, it is possible to reduce the diffusion of hydrogen into the oxide semiconductor and reduce the V in the channel formation region. O H. Thus, the electrical characteristics and reliability of the transistor 200 can be improved.

[0314] Furthermore, it is preferable that the insulator 280 contains oxygen that is released by heating. By supplying the oxygen to the oxide semiconductor 230 through the insulator 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0315] In addition, if Fig. 8AAs shown, the insulator 282 may also have a stacked structure of an insulator 282a and an insulator 282b on the insulator 282a.

[0316] At this time, by depositing the insulator 282b by sputtering in an atmosphere containing an oxygen gas, oxygen can be added to the insulator 280. At this time, by depositing the insulator 282b in a state where the insulator 282a is formed, oxygen is added through the insulator 282a, so that the amount of oxygen added to the insulator 280 can be controlled. When the thickness of the insulator 282a is large, the above-mentioned oxygen addition is easily hindered and the amount of oxygen injected into the insulator 280 is reduced. When the thickness of the insulator 282a is small, the above-mentioned oxygen addition is not easily hindered and the amount of oxygen injected into the insulator 280 is increased. For example, by setting the thickness of the insulator 282a to be greater than 1 nm and less than 20 nm, preferably greater than 3 nm and less than 10 nm, an appropriate amount of oxygen can be supplied to the insulator 280.

[0317] In addition, in order to prevent oxygen from being added to the insulator 280 when depositing the insulator 282a, the insulator 282a is preferably deposited using the ALD method. In order to reduce the thickness of the insulator 282a as described above, it is preferably deposited using the ALD method. The ALD method includes a thermal ALD method that uses only thermal energy to react a precursor and a reactant, and a PEALD (Plasma Enhanced ALD) method that uses a reactant excited by plasma.

[0318] The precursor used in the ALD method sometimes contains carbon and the like. Therefore, a film formed by the ALD method sometimes contains more impurities such as carbon than a film formed by other deposition methods. Therefore, the carbon concentration of the insulator 282a is sometimes higher than that of the insulator 282b. In addition, the quantitative determination of impurities can be performed using SIMS, XPS or Auger Electron Spectroscopy (AES).

[0319] For example, when both the insulator 282a and the insulator 282b contain aluminum oxide, the carbon concentration of the insulator 282a may be higher than that of the insulator 282b. In this case, the carbon concentration of the insulator 282a in SIMS analysis is preferably 1×10 18 atoms / cm 3 Above and 1×10 21 atoms / cm 3 Below. Insulator 282a sometimes has 1×10 19 atoms / cm 3 Above and 1×10 21 atoms / cm 3In addition, the carbon concentration of the insulator 282b in SIMS analysis is preferably above the detection limit and 1×10 20 atoms / cm 3 The insulator 282b sometimes has a carbon concentration of 4.46×10 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The following area.

[0320] As described above, the insulator 280 containing oxygen released by heating is subjected to heat treatment, whereby an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 through the insulator 250. In this heat treatment, since the insulator 282 and the insulator 283 having oxygen barrier properties are formed on the insulator 280, the oxygen contained in the insulator 280 can be prevented from excessively diffusing from the insulator 280. In addition, since the insulator 275 having oxygen barrier properties is formed between the insulator 280 and the oxide semiconductor 230, the conductors 242a, and the conductors 242b, the oxygen contained in the insulator 280 can be prevented from excessively diffusing from the insulator 280. In addition, by performing this heat treatment in a state where openings are formed in part of the insulator 280, the insulator 282, and the insulator 283, part of the oxygen contained in the insulator 280 can be diffused outward, thereby adjusting the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230.

[0321] Here, the insulator 250 preferably has a structure that diffuses oxygen from the insulator 280 into the oxide semiconductor 230 and suppresses oxidation of the conductor 242 a , the conductor 242 b , and the conductor 260 .

[0322] like Figure 7B and Figure 7C As shown, the insulator 250 is disposed in an opening formed in the insulator 280 and the insulator 275. In the opening, the insulator 250 is formed in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface and the top surface of the oxide semiconductor 230, the side surface of the conductor 242a, the side surface of the conductor 242b, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the insulator 275, and the side surface of the insulator 280. Fig. 8A As shown in the figure, when the oxide semiconductor 230 includes the oxide semiconductors 230a to 230c, the insulator 250 is in contact with the side surface of the oxide semiconductor 230a, the side surface of the oxide semiconductor 230b, and the top surface and the side surface of the oxide semiconductor 230c. Here, as shown in Embodiment 1, it is preferable to increase the thickness of the oxide semiconductor 230c ( Figure 2AThe oxide semiconductor 230c has a large contact area with the insulator 250, so that the carrier mobility can be improved when the transistor 200 is in the on state.

[0323] Here, if Fig. 8A As shown, the insulator 250 preferably has a stacked-layer structure of an insulator 250 a in contact with the oxide semiconductor 230 , an insulator 250 b on the insulator 250 a , and an insulator 250 c on the insulator 250 b .

[0324] The insulator 250b preferably uses silicon oxide or silicon oxynitride with high insulation withstand voltage. In addition, in order to improve the insulation withstand voltage, the thickness of the insulator 250b can also be made larger than the thickness of the insulator 250a and the insulator 250d. By using the above-mentioned oxide insulator, a high-temperature heat treatment can be performed to diffuse oxygen in the insulator 250b. Therefore, by performing a heat treatment, the oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250b. Note that in this specification, etc., "oxynitride" refers to a material whose oxygen content is greater than the nitrogen content in its composition, and "nitride oxide" refers to a material whose nitrogen content is greater than the oxygen content in its composition. For example, "silicon oxynitride" refers to a material whose oxygen content is greater than the nitrogen content in its composition, and "silicon oxynitride" refers to a material whose nitrogen content is greater than the oxygen content in its composition.

[0325] Furthermore, in order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. For example, an oxygen blocking insulator is preferably provided as the insulators 250a and 250c.

[0326] The insulator 250a preferably has oxygen barrier properties. The insulator 250a is preferably at least less likely to allow oxygen to penetrate than the insulator 250b. The insulator 250a has a region in contact with the side of the conductor 242a and the side of the conductor 242b. When the insulator 250a has oxygen barrier properties, it is possible to suppress the oxidation of the side of the conductor 242a and the conductor 242b and form an oxide film on the side. Therefore, it is possible to suppress the decrease in the on-state current of the transistor 200 or the decrease in the field effect mobility. In addition, by adopting this structure, the amount of oxygen in the insulator 250b absorbed by the conductor 242a and the conductor 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 from the insulator 250b, thereby reducing the oxygen vacancies in the channel formation region of the oxide semiconductor 230.

[0327] In addition, by providing the insulator 250a between the insulator 280 and the insulator 250b and between the insulator 250b and the oxide semiconductor 230, it is possible to suppress excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230, and to supply an appropriate amount of oxygen to the oxide semiconductor 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, so that the normally-off state of the transistor 200 can be prevented from being excessively turned off, thereby improving reliability. In addition, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility caused by excessive oxidation of the source region and the drain region.

[0328] Therefore, the thickness of the insulator 250a is preferably such that diffusion of oxygen from the insulator 280 to the insulator 250b and diffusion of oxygen from the insulator 250b to the oxide semiconductor 230 are not excessively blocked. For example, the thickness of the insulator 250a is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, further preferably 0.5 nm to less than 3.0 nm, and further preferably 0.5 nm to 2.0 nm.

[0329] As described above, it is preferable to appropriately diffuse oxygen from the insulator 280 to the insulator 250b and diffuse oxygen from the insulator 250b to the oxide semiconductor 230, and to suppress the diffusion of oxygen from the insulator 250b to the conductors 242a and 242b as much as possible. Here, in the semiconductor device according to the present embodiment, the contact area between the insulator 250a and the conductor 242a and the contact area between the insulator 250a and the conductor 242b are much smaller than the contact area between the insulator 250a and the oxide semiconductor 230. That is, it can be inferred that the amount of oxygen diffused from the insulator 250b to the conductors 242a and 242b through the insulator 250a is less than the amount of oxygen diffused from the insulator 250b to the oxide semiconductor 230 through the insulator 250a. Therefore, by controlling the amount of oxygen included in the insulator 280 so that an appropriate amount of oxygen is supplied from the insulator 280 to the insulator 250 b and the oxide semiconductor 230 , oxidation of the conductors 242 a and 242 b can be reduced.

[0330] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Therefore, the V O H makes the channel formation region i-type or substantially i-type.

[0331] In addition, the insulator 250a preferably uses a high dielectric constant (high-k) material. As an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0332] Therefore, as the insulator 250a, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Since aluminum oxide can be easily deposited as an amorphous film by the ALD method, it is further preferable to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. Aluminum oxide has a function of capturing or fixing hydrogen and has oxygen barrier properties, so it can be appropriately used as the insulator 250a.

[0333] The insulator 250c also preferably has oxygen barrier properties. The insulator 250c is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide semiconductor 230 into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide semiconductor 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide semiconductor 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250c is preferably at least less likely to allow oxygen to penetrate than the insulator 250b. In addition, the insulator 250c preferably has a function of suppressing the diffusion of hydrogen. Thus, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide semiconductor 230. For example, a silicon nitride film is preferably used as the insulator 250c.

[0334] In addition, if Figure 8B As shown, a structure in which an insulator 250d is provided on the insulator 250b may be adopted. In this case, an insulator that can be used as the insulator 250a may be provided as the insulator 250d. For example, hafnium oxide may be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like may be more effectively captured and fixed. In addition, a structure in which the insulator 250a, the insulator 250b and the insulator 250d are provided instead of the insulator 250c may be adopted.

[0335] By adopting the above structure, the channel forming region can be i-type or substantially i-type and the source region and the drain region can be n-type, and a semiconductor device with good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0336] Insulators 250a to 250d are used as part of the first gate insulator. Insulators 250a to 250d are arranged in an opening formed in insulator 280 together with conductor 260. In order to achieve miniaturization of transistor 200, the thickness of insulator 250a, insulator 250c and insulator 250d is preferably small. The thickness of insulator 250a, insulator 250c and insulator 250d is preferably 0.1nm or more and 20nm or less, more preferably 0.1nm or more and 10nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a part of insulator 250a, insulator 250c and insulator 250d has a region of the above-mentioned thickness.

[0337] In order to reduce the thickness of the insulators 250a to 250d as described above, it is preferable to deposit them using the ALD method. In addition, in order to form the insulators 250a to 250d with high coverage in the opening of the insulator 280 and the like, it is preferable to deposit the insulators 250a to 250d using the ALD method.

[0338] Note that in the above description, the insulator 250 has a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0339] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide semiconductor 230 and the conductor 260. As the conductor 205, the conductive material described in <<Conductor>> can be used. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Fig. 7A and Figure 7CAs shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0340] like Fig. 8A As shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is consistent or substantially consistent with the height of the top surface of the insulator 216.

[0341] Here, as the conductor 205a, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Alternatively, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0342] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide semiconductor 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting oxygen diffusion as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having a function of inhibiting oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0343] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0344] The conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0345] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0346] Note that Fig. 8A , a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductor 205a may have a two-layer structure of tantalum nitride and titanium nitride on the tantalum nitride, and the conductor 205b including tungsten is provided on the conductor 205a. By adopting such a structure, it is possible to suppress the diffusion of impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 into the conductor 205.

[0347] Insulator 224 , insulator 221 , and insulator 222 corresponding to layer 29 are used as a second gate insulator.

[0348] As the insulator 224 in contact with the oxide semiconductor 230, an insulating material described in <<Insulator>> can be used. The insulator 224 preferably contains silicon oxide or silicon oxynitride, for example. Thus, oxygen can be supplied from the insulator 224 to the oxide semiconductor 230 to reduce oxygen vacancies. In addition, the insulator 224 may also have a stacked structure of more than two layers. At this time, it is not limited to a stacked structure composed of the same material, and a stacked structure formed of different materials may also be used.

[0349] In addition, the insulator 224 is preferably processed into an island shape in the same manner as the oxide semiconductor 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 includes an insulator 224 of substantially the same size. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 in each transistor 200 is substantially equal. Thus, non-uniformity in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.

[0350] Note that the insulator 224 does not necessarily have to be processed into an island shape. 9A to 9D As shown, the insulator 224 may also be partially formed with an opening instead of an island shape. 9A to 9D Corresponding to 7A to 7D , except for the shape of the insulator 224. 7A to 7D same.

[0351] exist 9A to 9DIn the insulator 224 shown, the thickness of the region not overlapping with the oxide semiconductor 230 is smaller than the thickness of the region overlapping with the oxide semiconductor 230. In addition, an opening is formed in the region not overlapping with the oxide semiconductor 230 and overlapping with the insulator 250. When a plurality of transistors are provided on the same substrate, by forming the insulator 224 in this way, the oxide semiconductor 230 of each transistor is formed on the same insulator 224. Thus, the unevenness of the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 of each transistor can be reduced. Therefore, the unevenness of the electrical characteristics of each transistor can be reduced.

[0352] Note that 9A to 9D In the illustrated insulator 224 , an opening is formed in a region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250 , but the opening may not be provided.

[0353] As the conductor 242a, the conductor 242b, and the conductor 260, the conductive materials described in <<Conductor>> can be used. In particular, as the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thereby, the decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0354] As the conductor 242a and the conductor 242b, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. For example, tantalum nitride can be used as the conductor 242a and the conductor 242b. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0355] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a or the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or the conductor 242b.

[0356] In addition, the conductor 242a and the conductor 242b may have a stacked structure. In this case, the above-mentioned conductive material may be used as the lower layer of the conductor 242a and the conductor 242b, and a conductive material with higher conductivity may be used as the upper layer of the conductor 242a and the conductor 242b. For example, tantalum nitride may be used as the lower layer, and tungsten may be used as the upper layer.

[0357] Insulators 271a and 271b are inorganic insulators used as etching stop layers to protect conductors 242a and 242b during processing of conductors 242a and 242b. In addition, since insulators 271a and 271b are in contact with conductors 242a and 242b, inorganic insulators that are not likely to oxidize conductors 242a and 242b are preferably used. Fig. 8A As shown, it is preferred that the insulator 271a has a stacked structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a stacked structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 preferably use a nitride insulator that can be used for the insulator 250c so as not to oxidize the conductors 242a2 and 242b2. In addition, in order to function as an etching stop layer, the insulators 271a2 and 271b2 preferably use an oxide insulator that can be used for the insulator 250b.

[0358] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b and a part of the insulator 275. In addition, the insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride can be used as the insulator 271a1 and the insulator 271b1, and silicon oxide can be used as the insulator 271a2 and the insulator 271b2.

[0359] The insulators that will become insulators 271a and insulators 271b are used as masks for the conductors that will become conductors 242a and conductors 242b, so that Fig.7D The conductor 242a and the conductor 242b shown do not have a curved surface between the side surface and the top surface. As a result, the end portion where the side surface of the conductor 242a and the conductor 242b intersects with the top surface has an angular shape. When the end portion where the side surface of the conductor 242a and the conductor 242b intersects with the top surface has an angular shape, the cross-sectional area of ​​the conductor 242a and the conductor 242b is increased compared to the case where the end portion has a curved surface. Furthermore, by using a nitride insulator that is not easy to oxidize metal as the insulator 271a1 and the insulator 271b1, it is possible to prevent the conductor 242a and the conductor 242b from being excessively oxidized. As a result, the resistance of the conductor 242a and the conductor 242b is reduced, so the on-state current of the transistor can be increased.

[0360] like Figure 7B and Figure 7C As shown, the conductor 260 is arranged in the opening formed in the insulator 280 and the insulator 275. The conductor 260 is provided in the opening so as to cover the top surface of the insulator 222, the side surface of the insulator 224, and the side surface and the top surface of the oxide semiconductor 230 via the insulator 250. In addition, the top surface of the conductor 260 is arranged so as to be consistent or substantially consistent with the height of the upper end of the insulator 250 and the top surface of the insulator 280.

[0361] In the above-mentioned opening where the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. The tapered side wall can improve the coverage of the insulator 250 and the like provided in the opening of the insulator 280, thereby reducing defects such as voids.

[0362] The conductor 260 is used as a first gate electrode of the transistor 200. Fig. 7A and Figure 7C As shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0363] In the case of adopting the above structure, if Figure 7C As shown, when the transistor 200 is cross-sectionally viewed in the channel width direction, a curved surface may be provided between the side surface of the oxide semiconductor 230 and the top surface of the oxide semiconductor 230. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0364] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide semiconductor 230 in the region overlapping the conductor 242a and the conductor 242b or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 to the oxide semiconductor 230 can be improved.

[0365] In this specification, etc., a transistor structure in which a channel forming region is surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In addition, in this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is configured in a manner that surrounds at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is not prone to short channel effects can be realized.

[0366] By adopting the above-mentioned S-channel structure as the transistor 200, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is essentially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at the interface or near the interface between the oxide semiconductor 230 and the gate insulator can be regarded as the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0367] This embodiment adopts a structure in which the insulator 224 is set to an island shape. Figure 7CAs shown, at least a portion of the bottom surface of the conductor 260 may be disposed below the bottom surface of the oxide semiconductor 230. Thus, the conductor 260 may be disposed opposite to the top surface and the side surface of the oxide semiconductor 230, so that the electric field of the conductor 260 may act on the top surface and the side surface of the oxide semiconductor 230. In this way, by adopting a structure in which the insulator 224 is disposed in an island shape, the transistor 200 may have an S-channel structure.

[0368] Note that as Figure 7C The transistor 200 shown is an S-channel structure transistor, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, as a structure of a transistor that can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure can also be used.

[0369] like Fig. 8A As shown, the conductor 260 preferably has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged in a manner to surround the bottom surface and side surfaces of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion.

[0370] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0371] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0372] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0373] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a and the conductor 242b without alignment.

[0374] The insulator 216, the insulator 280, and the insulator 285 preferably have a lower dielectric constant than the insulator 222. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0375] For example, the insulator 216, the insulator 280, and the insulator 285 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores.

[0376] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, silicon oxide, silicon oxynitride, silicon oxide having pores and the like are preferred because they easily form a region containing oxygen released by heating.

[0377] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0378] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0379] The conductive materials described in <<Conductive Material>> can be used as the conductive material 240a and the conductive material 240b. For example, the conductive material 240a and the conductive material 240b preferably uses a conductive material containing tungsten, copper, or aluminum as a main component. The conductive material 240a and the conductive material 240b may have a stacked structure.

[0380] For example, Fig. 8A As shown, the conductor 240a and the conductor 240b may also have a two-layer stacked structure. The conductor 240a includes a conductor 240a1 formed along the opening and a conductor 240a2 formed inside the conductor 240a1. In addition, the conductor 240b includes a conductor 240b1 formed along the opening and a conductor 240b2 formed inside the conductor 240b1.

[0381] As with the conductor 205a, as the conductor 240a1 and the conductor 240b1, a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, a single layer or a stack of conductive materials having a function of inhibiting the penetration of impurities such as water and hydrogen can also be used. By providing the conductor 240a1 and the conductor 240b1, impurities such as water and hydrogen can be inhibited from mixing into the oxide semiconductor 230 through the conductor 240a2 and the conductor 240b2. In addition, the conductor 240a2 and the conductor 240b2 can use the conductive materials that can be used for the conductor 240a and the conductor 240b.

[0382] In addition, if Figure 7B As shown in FIG. 2 , the top surfaces of the conductors 240a and 240b may be formed in a manner that is aligned or substantially aligned with the top surface of the insulator 285. Fig. 8A As shown, the lower portion of the conductor 240a is sometimes formed in a manner embedded in the conductor 242a. Similarly, the lower portion of the conductor 240b is sometimes formed in a manner embedded in the conductor 242b.

[0383] As the insulator 241a and the insulator 241b, a blocking insulator that can be used for the insulator 275 or the like can be used. For example, as the insulator 241a and the insulator 241b, silicon nitride can be used. The insulator 241a and the insulator 241b are arranged in a manner in contact with the insulator 285, the insulator 283, the insulator 282, the insulator 275, the insulator 271a, and the insulator 271b. Thus, impurities such as water and hydrogen contained in the insulator 280 or the like can be suppressed from mixing into the oxide semiconductor 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is preferred because it has a high hydrogen barrier property. In addition, it is possible to prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0384] Alternatively, the insulator 241a and the insulator 241b may have a stacked structure. In this case, an oxygen blocking insulator and a hydrogen blocking insulator are preferably used in combination as the first insulator in contact with the side wall of the opening such as the insulator 280 and the second insulator inside the first insulator.

[0385] <Deformation example>

[0386] exist Figure 7B In the example, the insulator 250 is in contact with the side surface of the insulator 280 in the opening provided in the insulator 280, but the present invention is not limited to this structure. For example, an insulator may be provided between the insulator 250 and the insulator 280 in the opening.

[0387] Reference FIG. 10A to FIG. 11BA modified example of the semiconductor device described in <Structural example of semiconductor device> is described. FIG. 10A to FIG. 10D are a plan view and a cross-sectional view of a semiconductor device including a transistor 200, corresponding to 7A to 7D In addition, Fig.11A and Fig. 11B is an enlarged cross-sectional view of the channel length direction of the transistor 200, corresponding to Fig. 8A part of Figure 8B Enlarged cross-section shown.

[0388] FIG. 10A to FIG. 10D The transistor 200 shown is 7A to 7D The transistor 200 shown in FIG. FIG. 10A to FIG. 10D The transistor 200 shown includes an insulator 255, which is similar to 7A to 7D The transistor 200 shown is mainly different. Hereinafter, the parts different from the above-mentioned "Structural Example of Semiconductor Device" will be mainly described, and the above-mentioned description will be referred to for the overlapping parts, and the description may be omitted.

[0389] In addition, FIG. 10A to FIG. 10D , the conductor 242a and the conductor 242b both have a two-layer structure. The conductor 242a has a laminated structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1. The conductor 242b has a laminated structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 correspond to the lower layers of the conductors 242a and 242b, and the conductors 242a2 and 242b2 correspond to the upper layers of the conductors 242a and 242b.

[0390] like Fig. 10B and Fig. 10C As shown, the insulator 255 is arranged inside the opening formed in the insulator 280, and is in contact with the side surface of the insulator 280 in the opening, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222. In other words, it can also be said that the insulator 255 is formed in a side wall shape so as to be in contact with the side wall of the opening formed in the insulator 280. Here, the side wall of the opening corresponds to, for example, the side surface of the insulator 280 in the opening.

[0391] In addition, the insulator 250 is in contact with the side surface of the insulator 255 .

[0392] The insulator 255 preferably has an oxygen barrier property. When the insulator 255 has an oxygen barrier property, oxidation of the side surfaces of the conductors 242a and 242b and formation of an oxide film on the side surfaces can be suppressed. Therefore, a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility can be suppressed.

[0393] The opening provided in the insulator 280 overlaps with the area between the conductor 242a2 and the conductor 242b2. When viewed from above, the side surface of the insulator 280 in the above-mentioned opening is aligned with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. In addition, a portion of the conductor 242a1 and the conductor 242b1 is formed to protrude toward the inner side of the above-mentioned opening. In other words, in the conductor 242a1, the portion on the top surface of which the insulator 255 is formed is formed in a manner protruding toward the conductor 260 side more than the conductor 242a2. Similarly, in the conductor 242b1, the portion on the top surface of which the insulator 255 is formed is formed in a manner protruding toward the conductor 260 side more than the conductor 242b2.

[0394] Here, a portion of the top surface of the conductor 242a1 is in contact with the conductor 242a2, and a portion of the top surface of the conductor 242b1 is in contact with the conductor 242b2. Therefore, the insulator 255 is in contact with another portion of the top surface of the conductor 242a1, another portion of the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 inside the above-mentioned opening. In addition, the insulator 250 is in contact with the top surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.

[0395] The insulator 255 is formed into a side wall shape by anisotropic etching so as to contact the side wall of the opening provided in the insulator 280. The insulator 255 is formed so as to contact the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has a function of protecting the conductors 242a2 and 242b2.

[0396] In addition, when dividing into the conductor 242a1 and the conductor 242b1, the insulator 255 is used as a mask. Fig.11A As shown, when the transistor 200 is viewed in cross section, the side ends of the insulator 255 are aligned with the side ends of the conductor 242a1 and the side ends of the conductor 242b1.

[0397] After the conductor 242a1 and the conductor 242b1 are separated and before the insulator 250 is deposited, heat treatment is preferably performed in an oxygen-containing atmosphere. At this time, since the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, the conductor 242a2 and the conductor 242b2 can be prevented from being excessively oxidized. When the conductor 242a1 and the conductor 242b1 are separated and microwave treatment is performed, the formation of an oxide film on the side surface of the conductor 242a and the conductor 242b can also be suppressed.

[0398] The insulator 255, the insulator 250, and the conductor 260 are arranged in the opening portion provided in the insulator 280 in accordance with the shape of the opening portion. Therefore, the insulator 255 is provided so as to cover the side wall of the opening portion, the insulator 250 is provided so as to cover the bottom of the opening portion and the insulator 255, and the conductor 260 is provided so as to be embedded in the recess of the insulator 250.

[0399] Note that, similar to the above-mentioned <Structural example of semiconductor device>, the insulator 250 may also have a stacked structure. Fig.11A As shown, the insulator 250 may also have a three-layer structure of an insulator 250a, an insulator 250b, and an insulator 250c. Fig. 11B As shown, the insulator 250 may also have a four-layer structure of an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d.

[0400] In addition, the thickness of the insulator 255 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and further preferably 0.5 nm or more and 3 nm or less. When the insulator 255 has the above thickness, the conductor 242a2 and the conductor 242b2 can be suppressed from being excessively oxidized. Note that the insulator 255 only needs to have a region with a thickness of the above value in at least a portion thereof. In addition, since the insulator 255 is arranged in a manner in contact with the side wall of the opening formed in the insulator 280, it is preferably deposited using an ALD method with high coverage. When the thickness of the insulator 255 is too large, the deposition time of the insulator 255 using the ALD method is long, resulting in a decrease in productivity, so it is preferred to set the thickness of the insulator 255 approximately within the above range. In addition, as the thickness of the insulator 255, it is preferred to use a thickness that does not excessively block the diffusion of excess oxygen from the insulator 280 to the insulator 250b and the diffusion of excess oxygen from the insulator 250b to the oxide semiconductor 230.

[0401] like Fig.11AAs shown, when the transistor 200 is cross-sectionally viewed in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. Specifically, the difference between the distance L1 and the distance L2 is consistent with twice the thickness of the insulator 255. In other words, the distance L1 is consistent with the distance L2 plus twice the thickness of the insulator 255. Here, the thickness of the insulator 255 refers to the width of at least a portion of the insulator 255 in the A1-A2 direction. By adopting this structure, the distance between the source and the drain can be further shortened and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0402] In addition, the insulator 255 may also have a stacked structure with more than two layers. In this case, at least one layer is preferably the above-mentioned inorganic insulator that is not easily oxidized. For example, the above-mentioned inorganic insulator that is not easily oxidized is used as the first insulator of the insulator 255, and the second insulator on the first insulator of the insulator 255 can be an insulator that can be used for the insulator 250b (for example, silicon oxide, etc.). The dielectric constant of the second insulator of the insulator 255 is preferably lower than that of the first insulator of the insulator 255. In this way, by increasing the thickness by using a two-layer structure as the insulator 255, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased to reduce the parasitic capacitance.

[0403] <Materials Constituting Semiconductor Devices>

[0404] The constituent materials that can be used for the semiconductor device are described below. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked-layer structure.

[0405] <<Substrate>>

[0406] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Alternatively, a substrate having one or more elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0407] <<Insulator>>

[0408] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0409] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0410] Examples of insulators having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0411] Examples of insulators having a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resins.

[0412] In addition, by surrounding a transistor using a metal oxide with an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0413] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, when a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230 is adopted, oxygen vacancies contained in the oxide semiconductor 230 can be filled.

[0414] <<Conductor>>

[0415] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be cited. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that absorb oxygen and maintain conductivity, so they are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0416] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0417] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0418] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0419] <Example of Method for Manufacturing Semiconductor Device>

[0420] Reference FIG. 12A to FIG. 19D An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. 7A to 7D The case of the semiconductor device shown in FIG. 1 is described as an example.

[0421] FIG. 12A to FIG. 15D as well as FIG. 17A to FIG. 19D A in each drawing is a plan view. FIG. 12A to FIG. 15D as well as FIG. 17A to FIG. 19D B in each drawing is a cross-sectional view of a portion along the dashed line A1 - A2 in each drawing A, and is also a cross-sectional view in the channel length direction of the transistor 200 . FIG. 12A to FIG. 15D as well as FIG. 17A to FIG. 19D C in each drawing is a cross-sectional view of a portion along the dashed line A3 - A4 in each drawing A, and is also a cross-sectional view in the channel width direction of the transistor 200 . FIG. 12A to FIG. 15D as well as FIG. 17A to FIG. 19D D in each figure is a cross-sectional view of a portion along the dashed line A5-A6 in each figure A, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that FIG. 12A to FIG. 15D as well as FIG. 17A to FIG. 19D In the plan view of A in each of the drawings, some components are omitted for clarity. FIG. 16A1 to FIG. 16D1 is corresponding to Figure 7B is a cross-sectional view of a portion of the transistor 200, and is also a cross-sectional view of the channel length direction of the transistor 200. FIG. 16A2 to FIG. 16D2 is corresponding to Figure 7C , which is also a cross-sectional view of a portion of the transistor 200 in the channel width direction.

[0422] Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be appropriately deposited using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0423] First, a substrate (not shown) is prepared, an insulator 212 is deposited on the substrate, and an insulator 214 is deposited on the insulator 212 (see FIG. 12A to FIG. 12D ). The above-mentioned insulating materials can be used for the insulator 212 and the insulator 214. For example, the insulator 212 and the insulator 214 can be deposited by sputtering, CVD, MBE, PLD, or ALD. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 and the insulator 214 can be reduced, so it is preferred.

[0424] In this embodiment, silicon nitride is deposited by sputtering as the insulator 212, and aluminum oxide is deposited by sputtering as the insulator 214. In this way, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 212, diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 214, hydrogen contained in the insulator 216 and the like can be captured or fixed by the insulator 214. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0425] In addition, it is preferable to perform heat treatment to reduce water and hydrogen adsorbed to the substrate (including circuit elements and interlayer films formed on the substrate) before depositing the insulator 212. In this embodiment, the temperature of the heat treatment is set to 400°C.

[0426] Next, an insulator 216 is deposited on the insulator 214. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen for a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, an MBE method, a PLD method, or an ALD method may be used as appropriate. In this embodiment, silicon oxide is deposited by a sputtering method as the insulator 216.

[0427] The insulator 212, the insulator 214, and the insulator 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 212, the insulator 214, and the insulator 216 can be deposited while reducing hydrogen in the film, and the mixing of hydrogen into the film between each deposition step can be reduced.

[0428] Next, an opening that reaches the insulator 214 is formed in the insulator 216. The opening is formed in the region where the conductor 205 is to be formed. When forming the opening, wet etching can be used, but dry etching is preferred for micro-machining. As the insulator 214, it is preferable to select an insulator that serves as an etching stopper film when etching the insulator 216. For example, when silicon oxide or silicon oxynitride is used as the insulator 216, it is preferable to use silicon nitride, aluminum oxide, hafnium oxide, or the like as the insulator 214.

[0429] After the opening is formed, a conductive film to be the conductor 205 is deposited, and a CMP process is performed until the insulator 216 is exposed to remove a portion of the conductive film to be the conductor 205. Thus, the conductor 205 embedded in the insulator 216 can be formed (see FIG. 12A to FIG. 12D ).

[0430] Here, the conductive film to be the conductor 205 can be deposited using the above-mentioned conductive materials by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a tantalum nitride film, a titanium nitride film, and a tungsten film can be deposited by stacking them by CVD. Fig. 8A As shown in FIG. 1 , the conductor 205 may have a stacked structure of a conductor 205a formed by stacking titanium nitride on tantalum nitride and a conductor 205b formed by stacking tungsten.

[0431] Next, an insulator 221 is deposited on the insulator 216 and the conductor 205 (see FIG. 12A to FIG. 12D ).

[0432] The insulator 221 may be any of the above-mentioned insulators that have barrier properties to oxygen, hydrogen, and water. The insulator 221 may be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is deposited by PEALD as the insulator 221 .

[0433] Next, an insulator 222 is deposited on the insulator 221 (see FIG. 12A to FIG. 12D ).

[0434] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the surrounding structure of the transistor can be suppressed from diffusing through the insulator 222 to the inside of the transistor, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0435] The insulator 222 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, hafnium oxide is deposited as the insulator 222 by thermal ALD.

[0436] In this embodiment, silicon nitride is deposited by a PEALD method as the insulator 221, and hafnium oxide is deposited by a thermal ALD method as the insulator 222. In this way, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 221, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide having a function of capturing or fixing hydrogen as the insulator 222, hydrogen in the insulator 224 and the like can be captured or fixed by the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0437] Next, an insulating film 224f is deposited on the insulator 222 (see FIG. 12A to FIG. 12D ). As the insulating film 224f, an insulator corresponding to the above-described insulator 224 can be used. By forming the insulating film 224f in this way, the insulating film 224f is formed in parallel or substantially parallel to the substrate surface.

[0438] The insulating film 224f can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is deposited by a sputtering method as the insulating film 224f. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. The insulating film 224f is in contact with the oxide semiconductor 230 in a subsequent process, so it is preferable that the hydrogen concentration is reduced as described above.

[0439] Next, an oxide semiconductor film 230f is deposited on the insulating film 224f (see FIG. 12A to FIG. 12D ). The oxide semiconductor film 230f can be deposited using the same method as the deposition of the oxide semiconductor 30 described in Embodiment 1. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed parallel to or substantially parallel to the substrate surface.

[0440] For example, Fig. 8AAs shown, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, the films that will become the oxide semiconductors 230a and 230c can be deposited by the ALD method, and the film that will become the oxide semiconductor 230b can be deposited by the sputtering method. Specifically, the film that will become the oxide semiconductor 230a can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or a composition thereof and a thickness of 5nm. Alternatively, indium oxide can also be used for the film that will become the oxide semiconductor 230a. In addition, the film that will become the oxide semiconductor 230b can be deposited in a manner having a thickness of 5nm using an oxide target having a composition of In:Ga:Zn=1:1:1.2 [atomic ratio] or a composition thereof. In addition, the film that will become the oxide semiconductor 230c can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or a composition thereof and a thickness of 10nm. Alternatively, indium oxide can also be used for the film that will become the oxide semiconductor 230c.

[0441] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230 f is not polycrystallized. The heat treatment of the oxide semiconductor film 230 f can be performed using the same method as the heat treatment of the oxide semiconductor 30 described in Embodiment 1.

[0442] For example, as the heat treatment, a treatment may be performed at a temperature of 450° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1.

[0443] By depositing the oxide semiconductor 230 by the above method and performing a heat treatment, the oxide semiconductor 230 can be made into an Axial Growth CAAC. Thus, the on-state current, S value, field effect mobility, and frequency characteristics of the transistor 200 can be improved, and a semiconductor device with good electrical characteristics can be provided. In addition, a semiconductor device with high reliability can be provided.

[0444] The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may also be performed in a nitrogen gas or inert gas atmosphere, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been separated.

[0445] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the water content in the gas used in the above-mentioned heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide semiconductor film 230f and the like as much as possible. In addition, the heat treatment before this step and the heat treatment after this step can also use a highly purified gas.

[0446] By such a heat treatment containing an oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor film 230f is improved, and a denser structure with a higher density can be achieved. Therefore, the crystallized area in the oxide semiconductor film 230f can be increased, and the in-plane unevenness of the crystallized area in the oxide semiconductor film 230f can be reduced. Therefore, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0447] In addition, by performing the heat treatment, oxygen can be supplied to the oxide semiconductor film 230 f and oxygen vacancies in the oxide semiconductor film 230 f can be reduced. Thus, the reliability of the transistor 200 can be improved.

[0448] In addition, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f moves to the insulator 222 and is absorbed by the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentration in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f decreases. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment.

[0449] In particular, the insulating film 224f (later insulator 224) is used as a second gate insulator of the transistor 200, and the oxide semiconductor film 230f (later oxide semiconductor 230) is used as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f and the oxide semiconductor film 230f with reduced hydrogen concentration has excellent reliability and is therefore preferred.

[0450] Next, a conductive film 242f is deposited on the oxide semiconductor film 230f (see FIG. 12A to FIG. 12D). A conductor corresponding to the above-mentioned conductor 242a and conductor 242b may be used as the conductive film 242f. After the oxide semiconductor film 230f is deposited, the conductive film 242f is deposited on and in contact with the oxide semiconductor film 230f without an etching process, so that the top surface of the oxide semiconductor film 230f can be protected by the conductive film 242f. Thus, since the diffusion of impurities into the oxide semiconductor 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0451] The conductive film 242f can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0452] In this embodiment, tantalum nitride is deposited as the conductive film 242f by sputtering. In addition, heat treatment may be performed before depositing the conductive film 242f. The heat treatment may also be performed under reduced pressure, and the conductive film 242f is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The temperature of the heat treatment is preferably above 100°C and below 400°C.

[0453] Next, an insulating film 271f is deposited on the conductive film 242f (see FIG. 12A to FIG. 12D ). The insulating film 271f can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 271f preferably uses an insulating film having a function of inhibiting the permeation of oxygen. For example, as the insulating film 271f, a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film can be deposited by sputtering. By adopting such a structure, the insulator 271a (insulator 271b) can have a stacked structure of an insulator 271a1 (insulator 271b1) made of silicon nitride and an insulator 271a2 (insulator 271b2) made of silicon oxide.

[0454] Here, when a laminated film is used as the insulating film 271f, the deposition is performed continuously without being exposed to the atmosphere. By performing the deposition without being exposed to the atmosphere, the vicinity of the interface of the laminated film of the insulating film 271f can be kept clean. In addition, it is more preferable to continuously deposit the conductive film 242f to the insulating film 271f without being exposed to the atmosphere.

[0455] In addition, heat treatment may be performed before the insulating film 271f is deposited. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed, and the moisture concentration and hydrogen concentration in the conductive film 242f can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0456] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into island shapes by photolithography to form the insulator 224, the oxide semiconductor 230, the conductive film 242A, and the insulator 271A (see FIG. 13A to FIG. 13D ).

[0457] The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. In addition, the processing of the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f can be performed under different conditions.

[0458] Here, it is preferred that the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are processed into an island shape at one time. At this time, the side end of the conductor 242A is preferably aligned or roughly aligned with the side end of the oxide semiconductor 230. Furthermore, the side end of the insulator 224 is preferably aligned or roughly aligned with the side end of the oxide semiconductor 230. In addition, the side end of the insulator 271A is preferably aligned or roughly aligned with the side end of the conductor 242A. By adopting the above structure, the number of steps of a semiconductor device according to one embodiment of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with good productivity can be provided.

[0459] In addition, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are formed so that at least a portion thereof overlaps with the conductor 205. In addition, the insulator 222 is exposed in a region that does not overlap with the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A. However, the present invention is not limited to this, and a structure in which the insulator 224 remains on the insulator 222 in a region that does not overlap with the oxide semiconductor 230 may be employed. In this case, 9A to 9D As in the transistor 200 of FIG. 1 , the insulator 224 has a shape in which an opening is partially formed, rather than an island shape.

[0460] like FIG. 13B to FIG. 13D As shown, the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may also have a tapered shape. The taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be, for example, 60° or more and less than 90°. In this way, when the side surfaces have a tapered shape, the coverage of the insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0461] The present invention is not limited to this, and the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be perpendicular or substantially perpendicular to the top surface of the insulator 222. With such a structure, a small area and high density can be achieved when a plurality of transistors are provided.

[0462] Note that in lithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. In addition, when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0463] The resist mask that is unnecessary after processing can be removed by dry etching treatment such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0464] Furthermore, a hard mask made of an insulator or a conductor can also be used under the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material can be formed on the insulating film 271f and a resist mask can be formed thereon, and then the hard mask material can be etched to form a hard mask of a desired shape. For example, tungsten can also be used as a hard mask material. The etching of the insulating film 271f and the like can be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask sometimes disappears during etching. The hard mask can also be removed by etching after etching the oxide semiconductor film 230f and the like. On the other hand, when the hard mask material does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

[0465] In addition, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be deposited between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, the adhesion between the workpiece and the resist mask can be improved, thereby improving the durability of the mask pattern. For example, a SOC film, a SOG film, and a resist mask may be deposited sequentially on the workpiece to perform lithography.

[0466] As an etching gas for dry etching treatment, an etching gas containing halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine and bromine can be used. As an etching gas, for example, one or a mixed gas of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas and BBr3 gas can be used. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas or hydrocarbon gas can be appropriately added to the above-mentioned etching gas. In addition, depending on the object to be processed by dry etching treatment, a gas containing hydrocarbon gas or hydrogen gas but not halogen gas can also be used as an etching gas. As hydrocarbons used for etching gas, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2) and propyne (C3H4) One or more. The etching conditions can be appropriately set according to the etching object.

[0467] In addition, as a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. In addition, a structure in which a plurality of different high-frequency voltages are applied to the parallel plate electrodes can be adopted. This CCP etching device is called a dual-frequency capacitively coupled plasma (DF-CCP: Dual Frequency Capacitively Coupled Plasma) etching device. The DF-CCP etching device can adopt a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used. The etching device can be appropriately set according to the etching object. Note that in the above-mentioned dry etching apparatus, a high-frequency voltage is applied to an electrode on one side of the substrate to generate a self-bias potential, so that reactive ion etching can be performed. In reactive ion etching, ion species in plasma are accelerated to collide with the workpiece to perform etching, so highly anisotropic etching processing can be performed.

[0468] In addition, in the above-mentioned etching process, the insulator 271A can also be used as an etching stop layer to protect the conductor 242A. For example, when a metal hard mask is formed on the insulator 271A in the above-mentioned etching process, it is sometimes difficult to obtain an etching selectivity ratio with the conductor 242A when the hard mask is removed. However, by forming the insulator 271A on the conductor 242A, the insulator 271A can be used as an etching stop layer to protect the conductor 242A in the etching process of removing the hard mask. As a result, the formation of a curved surface between the side surface and the top surface of the conductor 242A can be prevented, so that Fig.7D As shown, the ends where the side and top surfaces of the conductors 242a and 242b formed later intersect are angular. When the ends where the side and top surfaces of the conductor 242A intersect are angular, the cross-sectional area of ​​the conductor 242A is increased compared to the case where the ends have a curved surface. Furthermore, by using a nitride insulator that does not easily oxidize metal as the insulator 271A, the conductor 242A can be prevented from being excessively oxidized. As a result, the resistance of the conductors 242a and 242b is reduced, so the on-state current of the transistor can be increased.

[0469] In addition, by processing the insulator 224 into an island shape, the insulator 275 can be provided in a manner in contact with the side surface of the insulator 224 and the top surface of the insulator 222 in the process described later. That is, the insulator 224 can be separated from the insulator 280 by the insulator 275. With such a structure, it is possible to prevent excessive impurities such as oxygen and hydrogen from being mixed into the oxide semiconductor 230 through the insulator 224 from the insulator 280.

[0470] Next, an insulator 275 is deposited to cover the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A, and an insulator 280 is deposited on the insulator 275 (see FIG. 14A to FIG. 14D ). As the insulator 275 and the insulator 280, the above-mentioned insulating materials can be used.

[0471] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222 .

[0472] As insulator 280, it is preferable to form an insulator with a flat top surface by forming an insulating film to be insulator 280 and then subjecting the insulating film to CMP. Alternatively, silicon nitride may be deposited on insulator 280 by, for example, sputtering and then subjected to CMP until it reaches insulator 280.

[0473] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0474] The insulator 275 preferably uses an insulator that has a function of inhibiting oxygen transmission. For example, silicon nitride is preferably deposited by the PEALD method as the insulator 275. In addition, aluminum oxide may be deposited by the sputtering method and silicon nitride may be deposited thereon by the PEALD method as the insulator 275. When the insulator 275 has the above structure, the function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0475] In this manner, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275 having a function of suppressing oxygen diffusion. Thus, direct diffusion of oxygen from the insulator 280 or the like into the oxide semiconductor 230 and the conductor 242A in a subsequent step can be suppressed.

[0476] In addition, silicon oxide is preferably deposited by sputtering as the insulator 280. By depositing an insulating film to be the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, heat treatment can also be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, and the insulating film is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed to the surface of the insulator 275 can be removed. The heat treatment can adopt the conditions of the above-mentioned heat treatment.

[0477] Next, the conductor 242A, the insulator 271A, the insulator 275, and the insulator 280 are processed by photolithography to form openings reaching the oxide semiconductor 230 and the insulator 222 (see FIG. 15A to FIG. 15D Here, the conductor 242A is divided into the conductor 242a and the conductor 242b, and the insulator 271A is divided into the insulator 271a and the insulator 271b. The openings formed in the insulator 280 and the insulator 275 overlap with the oxide semiconductor 230 and the conductor 205.

[0478] The above method can be appropriately used by lithography technology. In order to process the opening of the insulator 280 into a small size, it is preferable to use lithography technology using short-wavelength light such as EUV light or electron beam. For example, FIG. 16A1 to FIG. 16D2 The method shown forms openings in the insulator 280 to form the conductors 242a and 242b.

[0479] First, a coating film 277 is deposited on the insulator 280, and a coating film 278 is deposited (see Fig.16A1 and Fig.16A2The coating films 277 and 278 may also have the function of improving the adhesion between the resist mask described later and the insulator 280. The coating films 277 and 278 may be deposited by, for example, spin coating. As the coating films 277 and 278, non-photosensitive organic resins may be used.

[0480] Here, the coating film 278 is used as a mask in the etching process of processing the coating film 277. Therefore, under the etching conditions of the coating film 277, the etching rate of the coating film 278 is preferably lower than the etching rate of the coating film 277. For example, the coating film 277 can be set to a film containing carbon, and the coating film 278 can be set to a film containing silicon and carbon. In this embodiment, the SOC film is deposited as the coating film 277, and the SOG film is deposited as the coating film 278.

[0481] Note that the coating film 277 and the coating film 278 contain an organic solvent such as alcohol when applied, but the organic matter contained is sometimes reduced or removed in the subsequent process or when the semiconductor device is completed. In addition, the coating film can be provided as needed, a single-layer coating film can be provided, or a coating film may not be provided when only the resist mask described later is sufficient.

[0482] Next, a resist mask 279 having an opening is formed on the coating film 278 by using a lithography technique (see Fig.16A1 and Fig.16A2 ). The resist mask 279 can be formed by exposing the resist using, for example, KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask may not be used in some cases.

[0483] Below, according to FIG. 16B1 to FIG. 16D2 In the process, it is preferred to process the workpiece by dry etching. Anisotropic etching can be performed in dry etching, so dry etching is suitable for forming openings with a high aspect ratio. When anisotropic etching is performed, for example, reactive ion etching is preferably performed. Note that the dry etching conditions and dry etching apparatus can refer to the above content. Note that according to FIG. 16B1 to FIG. 16D2 The process is preferably performed continuously without being exposed to the atmosphere. For example, it can be performed continuously without being exposed to the atmosphere using a multi-chamber etching apparatus.

[0484] First, the coating film 278 is processed using the resist mask 279 to form the coating film 278 having an opening. For example, when an SOG film is used for the coating film 278, etching can be performed using a DF-CCP etching apparatus and CF4 as an etching gas.

[0485] Next, the coating film 278 is used as a mask to process the coating film 277 to form a coating film 277 having an opening (see Fig.16B1 and Figure 16B2 ). For example, when an SOC film is used for the coating film 277, a DF-CCP etching device can be used to perform etching using H2 and N2 as etching gases. Here, since an SOG film is used as the coating film 278, the coating film 278 can be prevented from disappearing during the etching process of the coating film 277.

[0486] In addition, the resist mask 279 is preferably removed simultaneously with the processing of the coating film 277. Since the SOC film is used as the coating film 277, the resist mask 279 can be easily removed. In addition, when the resist mask 279 remains after the coating film 277 is formed, the resist mask 279 is preferably removed.

[0487] Next, the insulator 280 is processed using the coating film 277 as a mask to form the insulator 280 having an opening. For example, when a silicon oxide film is used for the insulator 280, etching can be performed using a DF-CCP etching apparatus and using C4F8, C4F6, O2, and Ar as etching gases.

[0488] Furthermore, the insulator 275 and the insulator 271A are processed using the coating film 277 as a mask to form the insulator 275, the insulator 271a, and the insulator 271b having openings (see Fig.16C1 and Fig.16C2 ). For example, when a silicon oxide film and a silicon nitride film are used for the insulator 275 and the insulator 271A, a DF-CCP etching device can be used and CH2F2, O2 and Ar can be used as etching gases for etching. In this case, the conductor 242A and the insulator 222 can be used as an etching stop layer. In addition, it is preferable to remove the coating film 278 while processing the insulator 275 and the insulator 271A.

[0489] After forming the insulators 271a and 271b, preferably, dry etching such as ashing using oxygen plasma is performed to remove the coating film 277. However, the present invention is not limited thereto, and the coating film 277 may be removed after forming the conductors 242a and 242b.

[0490] Next, the surface oxide film of the conductor 242A is preferably removed using the insulator 280 as a mask. For example, when a tantalum nitride film is used for the conductor 242A, etching can be performed using an ICP etching apparatus and BCl 3 and Cl 2 as etching gases.

[0491] Furthermore, the conductor 242A is processed using the insulator 280 as a mask to form the conductor 242a and the conductor 242b (see Fig.16D1 and Fig.16D2 ). For example, when a tantalum nitride film is used for the conductor 242A, an ICP etching device can be used to perform etching using Cl2 and Ar as etching gases. In this case, the oxide semiconductor 230 and the insulator 222 can be used as an etching stop layer. In this case, Fig.16D2 As shown, when the transistor 200 is cross-sectionally viewed in the channel width direction, there may be a curved surface between the side surface of the oxide semiconductor 230 and the top surface of the oxide semiconductor 230. That is, the end of the side surface and the end of the top surface may be rounded.

[0492] A recessed portion may be formed in a portion of the oxide semiconductor 230 exposed from the conductor 242a and the conductor 242b. In other words, on the top surface of the oxide semiconductor 230, a region sandwiched between the conductor 242a and the conductor 242b may be smaller in height than a region overlapping with the conductor 242a and a region overlapping with the conductor 242b.

[0493] Through the above steps, openings may be formed in the insulators 275 and 280 , and the insulators 271 a , 271 b , the conductors 242 a , and the conductors 242 b may be formed.

[0494] After the conductor 242A is processed, an ashing treatment using oxygen plasma may also be performed. By performing such an oxygen plasma treatment, impurities generated in the above-mentioned etching process and diffused into the oxide semiconductor 230 and the like can be removed. As such impurities, impurities of components in the workpiece caused by the above-mentioned etching process and impurities of components in the gas used in etching and the like can be cited. For example, chlorine, fluorine, tantalum, silicon, hafnium, etc. can be cited. By removing impurities attached to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0495] The processing and oxygen plasma treatment of the conductor 242A can be performed continuously without being exposed to the atmosphere. For example, a multi-chamber etching apparatus can be used without being exposed to the atmosphere.

[0496] Preferably, a cleaning process is performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the above-mentioned etching process. As a cleaning method, there are wet cleaning using a cleaning liquid or the like (which may also be referred to as a wet etching process), plasma treatment using plasma, cleaning using a heat treatment, and the like, and the above-mentioned cleaning may be appropriately combined. Note that the above-mentioned groove may become deeper by performing this cleaning process.

[0497] Wet cleaning can also be performed using an aqueous solution formed by diluting one or more of oxalic acid, phosphoric acid and hydrofluoric acid with carbonated water or pure water. In addition, wet cleaning can also be performed using an aqueous solution formed by diluting ammonia water with carbonated water or pure water. In addition, wet cleaning can also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning can also be performed using the above-mentioned aqueous solution, pure water or carbonated water. In addition, the above-mentioned washing can also be appropriately combined.

[0498] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, and more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01ppm or more and 100ppm or less, and more preferably set to 0.1ppm or more and 10ppm or less.

[0499] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide semiconductor 230 and the like can be reduced.

[0500] In addition, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be a treatment using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be a treatment using pure water or carbonated water.

[0501] As the washing process, in this embodiment, carbonated water is used for wet washing. By performing this washing process, impurities attached to the surface of the oxide semiconductor 230 or diffused into the inside thereof can be removed. In addition, the surface layer of the oxide semiconductor 230 damaged in the etching process can also be removed.

[0502] It is preferred to perform heat treatment after the above-mentioned etching or after the above-mentioned washing. The temperature of the heat treatment is not less than 100°C and not more than 650°C, preferably not less than 250°C and not more than 600°C, more preferably not less than 300°C and not more than 550°C, and further preferably not less than 350°C and not more than 400°C. The heat treatment is performed in an atmosphere of nitrogen gas, an inert gas, or an oxidizing gas containing not less than 10 ppm, not less than 1%, or not less than 10%. For example, it is preferred to perform the heat treatment in an oxygen-containing atmosphere, preferably at a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide semiconductor 230, so that oxygen vacancies can be reduced. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, when the residual hydrogen in the oxide semiconductor 230 reacts with the supplied oxygen, the hydrogen can be removed (dehydrated) in the form of H2O. Thus, the hydrogen remaining in the oxide semiconductor 230 can be inhibited from recombinating with oxygen vacancies to form V O H. Thus, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved and the reliability can be improved. In addition, the non-uniformity of the electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed. The above-mentioned heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere, and then the heat treatment can be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere. In addition, the above-mentioned heat treatment can also serve as the heat treatment shown in Embodiment 1. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows by the above-mentioned heat treatment.

[0503] When the conductor 242a and the conductor 242b are heat treated in a state of being in contact with the oxide semiconductor 230, the sheet resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may be reduced. In addition, the carrier concentration may be increased. Therefore, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0504] Next, an insulating film 250f (see FIG. 250f ) to be the insulator 250 is deposited so as to cover the opening formed in the insulator 280 and the like. 17A to 17D Here, the insulating film 250 f is deposited along the openings of the insulator 280 and the insulator 275 . The insulating film 250 f is in contact with the insulator 280 , the conductor 242 a , the conductor 242 b , the insulator 222 , the insulator 224 , and the oxide semiconductor 230 .

[0505] The insulating film 250f can be deposited by sputtering, CVD, MBE, PLD or ALD. For example, the insulating film 250f is preferably deposited by the ALD method. The insulating film 250f is preferably formed thin, and the thickness unevenness needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.). Since the thickness of the film can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, the insulating film 250f needs to be deposited on the bottom and side surfaces of the above-mentioned opening with high coverage. By using the ALD method, since each atomic layer can be deposited on the bottom and side surfaces of the above-mentioned opening, the insulating film 250f can be formed in the opening with high coverage.

[0506] When the insulating film 250f is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as an oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidant, hydrogen diffused into the oxide semiconductor 230 can be reduced.

[0507] like Figure 8B As shown in FIG. 1 and FIG. 2 , the insulator 250 may have a laminated structure. Figure 8B Similarly, a deposition method of the insulating film 250f is described in detail when the insulating film 250f has a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d.

[0508] First, a film to be the insulator 250a is deposited so as to cover the opening formed in the insulator 280, etc., and a film to be the insulator 250b is deposited on the film to be the insulator 250a. In this embodiment, aluminum oxide is deposited as the film to be the insulator 250a by the thermal ALD method, and silicon oxide is deposited as the film to be the insulator 250b by the PEALD method.

[0509] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to, for example, the treatment using a device including a power supply for generating high-density plasma using microwaves. In addition, in this specification, microwave refers to an electromagnetic wave having a frequency of more than 300 MHz and less than 300 GHz.

[0510] Microwave treatment, for example, preferably uses a microwave processing device that includes a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to be greater than 300 MHz and less than 300 GHz, more preferably greater than 2.4 GHz and less than 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably greater than 1000 W and less than 10000 W, more preferably greater than 2000 W and less than 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0511] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is preferably 750°C or less, more preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment without being exposed to the outside air after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.

[0512] In addition, for example, the above-mentioned microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration of the area exposed from the opening of the oxide semiconductor 230 can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave treatment, the carrier concentration in the oxide semiconductor 230 can be prevented from being excessively reduced.

[0513] By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to convert oxygen gas into plasma, and the oxygen plasma can be applied to a region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 8BWhen the structure shown in the figure is used, it is preferable to use an insulating film (for example, aluminum oxide, etc.) having a function of capturing or fixing hydrogen as the film to be the insulator 250a. By adopting the above structure, the film to be the insulator 250a can capture or fix hydrogen generated by microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0514] As oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (also called O free radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region is preferably any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0515] On the other hand, the oxide semiconductor 230 has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as shielding films for protecting from microwaves, high frequencies such as RF, or oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Thus, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0516] The conductors 242a and 242b shield the microwaves, high frequencies such as RF, oxygen plasma, etc., and thus do not act on the region of the oxide semiconductor 230 that overlaps with either the conductors 242a and 242b. Thus, V is not generated in the source region and the drain region by the microwave treatment. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0517] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. O H makes the channel formation region i-type or substantially i-type. In addition, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (the state of the low resistance region) before the microwave treatment. Thus, it is possible to suppress the change of the electrical characteristics of the transistor and suppress the non-uniformity of the electrical characteristics of the transistor within the substrate surface.

[0518] Furthermore, by performing microwave treatment to modify the film quality of the film to be the insulator 250a and the film to be the insulator 250b, diffusion of hydrogen, water, impurities, etc. can be suppressed. Thus, diffusion of hydrogen, water, impurities, etc. through the insulator 250 to the oxide semiconductor 230, etc., due to post-processes such as deposition of the conductive film to be the conductor 260 or post-processes such as heat treatment can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0519] Next, a film to be the insulator 250d is deposited on the film to be the insulator 250b. In this embodiment, hafnium oxide is deposited as the film to be the insulator 250d by thermal ALD. Alternatively, microwave treatment may be performed again after the film to be the insulator 250d is deposited.

[0520] Next, a film to be the insulator 250c is deposited on the film to be the insulator 250d. In this embodiment, silicon nitride is deposited as the film to be the insulator 250c by the PEALD method. In this way, an insulating film 250f including the film to be the insulator 250a to the film to be the insulator 250d can be formed.

[0521] Note that in the above structure, an example of performing microwave treatment after depositing the film that will become the insulator 250b and after depositing the film that will become the insulator 250d is shown, but the present invention is not limited to this. Microwave treatment may also be performed after the deposition of the film that will become the insulator 250c. Alternatively, microwave treatment may be performed before depositing the film that will become the insulator 250a. In addition, microwave treatment may be performed three or more times. In addition, the above microwave treatment may sometimes also serve as the heat treatment shown in Embodiment 1. Therefore, the crystalline region of the oxide semiconductor 230 is sometimes grown by the above microwave treatment.

[0522] In addition, heat treatment may be performed while maintaining a reduced pressure state after the microwave treatment. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. In addition, the step of maintaining a reduced pressure state and performing heat treatment after the microwave treatment may be repeated. By repeatedly performing heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be further efficiently removed. Note that the heat treatment temperature is preferably not less than 300° C. and not more than 500° C. In addition, the above-mentioned heat treatment may also serve as the heat treatment described in Embodiment 1. Therefore, the crystalline region of the oxide semiconductor 230 is sometimes grown by the above-mentioned heat treatment.

[0523] Next, a conductive film 260f (see 17A to 17D). The conductive film 260f can be deposited by using the above conductive materials and by using a sputtering method, a CVD method, a MBE method, a PLD method, a plating method, or an ALD method. For example, a titanium nitride film and a tungsten film can be deposited by using a CVD method. Fig. 8A As shown, the conductor 260 may have a stacked structure of a conductor 260a made of titanium nitride and a conductor 260b made of tungsten. Alternatively, the conductive film 260f may be deposited while the substrate is heated. Alternatively, the heating of the substrate may also serve as the heat treatment described in Embodiment 1. Therefore, the crystallized region of the oxide semiconductor 230 may be grown by heating the substrate.

[0524] Next, the insulating film 250f and the conductive film 260f are polished by CMP until the insulator 280 is exposed. That is, the portion of the insulating film 250f and the conductive film 260f exposed from the above-mentioned opening is removed. Thus, the insulator 250 and the conductive body 260 (conductive body 260a and conductive body 260b) are formed in the opening overlapping with the conductive body 205 (see 18A to 18D ).

[0525] Thus, the insulator 250 is provided in the opening so as to be in contact with the conductor 242a, the conductor 242b, the oxide semiconductor 230, the insulator 224, and the insulator 222. The conductor 260 is disposed so as to be embedded in the opening via the insulator 250. Thus, the transistor 200 is formed.

[0526] Next, an insulator 282 is deposited on the insulator 250, the conductor 260, and the insulator 280 (see FIG. 19A to FIG. 19D ). The insulator 282 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 282 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used for the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0527] In addition, if Fig. 8A As shown, the insulator 282 preferably has a stacked structure of an insulator 282a and an insulator 282b. Here, the insulator 282a is preferably deposited by ALD, and the insulator 282b is preferably deposited by sputtering.

[0528] In this embodiment, aluminum oxide may be deposited as the insulator 282a by a thermal ALD method. Here, the thickness of the insulator 282a may be greater than or equal to 1 nm and less than or equal to 20 nm, and preferably greater than or equal to 3 nm and less than or equal to 10 nm.

[0529] By depositing the insulator 282a by the ALD method, the insulator 282a can be deposited without causing excessive damage to the surface to be formed. Therefore, the upper end of the insulator 250 and the top surface of the conductor 260 can be prevented from being excessively damaged, so that the electrical characteristics and reliability of the transistor 200 can be improved.

[0530] Furthermore, by depositing the insulator 282a using the ALD method, the insulator 282a can be deposited without adding oxygen to the insulator 280. Thus, it is possible to prevent excessive addition of oxygen to the insulator 280. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0531] In this embodiment, aluminum oxide can be deposited as the insulator 282 b by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0532] Here, by depositing the insulator 282b in an oxygen-containing atmosphere by sputtering, oxygen can be added to the insulator 280 while the deposition is being performed. Thus, the insulator 280 can contain excess oxygen. At this time, it is preferred to deposit the insulator 282b while heating the substrate. Here, since the insulator 282b is deposited on the insulator 282a and oxygen is added through the insulator 282a, the amount of oxygen injected into the insulator 280 can be controlled. When the thickness of the insulator 282a is large, the above-mentioned oxygen addition is easily hindered and the amount of oxygen injected into the insulator 280 is reduced. When the thickness of the insulator 282a is small, the above-mentioned oxygen addition is not easily hindered and the amount of oxygen injected into the insulator 280 is increased. For example, by setting the thickness of the insulator 282a to within the above range, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and excessive oxygen can be prevented from being supplied to the oxide semiconductor 230. Thus, the electrical characteristics and reliability of the transistor 200 can be improved. In addition, when the insulator 282 b is deposited, oxygen may be added not only to the insulator 280 but also to the upper end of the insulator 250 .

[0533] Furthermore, by depositing the insulator 282 b on the insulator 282 a , the upper end of the insulator 250 and the top surface of the conductor 260 can be protected from the impact of ion collisions generated by the sputtering deposition of the insulator 282 b .

[0534] Aluminum oxide is deposited using an aluminum target in an atmosphere containing an oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled according to the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less oxygen is injected into the insulator 280, and the oxygen amount is easily saturated even if the thickness of the insulator 282b is small. In addition, the greater the bias power, the more oxygen is injected into the insulator 280. By reducing the bias power, the amount of oxygen injected into the insulator 280 can be suppressed. Note that when a substrate bias is applied using an RF power supply, the frequency of the RF is preferably above 10 MHz. Typically, it is 13.56 MHz. The higher the frequency of the RF, the less damage to the substrate can be caused.

[0535] In addition, heat treatment may be performed before depositing the insulator 282b. The heat treatment may also be performed under reduced pressure, wherein the insulator 282b is continuously deposited without being exposed to the atmosphere. By performing such treatment, the moisture and hydrogen adsorbed to the surface of the insulator 280 may be captured or fixed by the insulator 282a, and the moisture concentration and hydrogen concentration in the insulator 280 may be reduced. The temperature of the heat treatment is preferably 100°C or more and 400°C or less. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0536] Next, an insulator 283 is formed on the insulator 282 (see FIG. 19A to FIG. 19D ). The insulator 283 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 283 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used for the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited by sputtering as the insulator 283.

[0537] In this embodiment, silicon nitride is deposited by sputtering as the insulator 283, and aluminum oxide is deposited by thermal ALD and sputtering as the insulator 282. In this way, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 283, diffusion of hydrogen from an upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed by the insulator 282. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0538] Next, an insulator 285 is formed on the insulator 283 (see FIG. 19A to FIG. 19D). The insulator 285 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 285 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used for the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is deposited by sputtering as the insulator 285.

[0539] Here, it is preferable to continuously deposit the insulator 282, the insulator 283, and the insulator 285 by sputtering without exposing them to the atmosphere. By depositing them without exposing them to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to the insulator 282, the insulator 283, and the insulator 285, so that the vicinity of the interface between the insulator 282 and the insulator 283 and the vicinity of the interface between the insulator 283 and the insulator 285 can be kept clean.

[0540] Next, an opening reaching the conductor 242a is formed in the insulator 271a, the insulator 275, the insulator 280, the insulator 282, the insulator 283 and the insulator 285, and an opening reaching the conductor 242b is formed in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283 and the insulator 285. The formation of the opening can be performed using a lithography technique. When forming the opening, it is preferred to process the workpiece using a dry etching method. Anisotropic etching can be performed in the dry etching method, so the dry etching method is suitable for forming an opening with a high aspect ratio. When anisotropic etching is performed, for example, reactive ion etching is preferably performed. For the conditions of the dry etching method and the dry etching device, reference can be made to the previous records. In addition, the shape of the opening when viewed from above can be a circular shape, an ellipse or other approximate circular shape, a polygonal shape such as a quadrangle, a shape with an arc at the corner of a polygon such as a quadrangle, etc.

[0541] Next, after the above-mentioned opening is formed, heat treatment is performed. The temperature of the heat treatment can be above 100°C and below 600°C, preferably above 250°C and below 550°C, and more preferably above 350°C and below 450°C. The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. In addition, since the heat treatment is performed in a state where the conductor 242a and the conductor 242b are exposed, it is preferably performed in an atmosphere that does not contain an oxidizing gas and an oxygen gas. For example, it is preferred to perform a heat treatment at a temperature of 400°C for 1 hour in a nitrogen gas atmosphere. The above-mentioned heat treatment can also be performed under reduced pressure. Through the above-mentioned heat treatment, the oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. Thereby, the oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. In addition, the above-mentioned heat treatment can also serve as the heat treatment shown in Embodiment 1. Therefore, sometimes the crystalline region of the oxide semiconductor 230 is grown by the above-mentioned heat treatment.

[0542] Here, since the side of the insulator 280 is exposed in the above-mentioned opening, the above-mentioned heat treatment can be used to control the amount of oxygen contained in the insulator 280 by causing the oxygen contained in the insulator 280 to diffuse outward. On the other hand, since the insulator 280 is provided with the insulator 282 and the insulator 283 having oxygen barrier properties, oxygen does not diffuse outward from the top surface of the insulator 280. Thus, it is possible to prevent excessive oxygen from diffusing outward from the insulator 280 and forming oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered by the insulator 275. Thus, it is possible to prevent excessive oxygen from diffusing directly from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the above-mentioned heat treatment.

[0543] As described above, when depositing the insulator 282b, by adding oxygen to the insulator 280 through the insulator 282a, the amount of oxygen added to the insulator 280 can be controlled. Furthermore, when the oxygen is diffused outward from the side of the insulator 280 by the above-mentioned heat treatment, the amount of oxygen in the insulator 280 can be more appropriate. In this way, by supplying oxygen to the oxide semiconductor 230 from the insulator 280 in which the amount of oxygen is adjusted, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Thus, oxygen vacancies in the oxide semiconductor 230 can be reduced and excessive oxygen can be prevented from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. In addition, the process of exposing the side of the insulator 280 can also serve as the process of forming the openings for embedding the conductor 240a and the conductor 240b, so the manufacturing process of the semiconductor device can be simplified.

[0544] In addition, by performing the above-mentioned heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 moves to the insulator 282 and is captured by the insulator 282. In other words, the hydrogen in the insulator 280, the insulator 250, and the oxide semiconductor 230 diffuses into the insulator 282. Therefore, although the hydrogen concentration of the insulator 282 becomes higher, the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide semiconductor 230 all become lower. In addition, when the insulator 283 is provided in contact with the top surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. In addition, by performing the heat treatment, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 moves to the insulator 222 and is captured by the insulator 222. In other words, the hydrogen in the insulator 216, the insulator 224, and the oxide semiconductor 230 diffuses into the insulator 222. Therefore, although the hydrogen concentration of the insulator 222 increases, the hydrogen concentrations of the insulator 216, the insulator 224, and the oxide semiconductor 230 all decrease. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture and hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment.

[0545] Next, an insulating film to be the insulator 241a and the insulator 241b is deposited along the shape of the above-mentioned opening. The insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film to be the insulator 241a and the insulator 241b is deposited in an opening with a high aspect ratio, it is preferably deposited by an ALD method. As the insulating film to be the insulator 241a and the insulator 241b, an insulating film having a function of inhibiting oxygen permeation is preferably used. For example, silicon nitride is preferably deposited by a PEALD method. Silicon nitride is preferred because it has a high hydrogen barrier property.

[0546] Next, the insulating film is anisotropically etched to form insulators 241a and 241b. Here, insulator 241a is formed in a manner that covers the side walls of the opening on conductor 242a, and insulator 241b is formed in a manner that covers the side walls of the opening on conductor 242b. As anisotropic etching of the insulating film that will become insulator 241a and insulator 241b, dry etching method or the like can be used. For example, reactive ion etching is preferably performed. By providing insulators 241a and insulators 241b on the side walls of the opening, it is possible to suppress the penetration of oxygen from the outside and prevent oxidation of conductors 240a and 240b that are formed next. In addition, it is possible to prevent impurities such as water and hydrogen contained in insulator 280 and the like from diffusing into conductors 240a and 240b. Note that sometimes a recess is formed on a portion of the top surface of conductors 242a and 242b due to this anisotropic etching.

[0547] Next, a conductive film to be the conductor 240a and the conductor 240b is deposited. The conductive film preferably has a laminated structure including a conductor having a function of inhibiting the permeation of impurities such as water and hydrogen. For example, a laminated structure of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. can be used. The conductive film to be the conductor 240a and the conductor 240b can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0548] Next, a portion of the conductive film to be the conductors 240a and 240b is removed by CMP treatment, thereby exposing the top surface of the insulator 285. As a result, the conductive film remains only in the opening, thereby forming the conductors 240a and 240b with flat top surfaces (see FIG. 7A to 7D ). Note that sometimes a portion of the top surface of the insulator 285 is removed due to the CMP process.

[0549] In addition, heat treatment may be performed after the conductor 240a and the conductor 240b are formed. The heat treatment may be performed under the same conditions as the above-mentioned heat treatment. By performing the heat treatment, the amount of oxygen supplied to the oxide semiconductor 230 may be adjusted. Thus, the electrical characteristics and reliability of the transistor 200 may be improved.

[0550] Through the above process, it is possible to produce 7A to 7D The semiconductor device shown.

[0551] The semiconductor device according to this embodiment includes an OS transistor. In this embodiment, by using Axial Growth CAAC as an oxide semiconductor layer of the OS transistor, a semiconductor device with good electrical characteristics can be provided. For example, the on-state current, S value, field effect mobility, and frequency characteristics of the transistor can be improved. In addition, a semiconductor device with high reliability can be provided.

[0552] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0553] Implementation 3

[0554] In this embodiment, a semiconductor device 900 which is one embodiment of the present invention is described. The semiconductor device 900 can be used as a memory device.

[0555] Fig. 20 is a block diagram showing a structural example of a semiconductor device 900 . Fig. 20The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Fig. 20 An example is shown in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0556] The transistor described in Embodiment 2 can be used for the memory cell 950. By using the above transistor, the operating speed of the memory device can be increased. Furthermore, the memory device can be miniaturized and highly integrated. In addition, the capacity per unit area of ​​the memory device can be increased.

[0557] The driving circuit 910 includes a PSW 931 (power switch), a PSW 932 , and a peripheral circuit 915 . The peripheral circuit 915 includes a peripheral circuit 911 , a control circuit 912 , and a voltage generating circuit 928 .

[0558] In the semiconductor device 900, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0559] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 912.

[0560] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 to execute the above operation mode.

[0561] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0562] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0563] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting a row to be connected to the row specified by the row decoder 941. The column driver 924 has the following functions: a function of writing data to the memory cell 950; a function of reading data from the memory cell 950; a function of holding the read data, etc.

[0564] The input circuit 925 has a function of holding a signal WDA. The data held in the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) written to the memory cell 950. The data (Dout) read out from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data signal output from the output circuit 926 is a signal RDA.

[0565] PSW931 has the function of controlling the supply of V to the peripheral circuit 915 DD PSW932 has the function of controlling the supply of V to the row driver 923. HM Here, the high power supply voltage of the semiconductor device 900 is V DD , the low power supply voltage is GND (ground potential). In addition, V HM It is a high power supply voltage used to make the word line high, which is higher than V DD The on / off of PSW931 is controlled by signal PON1, and the on / off of PSW932 is controlled by signal PON2. Fig. 20 In the peripheral circuit 915, V DD The number of power domains is 1, but may be multiple. In this case, a power switch may be provided for each power domain.

[0566] Reference FIG. 21A to FIG. 21H Other examples of memory cell structures that can be used for the memory cell 950 are described below.

[0567] [DOSRAM]

[0568] Fig.21AAn example of a circuit structure of a DRAM type memory cell is shown. In this specification, etc., a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0569] The transistor M1 may include a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is supplied. In addition, the front gate and the back gate may be connected.

[0570] The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the second terminal of the capacitor CA is connected to the wiring CAL.

[0571] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. In writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0572] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0573] In addition, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit structure can also be changed. Fig.21B The structure of the memory cell 952 shown in FIG. 9 is an example of a case where the capacitor CA and the wiring CAL are not included. The first terminal of the transistor M1 is in an electrically floating state.

[0574] In the memory cell 952, the potential written by the transistor M1 is held in the capacitance (also referred to as parasitic capacitance) between the first terminal and the gate indicated by the dotted line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0575] As the transistor M1, it is preferred to use the OS transistor shown in Embodiment 2. By using the OS transistor shown in Embodiment 2, the operating speed of the storage device can be increased. In addition, the occupied area of ​​the storage cell can be reduced. In addition, the OS transistor has a characteristic of extremely small off-state current. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. In other words, the transistor M1 can be used to maintain the written data for a long time, thereby reducing the refresh frequency of the storage cell. In addition, the refresh operation of the storage cell can be omitted. In addition, since the leakage current is very small, multi-value data or analog data can be maintained in the storage cell 951 and the storage cell 952.

[0576] Here, refer to Fig. 22 An example of the structure of a DOSRAM is shown below. Fig. 22 In the figure, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction.

[0577] like Fig. 22 As shown, the memory cell 951 includes a transistor M1 and a capacitor CA. An insulator 284 is provided on the transistor M1. The insulator 284 can use the insulator that can be used for the insulator 216. In addition, the transistor M1 has the same structure as the transistor 200 shown in Embodiment 2, and the same symbols are attached to the same components. For details of the transistor 200, reference can be made to Embodiment 2. In addition, the conductor 240b (conductor 240b1 and conductor 240b2) is provided in a manner of contacting one of the source electrode and the drain electrode (conductor 242b) of the transistor M1. The conductor 240b extends in the Z direction and is used as the wiring BIL. In addition, the conductor 260 of the transistor 200 extends in the X direction and is used as the wiring WOL.

[0578] The capacitor CA includes a conductor 453 on the conductor 242 a , an insulator 454 on the conductor 453 , and a conductor 460 (a conductor 460 a and a conductor 460 b ) on the insulator 454 .

[0579] At least a portion of each of the conductor 453, the insulator 454, and the conductor 460 is disposed inside the openings provided in the insulator 271a, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. An end portion of each of the conductor 453, the insulator 454, and the conductor 460 is located at least on the insulator 283, preferably on the insulator 285. The insulator 454 is provided so as to cover the end portion of the conductor 453. Thus, the conductor 453 and the conductor 460 can be electrically insulated.

[0580] The deeper the depth of the openings provided in the insulators 271a, 275, 280, 282, 283, and 285 (that is, the thickness of one or more of the insulators 271a, 275, 280, 282, 283, and 285 is increased), the greater the electrostatic capacitance of the capacitor CA can be. By increasing the electrostatic capacitance per unit area of ​​the capacitor CA, miniaturization or high integration of the storage device can be achieved.

[0581] The conductor 453 has a region serving as one electrode (lower electrode) of the capacitor CA. The insulator 454 has a region serving as a dielectric of the capacitor CA. The conductor 460 has a region serving as the other electrode (upper electrode) of the capacitor CA. In addition, the top of the conductor 460 may be extended and used as a wiring CAL. The capacitor CA constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0582] The conductor 242 a provided on the oxide semiconductor 230 so as to overlap with the oxide semiconductor 230 is used as an electrode electrically connected to the lower electrode of the capacitor CA.

[0583] The conductor 453 and the conductor 460 included in the capacitor CA can be formed using various conductors that can be used for the conductor 205 or the conductor 260. It is preferable that both the conductor 453 and the conductor 460 are deposited using a deposition method with high coverage such as the ALD method or the CVD method. For example, titanium nitride or tantalum nitride deposited by the ALD method or the CVD method can be used as the conductor 453.

[0584] The bottom surface of the conductor 453 is in contact with the top surface of the conductor 242a. Here, by using a conductive material with good conductivity as the conductor 242a, the contact resistance between the conductor 453 and the conductor 242a can be reduced.

[0585] Alternatively, titanium nitride deposited by ALD or CVD may be used as conductor 460a, and tungsten deposited by CVD may be used as conductor 460b. Here, when the adhesion of tungsten to insulator 454 is sufficiently high, a single layer of tungsten deposited by CVD may be used as conductor 460.

[0586] The insulator 454 included in the capacitor CA preferably uses a material with a high relative dielectric constant (high-k) as described in the above embodiment. By using such a high-k material, the insulator 454 can be thickened to a degree that can suppress leakage current, and the electrostatic capacitance of the capacitor CA can also be sufficiently ensured. In addition, the insulator 454 is preferably deposited using a deposition method with high coverage such as the ALD method or the CVD method.

[0587] In addition, it is preferred to use an insulator composed of the above-mentioned materials in a stacked manner, and it is preferred to use a stacked structure of a material having a high relative dielectric constant (high-k) and a material having a greater dielectric strength than the material having a high relative dielectric constant (high-k). For example, as the insulator 454, an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. In addition, for example, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. In addition, for example, an insulator stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulator with a relatively large dielectric strength such as aluminum oxide in a stacked manner, the dielectric strength is increased, and thus the electrostatic destruction of the capacitor CA can be suppressed.

[0588] Alternatively, a material having ferroelectricity may be used as the insulator 454. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0589] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2 and the number of atoms of the element M3 can be appropriately set.

[0590] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0591] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0592] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulator 454 can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0593] Ferroelectrics are insulators that have the property of being polarized internally when an electric field is applied from the outside and maintaining polarization even when the electric field is 0. Therefore, a non-volatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) using the material as a dielectric. Non-volatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, and the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, in the case of using a ferroelectric capacitor as the capacitor CA, the storage...

Claims

1. A semiconductor device comprising: an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer contains indium, The oxide semiconductor layer is formed in parallel or substantially parallel to the surface of the substrate, The oxide semiconductor layer has: Region 1; and a second area on the first area, The first region is arranged within a range of 0 nm to 3 nm from the surface on which the oxide semiconductor layer is formed in a direction substantially perpendicular to the surface on which the oxide semiconductor layer is formed, Furthermore, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formed surface of the oxide semiconductor layer are confirmed in each of the first region and the second region.

2. The semiconductor device according to claim 1, wherein said second region comprises zinc, the second region comprises crystals, Furthermore, the c-axis of the crystal is substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer.

3. The semiconductor device according to claim 1, The c-axis orientation ratio in the second region is higher than the c-axis orientation ratio in the first region.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer further has a third region on the second region, The c-axis orientation ratio in the third region is higher than the c-axis orientation ratio in the first region, Furthermore, in the cross-sectional observation of the oxide semiconductor layer using the transmission electron microscope, bright spots arranged in a layered manner in the direction parallel to the formed surface of the oxide semiconductor layer are confirmed in the third region.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer further has a third region on the second region, The indium content in the first region is higher than the indium content in the second region, The indium content in the third region is higher than the indium content in the second region, Furthermore, in the cross-sectional observation of the oxide semiconductor layer using the transmission electron microscope, bright spots arranged in a layered manner in the direction parallel to the formed surface of the oxide semiconductor layer are confirmed in the third region.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed on an insulator, And the insulator is amorphous.

7. A semiconductor device comprising: a first insulator on the substrate; an oxide semiconductor layer on the first insulator; a second insulator on the oxide semiconductor layer; as well as a conductor on the second insulator, wherein the first insulator and the oxide semiconductor layer are formed in parallel or substantially parallel to the surface of the substrate, The oxide semiconductor layer includes indium, The oxide semiconductor layer is formed in parallel or substantially parallel to the surface of the substrate, The oxide semiconductor layer has: First region; as well as a second area on the first area, The first region is arranged within a range of 0 nm to 3 nm from the surface on which the oxide semiconductor layer is formed in a direction substantially perpendicular to the surface on which the oxide semiconductor layer is formed, Furthermore, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formed surface of the oxide semiconductor layer are confirmed in each of the first region and the second region.

8. The semiconductor device according to claim 7, wherein said second region comprises zinc, the second region comprises crystals, Furthermore, the c-axis of the crystal is substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer.

9. The semiconductor device according to claim 7, The c-axis orientation ratio in the second region is higher than the c-axis orientation ratio in the first region.

10. The semiconductor device according to claim 7, wherein the oxide semiconductor layer further has a third region on the second region, The c-axis orientation ratio in the third region is higher than the c-axis orientation ratio in the first region, Furthermore, in the cross-sectional observation of the oxide semiconductor layer using the transmission electron microscope, bright spots arranged in a layered manner in the direction parallel to the formed surface of the oxide semiconductor layer are confirmed in the third region.

11. The semiconductor device according to claim 7, wherein the oxide semiconductor layer further has a third region on the second region, The indium content in the first region is higher than the indium content in the second region, The indium content in the third region is higher than the indium content in the second region, Furthermore, in the cross-sectional observation of the oxide semiconductor layer using the transmission electron microscope, bright spots arranged in a layered manner in the direction parallel to the formed surface of the oxide semiconductor layer are confirmed in the third region.

12. The semiconductor device according to claim 7, The first insulator is amorphous.

13. The semiconductor device according to claim 12, further comprising a third insulator covering the first insulator and the oxide semiconductor layer, wherein the third insulator has an opening formed therein that reaches the oxide semiconductor layer, And the second insulator and the conductor are arranged in the opening.

14. The semiconductor device according to claim 7, further comprising a third insulator covering the first insulator and the oxide semiconductor layer, wherein the third insulator has an opening formed therein that reaches the oxide semiconductor layer, The first insulator is amorphous, The second insulator and the conductor are arranged in the opening, The oxide semiconductor layer further includes a third region on the second region, The second insulator is in contact with the third region, Furthermore, in the cross-sectional observation of the oxide semiconductor layer using the transmission electron microscope, bright spots arranged in a layered manner in the direction parallel to the formed surface of the oxide semiconductor layer are confirmed in the third region.

15. A method for manufacturing a semiconductor device, comprising the following steps: depositing a first insulator on a substrate; depositing an oxide semiconductor layer on the first insulator; performing a heat treatment on the oxide semiconductor layer; Processing the first insulator and the oxide semiconductor layer into an island shape; depositing a second insulator in a manner covering the first insulator and the oxide semiconductor layer; forming an opening in the second insulator that reaches the oxide semiconductor layer; forming a third insulator in the opening of the second insulator; as well as forming a conductor on the third insulator in the opening of the second insulator, The deposition process of the oxide semiconductor layer comprises the following steps: depositing a first metal oxide; depositing a second metal oxide on the first metal oxide; and depositing a third metal oxide on the second metal oxide, The first metal oxide and the third metal oxide are both deposited by atomic layer deposition using a precursor containing indium and an oxidant, Furthermore, the second metal oxide is deposited by a sputtering method using a sputtering target containing indium.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the sputtering target comprises zinc, And the sputtering method is performed in an oxygen-containing atmosphere.

17. The method for manufacturing a semiconductor device according to claim 15, In the atomic layer deposition method, the substrate is heated at a temperature of 100° C. or higher and 350° C. or lower.

18. The method for manufacturing a semiconductor device according to claim 15, In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a formed surface of the oxide semiconductor layer are confirmed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

19. The method for manufacturing a semiconductor device according to claim 15, wherein no clear boundary is observed between the first metal oxide and the second metal oxide, And no clear boundary is observed between the second metal oxide and the third metal oxide.

20. The method for manufacturing a semiconductor device according to claim 15, The temperature of the heat treatment is 350° C. or higher and 550° C. or lower.

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