Semiconductor device and forming method thereof

Abstract

A method of forming a semiconductor device includes depositing a target metal layer in an opening. Deposition of the target metal layer includes performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles includes: flowing a first precursor in the opening; after flowing the first precursor, flowing a second precursor in the opening; and flowing the reactant in the opening. A first precursor is attached to the upper surface in the opening and a second precursor is attached to the remaining surface in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. As the semiconductor industry moves further toward increasing device density, higher performance, and lower cost, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field effect transistors (CFETs). However, as the minimum feature size decreases, additional components are introduced. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming an opening in the semiconductor device; and depositing a target metal layer in the opening, wherein depositing the target metal layer comprises implementing multiple deposition cycles, and wherein an initial deposition cycle of the multiple deposition cycles comprises: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; after flowing the first precursor, flowing a second precursor in the opening, wherein the second precursor is attached to a remaining surface in the opening, and wherein the first precursor does not react with the second precursor; and flowing a reactant in the opening, wherein the reactant reacts with the second precursor at a rate greater than the rate at which the reactant reacts with the first precursor.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a dummy gate stack around a plurality of nanostructures above a substrate, wherein the plurality of nanostructures are alternately stacked with a plurality of dummy nanostructures; forming a lower source / drain region above the substrate, wherein the lower nanostructures of the plurality of nanostructures extend between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein the upper nanostructures of the plurality of nanostructures extend between the upper source / drain regions; removing the dummy gate stack and the plurality of dummy nanostructures to define an opening; and performing the step of: A deposition process is provided to form a lower work function metal (WFM) layer in the openings around the plurality of nanostructures, wherein an initial deposition cycle of the first deposition process comprises: flowing a first precursor in the openings, wherein the first precursor is attached to an upper surface in the openings; after flowing the first precursor, flowing a second precursor in the openings, wherein the second precursor is attached to a lower surface in the openings, and wherein the first precursor has a higher adhesion coefficient than the second precursor; and flowing a third precursor in the openings, wherein the third precursor reacts with the second precursor at a rate greater than that of the third precursor with the first precursor.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a lower nanostructure extending between lower source / drain regions; an upper nanostructure extending between upper source / drain regions, wherein the upper nanostructure is disposed above the lower nanostructure, and wherein the upper source / drain regions are disposed above the lower source / drain regions; a lower gate electrode located around the lower nanostructure, wherein the lower gate electrode includes halide residues, and wherein a concentration of the halide residues in the lower gate electrode decreases in a direction toward a bottom surface of the lower gate electrode; and an upper gate electrode located around the upper nanostructure, wherein the upper gate electrode is disposed above the lower gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A perspective view of an exemplary stacked transistor (eg, CFET) is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a diagram of an intermediate stage in the fabrication of a stacked transistor according to some embodiments.

[0010] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E is a flow chart of an exemplary process for forming a gate electrode of a stacked transistor according to some embodiments.

[0011] Fig.13 The differences in adhesion coefficients of different deposition precursors according to some embodiments are shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] A stacked transistor structure and a method for forming the same are provided. In various embodiments, the stacked transistor includes a gate electrode having one or more work function metal (WFM) layers. The WFM layers can be deposited using a chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) process, wherein multiple deposition cycles are performed.

[0015] The initial deposition cycle includes flowing a first precursor and a second precursor into a gate opening for depositing a WFM layer. The first precursor may be, for example, a metal halide having a relatively high adhesion coefficient, and the second precursor may be, for example, a carbonyl metal having a relatively low adhesion coefficient. Due to different adhesion coefficients and by controlling one or more deposition parameters (e.g., flow rate and / or flow time), the first precursor may be primarily attached to the upper surface within the gate opening, and the second precursor may be attached to the remaining surface (e.g., primarily the lower surface) within the gate opening. After the first precursor and the second precursor flow into the gate opening, a reactant (sometimes referred to as a third precursor) then flows into the gate opening. The reactant may react with the second precursor (e.g., along the bottom of the gate opening) at a higher rate than the first precursor (e.g., along the top of the gate opening). For example, one or more process parameters may be controlled to increase the reaction with the second precursor and / or reduce the reaction with the first precursor. In this way, the first precursor may be used as a self-inhibiting agent that reduces the formation of the WFM at the top surface of the gate opening when the WFM is formed in the bottom of the opening.

[0016] The deposition cycles may continue until the desired thickness of the WFM is deposited. Each of the subsequent deposition cycles includes flowing at least the second precursor and the reactant. Certain deposition cycles (e.g., every other cycle, every third cycle, etc.) may also include flowing the first precursor to reduce growth at the top of the gate opening. Thus, the WFM layer may grow primarily from the bottom of the gate opening to the top of the gate opening in a bottom-up, seamless deposition process.

[0017] Embodiments can achieve one or more advantages. For example, various embodiments provide methods for achieving seamless gap fill in complex geometries (e.g., within gate openings). The resulting seamless structure (e.g., gate stack) can provide lower resistance, which improves device performance. In addition, in stacked transistors, the WFM of the lower gate stack can be etched back, and the seamless gate stack provides improved control during the etch-back process. For example, etching a seamless gate stack can provide an improved etch profile and improved depth uniformity. Therefore, embodiments allow for increased ease of processing, improved processing control, and improved electrical performance.

[0018] Figure 1 An example of a stacked transistor 10 (including FETs (transistors) 10U and 10L) is shown in accordance with some embodiments. Figure 1 It is a three-dimensional view, and some components of the stacked transistors are omitted for clarity of illustration.

[0019] The stacked transistor includes a plurality of vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 is used as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be applicable to other types of transistors (e.g., finFETs, etc.).

[0020] The gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. The gate electrode 80 (including the lower gate electrode 80L and the upper gate electrode 80U) is located above the gate dielectric 78. The source / drain region 62 (including the lower source / drain region 62L and the upper source / drain region 62U) is disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may be referred to as a source or a drain, individually or collectively depending on the context. Isolation features (not shown) may be formed to separate the desired source / drain region 62 and / or the desired gate electrode 80.

[0021] Figure 1 Reference cross sections used in later figures are also shown. Cross section AA' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor and in the direction of current flow, for example, between the source / drain regions 62 of the stacked transistor. Cross section BB' is a vertical cross section perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 80 of the stacked transistor. For clarity, subsequent figures may refer to these reference cross sections.

[0022] Figures 2 to 11 A stacked transistor (eg, Figure 1 A cross-sectional view of an intermediate stage in the formation of (schematically shown in ). Figure 2 Provides similar Figure 1 Stereoscopic diagram. Figure 3 , Figure 4 , Figure 5A and Fig.11 shows along with Figure 1 A vertical cross-sectional view of a similar cross-section to the vertical reference cross-section AA'. Figure 5B , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 shows along with Figure 1 A cross-sectional view of a cross section similar to the vertical reference cross section BB'.

[0023] Various embodiments are described below in a specific context, namely, depositing a gate material (e.g., WFM) in a stacked transistor having a stacked nanostructure FET. In other embodiments, the stacked transistor may have a different type of transistor (e.g., finFET). In still other embodiments, the described gapfill methods may be applicable to filling any trench or opening and are not limited to forming a gate structure. For example, the embodiment gapfill methods may be applicable to forming interconnect structures, contact structures, and the like, including filling conductive via openings, conductive line trench openings, sheet spacers, holes, and the like. The surface material (e.g., substrate) on which the embodiment gapfill method deposits the metal layer may be any suitable material, such as a dielectric material (e.g., HfO 2 、ZrO 2 、TiO 2 、SiO 2 , SiN) or non-conductive materials (e.g., silicon, germanium, silicon germanium, doped silicon, etc.). Embodiments may be used to deposit gate materials (e.g., work function metal (WFM) layers) for gate stacks as described below, but embodiments may also be used to deposit any type of target metal. For example, embodiments may be applicable to forming pure metals (e.g., W, Mo, Pt, Pd, Co, Ru, Rh, Ag, Au, Cu, Ni, Fe, Ti, etc.), alloys (e.g., TiN, NiB, NiP, CoNiP, CoNiB, CoMnP, CoNiMnP, CoWP, CoWB, CoNiReP, CoB, CoP, CoFeB, CoNiFeB, FeP, etc.), combinations thereof, etc. Therefore, it should be understood that the various embodiments are not limited to the specific contexts described below.

[0024] exist Figure 2 In the present invention, a wafer is provided, which includes a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with a p-type or n-type dopant) or undoped. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 20 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0025] Semiconductor strips 28 extending upward from the semiconductor substrate 20 are formed. Each of the semiconductor strips 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multilayer stack 22. The stacked assembly of the multilayer stack 22 is referred to as a nanostructure hereinafter. Specifically, the multilayer stack 22 includes a pseudo nanostructure 24A, a pseudo nanostructure 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. The pseudo nanostructure 24A and the pseudo nanostructure 24B may be further collectively referred to as a pseudo nanostructure 24, and the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U may be further collectively referred to as a semiconductor nanostructure 26.

[0026] The pseudo nanostructure 24A is formed of a first semiconductor material, and the pseudo nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The first semiconductor material and the second semiconductor material have high etching selectivity to each other. Therefore, in a subsequent process, the pseudo semiconductor layer 24B can be removed at a faster rate than the pseudo semiconductor layer 24A.

[0027] The semiconductor nanostructure 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from the candidate semiconductor material of the substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be formed of the same semiconductor material, or can be formed of different semiconductor materials. In addition, the first semiconductor material and the second semiconductor material of the pseudo nanostructure 24 have high etching selectivity to the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. As a specific example, the pseudo semiconductor nanostructure 24A is formed of silicon germanium, the semiconductor layer 26 is formed of silicon, and the pseudo semiconductor nanostructure 24B can be formed of germanium or silicon germanium with a higher atomic percentage of germanium than the semiconductor nanostructure 24A. For the pseudo semiconductor nanostructure 24A, the pseudo semiconductor nanostructure 24B and the semiconductor nanostructure 26, other combinations of semiconductor materials are also possible.

[0028] The lower semiconductor nanostructure 26L will provide a channel region for the lower nanostructure FET of the stacked transistor. The upper semiconductor nanostructure 26U will provide a channel region for the upper nanostructure FET of the stacked transistor. The semiconductor nanostructure 26 immediately above / below (e.g., in contact with) the pseudo nanostructure 24B may be used for isolation and may or may not be used as a channel region for the stacked transistor. Subsequently, the pseudo nanostructure 24B will be replaced with an isolation structure that defines the boundary of the lower nanostructure FET and the upper nanostructure FET.

[0029] To form semiconductor strips 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) may be deposited over semiconductor substrate 20. The layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by processes such as chemical vapor deposition (CVD) processes or atomic layer deposition (ALD) processes, etc. A patterning process may then be applied to the layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material and semiconductor substrate 20 to define semiconductor strips 28, which include semiconductor strips 20', pseudo-nanostructures 24, and semiconductor nanostructures 26.

[0030] The semiconductor fins and nanostructures may be patterned by any suitable method. For example, the patterning process may include one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etching mask for the patterning process to etch the layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material and the semiconductor substrate 20. Etching may be implemented by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0031] Likewise Figure 2As shown, STI regions 32 are formed above substrate 20 and between adjacent semiconductor strips 28. STI regions 32 may include a dielectric liner and a dielectric material above the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof. The formation of STI regions 32 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like, to remove excess portions of the dielectric material. The deposition process may include ALD, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, STI regions 32 include silicon oxide formed by an FCVD process, followed by an annealing process. Then, the dielectric layer is recessed to define STI regions 32. The dielectric layer may be recessed so that the upper portion of semiconductor strips 28 (including multilayer stack 22) protrudes above the remaining STI regions 32.

[0032] After forming the STI region 32, a dummy gate stack 42 may be formed over and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed of or include, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-SiGe), etc. A mask layer 40, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the planarized dummy gate layer 38. Next, mask layer 40 may be patterned by photolithography and etching processes to form a mask, which is then used to etch and pattern dummy gate layer 38, and possibly dummy dielectric layer 36. Mask layer 40, dummy gate layer 38, and the remaining portions of dummy dielectric layer 36 form dummy gate stack 42.

[0033] exist Figure 3, a gate spacer 44 and a source / drain recess 46 are formed. First, a gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc., which can be formed by a deposition process such as CVD, ALD, etc.

[0034] Subsequently, source / drain recesses 46 are formed in semiconductor strips 28. Source / drain recesses 46 are formed by etching and may extend through multilayer stack 22 and into semiconductor strips 20'. The bottom surface of source / drain recesses 46 may be located above, below, or at a level flush with the top surface of STI region 32. During the etching process, gate spacers 44 and dummy gate stack 42 mask portions of semiconductor strips 28. Etching may include a single etching process or multiple etching processes. When source / drain recesses 46 reach a desired depth, a timed etching process may be used to stop etching of source / drain recesses 46.

[0035] exist Figure 4 In the embodiment of the present invention, an internal spacer 54 and a dielectric isolation layer 56 are formed. The formation of the internal spacer 54 and the dielectric isolation layer 56 may include an etching process that laterally etches the pseudo nanostructure 24A and removes the pseudo nanostructure 24B. The etching process may be isotropic and may be selective to the material of the pseudo nanostructure 24, so that the pseudo nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective to the material of the pseudo nanostructure 24B, so that the pseudo nanostructure 24B is etched at a faster rate than the pseudo nanostructure 24A. In this way, the pseudo nanostructure 24B may be completely removed from between the lower semiconductor nanostructure 26L (common) and the upper semiconductor nanostructure 26U (common) without completely removing the pseudo nanostructure 24A. In some embodiments, where the pseudo nanostructure 24B is formed of germanium or silicon germanium with a high atomic percentage of germanium, the pseudo nanostructure 24A is formed of silicon germanium with a low atomic percentage of germanium, and the semiconductor nanostructure 26 is formed of silicon without germanium, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the dummy gate stack 42 wraps around the sidewalls of the semiconductor nanostructure 26 (see Figure 2 ), so the dummy gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse when the dummy nanostructure 24B is removed. In addition, although the sidewalls of the dummy nanostructure 24A are shown to be straight after etching, the sidewalls may be concave or convex.

[0036] The internal spacer 54 is formed on the sidewall of the recessed pseudo nanostructure 24A, and the dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively) and the lower semiconductor nanostructure 26L (collectively). As described in more detail later, the source / drain region will be formed in the source / drain groove 46, and the pseudo nanostructure 24A will be replaced with a corresponding gate structure. The internal spacer 54 serves as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for forming a gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively) from the lower semiconductor nanostructure 26L (collectively). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

[0037] The internal spacer 54 and the dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the pseudo nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon oxycarbon, silicon oxynitride, etc. Other low dielectric constant (low-k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion that remains in the sidewall of the pseudo nanostructure 26A (thus forming the internal spacer 54), and has a portion that remains between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0038] Likewise Figure 4 As shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L and does not contact the upper semiconductor nanostructure 26U. The internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0039] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surface (e.g., sidewall) of the upper semiconductor nanostructure 26U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain regions 62L, the mask over the upper semiconductor nanostructures 26U may then be removed.

[0040] As a result of the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surfaces of the lower epitaxial source / drain regions 62L have facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0041] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source / drain regions 62L. The first CESL 66 may be formed of a dielectric material having a high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0042] The formation process may include: depositing a conformal CESL layer: depositing a material for the first ILD 68: followed by a planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0043] An upper epitaxial source / drain region 62U is then formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U may be selected from the same candidate material group used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In an embodiment where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U may be opposite to the conductivity type of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U may be doped opposite to the lower epitaxial source / drain region 62L. Optionally, the conductivity types of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L may be the same. The upper epitaxial source / drain regions 62U may be in-situ doped with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U may remain separated after the epitaxial process, or may merge.

[0044] After forming the epitaxial source / drain regions 62U, the second CESL 70 and the second ILD 72 are formed. The materials and the formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail herein. The formation process may include: depositing layers for the CESL 70 and the ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 (if present) or the dummy gate 38 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or the dummy gate 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed so that the top surface of the dummy gate 38 is exposed through the second ILD 72.

[0045] FIG. 5A to FIG. 10 A replacement gate process is shown in which the dummy gate stack 42 and the dummy nanostructure 24A are replaced with the gate stack 90. Figure 5A and Figure 5B The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A to define a gate opening 74 . Figure 5A Shown along Figure 1 A cross-sectional view of section AA, and Figure 5B Shown along Figure 1BB. The pseudo gate stack 42 is removed in one or more etching processes such that the gate opening 74 is defined between the gate spacers 44 and the upper portion of the semiconductor strip 28 is exposed. The remaining portion of the pseudo nanostructure 24A is then removed by etching such that the gate opening 74 extends between the semiconductor nanostructures 26. In the etching process, the pseudo nanostructure 24A is etched at a faster rate than the semiconductor nanostructure 26, the dielectric isolation layer 56, and the internal spacer 54. The etching can be isotropic. For example, when the pseudo nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) and other wet etching processes.

[0046] Then, in Figure 6 In the grooves between the gate spacers 44 (see Fig.11 ) and the exposed semiconductor nanostructure 26, a gate dielectric 78 is deposited. The gate dielectric 78 is conformally formed on the exposed surface of the gate opening 74 (including the semiconductor nanostructure 26 and the gate spacer 44). In some embodiments, the gate dielectric 78 wraps around all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 can be formed on the top surface of the fin 20'; the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26. The gate dielectric 78 can also be formed on the sidewalls of the gate spacer 44 (see Fig.11 ). The gate dielectric 78 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, or the like. The gate dielectric 78 may include a high dielectric constant (high-k) material having a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and a combination thereof. The formation method of the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, or the like, followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single layer of the gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0047] exist Figures 7 to 10 In the embodiment, a lower gate electrode 80L and an upper gate electrode 80U are formed around the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U, respectively. FIG. 12A to FIG. 12E Flowcharts for forming the lower gate electrode 80L and the upper gate electrode 80U according to various embodiments are provided.

[0048] The lower gate electrode 80L may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, and the like. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filler materials. The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function metal (WFM) layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type WFM layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 80L includes a p-type WFM layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 80L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0049] The lower gate electrode 80L may be formed by conformally depositing one or more gate electrode layers such that the gate electrode layers are recessed. Fig. 12A In steps 202 and 204, a lower WFM layer of the lower gate electrode 80L may be formed around the semiconductor nanostructure 26. Depositing the lower WFM layer may include a conformal deposition process such as CVD, ALD, a combination thereof, etc. Fig. 12A As shown in steps 202 and 204 of , the conformal deposition process may include performing N deposition cycles until a desired thickness for the lower WFM layer is achieved, where N is any positive integer. The conformal deposition may be a bottom-up deposition process, as described in more detail below. In some embodiments, prior to the conformal deposition process, an optional inhibitor (e.g., a self-assembled monolayer (SAM) or a small molecule inhibitor (SMI)) may be formed to cover the top surface of the gate dielectric 78 (e.g., Figure 7 78') to further promote the bottom-up directionality of the conformal deposition process. After the conformal deposition process is completed, an optional annealing process may be performed. For example, an inert gas (e.g., Ar, He, N 2 The lower WFM layer is annealed at a temperature in the range of 200° C. to 600° C. in an environment such as a vacuum furnace.

[0050] Now about Figures 7 to 9 , Fig. 12B and Fig. 12C Describe N deposition cycles. Fig. 12BA process flow of an initial deposition cycle of a conformal deposition process for depositing the lower gate electrode 80L (eg, depositing the lower WFM layer of the lower gate electrode 80L) is shown. Fig. 12B Step 202A and Figure 7 , the first precursor 82 flows into the gate opening 74 above the gate dielectric 78. The first precursor 82 can be selected from metal organic compounds, metal halides, metal carbonyl compounds, metal complexes, etc. having a relatively high adhesion coefficient. For example, the first precursor 82 can be a metal halide. In an embodiment where the target metal layer (e.g., the lower WFM layer) is a titanium nitride layer, the first precursor 82 can be TiCl 4 . Due to the relatively high adhesion coefficient of the first precursor 82, the first precursor can accumulate and attach to the upper surface and upper sidewalls in the gate opening 74 (e.g., the upper surface and sidewalls of the gate dielectric 78). The surface concentration of the first precursor 82 can decrease in the direction of arrow 76 toward the bottom of the gate opening 74 / substrate 20. For example, the first precursor 82 can completely saturate the upper surface and upper sidewalls of the gate dielectric 78, and the saturation percentage of the first precursor 82 can be reduced to essentially zero at the bottom surface of the gate opening 74. When flowing the first precursor 82, the depth and coverage profile of the first precursor 82 can be controlled by controlling one or more processing parameters (e.g., precursor dosage, precursor flow time, etc.). After the first precursor 82 is flowed into the chamber, an inert gas (e.g., Ar, He, N 2 etc.) to perform a gas purge to remove excess (eg, unattached) amounts of the first precursor 82 from the processing chamber.

[0051] Next, refer to Fig. 12B Step 202B and Figure 8, the second precursor 84 flows into the gate opening 74, such as above the gate dielectric 78. The second precursor 84 can be selected from metal organic compounds, metal halides, metal carbonyl compounds, metal complexes, etc. with relatively low adhesion coefficients. In some embodiments, the first precursor 82 and the second precursor 84 are both selected from candidate precursors for forming the same target metal (e.g., the material of the lower WFM layer), and the first precursor 82 and the second precursor 84 do not react with each other. For example, the second precursor 84 can be a carbonyl metal. In an embodiment where the target metal layer (e.g., the lower WFM layer) is a titanium nitride layer, the second precursor 84 can be tetrakis(dimethylamino)titanium (TDMAT). Since the top surface in the gate opening 74 is substantially occupied by the first precursor 82, the second precursor 84 can flow toward the bottom of the gate opening 74 and attach to the lower surface and lower sidewalls in the gate opening 74 (e.g., the lower surface and sidewalls of the gate dielectric 78). The relatively low sticking coefficient of the second precursor 84 can further facilitate the flow of the second precursor 84 toward the bottom of the gate opening 74 because the second precursor 84 will not tend to accumulate on the upper surface of the gate opening 74. The surface concentration of the second precursor 84 can increase toward the bottom of the gate opening 74 / substrate 20 in the direction of arrow 76. For example, the second precursor 84 can completely saturate the lower surface and lower sidewalls of the gate opening 74, and the saturation percentage of the first precursor 82 can decrease to substantially zero at the top of the gate opening 74.

[0052] The first precursor 82 may have a higher adhesion coefficient than the second precursor 84 . Fig.13 8 shows the difference in adhesion coefficient between the first precursor 82 and the second precursor 84 according to various embodiments. Specifically, Fig.13 A graph 300 is shown of the percentage of surface coverage achieved by flowing precursors over a blanket substrate as a function of time. Line 302 corresponds to coverage by the first precursor 82 and line 304 corresponds to coverage by the second precursor 84. As can be seen from graph 300 at time T1, neither the first precursor 82 (as shown by line 302) nor the second precursor 84 (as shown by line 304) may achieve 100% surface convergence (sometimes referred to as saturated bonding). However, at time T1, the percentage of surface coverage of the first precursor 82 may be higher than the percentage of surface coverage of the second precursor 84. Subsequently, at time T2, the first precursor 82 may achieve saturation on the blanket substrate, while the second precursor 84 has not yet achieved saturation on the blanket substrate. At time T3, after time T2, both the first precursor 82 and the second precursor 84 have achieved saturation on the blanket substrate. As shown by Fig.13As can be seen, the relatively high adhesion coefficient of the first precursor 82 allows the first precursor 82 to attach to the surface at a faster rate and reach surface saturation faster than the second precursor 84 compared to the relatively low adhesion coefficient of the second precursor 84. Therefore, the first precursor 82 is more likely to adhere to the upper surface of the gate opening 74, and the second precursor 84 can then flow into the gate opening 74 to cover the remaining surface (lower surface) of the gate opening 74. In some embodiments, the flow time of the first precursor 82 can be less than T2, so that the first precursor 82 only partially saturates the surface of the gate opening 74, and the flow time of the second precursor 84 can be greater than T3, so that the remaining surface of the gate opening 74 is fully saturated by the second precursor 84. For example, the second precursor 84 can be overdosed in the gate opening 74 so that the surface of the gate opening 74 is fully saturated by the first precursor 82 and the second precursor 84.

[0053] After the second precursor 84 has been flowed into the chamber for a desired time to achieve the desired surface coverage, the chamber may be heated with an inert gas (e.g., Ar, He, N 2 The process chamber may be subjected to a gas purge (e.g., a gas purge, such as a gas purge, etc.) to remove excess (e.g., unattached) amounts of the first precursor 82 from the process chamber. Thus, the surface of the gate opening 74 may have a precursor coverage monolayer from the combination of the first precursor 82 (at the top of the opening 74) and the second precursor 84 (at the bottom of the opening 74).

[0054] Next, refer to Fig. 12B Step 202C and Fig. 9 , a first reactant 86 (sometimes referred to as a third precursor) flows into the gate opening 74, such as above the monolayer of the first precursor 82 and the second precursor 84. The reactant can be selected from materials that react with the first precursor 82 and the second precursor 84 to form a portion (e.g., a monolayer) of the target metal layer 80' (e.g., the lower WFM layer). For example, in the case where the target metal layer is a titanium nitride layer, the first precursor 82 is TiCl 4 , the second precursor 84 is TDMAT, and the first reactant 86 can be ammonia (NH 3 ) or hydrazine (N 2 H 4). The process conditions for flowing the first reactant 86 can be controlled so that the first reactant 86 reacts with the second precursor 84 at a greater rate than with the first precursor 82. For example, the temperature of the processing chamber when flowing the first reactant 86 can be controlled to promote the reaction between the second precursor 84 and the first reactant 86 while limiting the reaction between the first precursor 82 and the first reactant 86. In some embodiments, the temperature of the processing chamber when flowing the first reactant 86 can be in the range of 300° C. to 350° C. to promote the reaction between the second precursor 84 and the first reactant 86 while limiting the reaction between the first precursor 82 and the first reactant 86. Other processing conditions that can be controlled include the presence or absence of a plasma, the presence or absence of an ion beam, and / or the presence of a reagent that is selective to the first precursor 82 when flowing the first reactant 86. In various embodiments, the materials of the first precursor 82 and the second precursor 84 can also be selected so that a selective reaction can be achieved when the first reactant 86 flows by controlling one or more of the processing parameters discussed above. Thus, a portion of the target metal layer 80' may be substantially formed in the bottom of the gate opening 74, and the target metal layer 80' may not be formed at the top of the gate opening 74 or may have only limited formation at the top of the gate opening 74. The first precursor 82 at the top surface in the gate opening 74 may serve as a self-inhibiting agent that reduces the formation of the target metal layer 80' at the top of the gate opening 74. For example, the first precursor 82 may limit the growth of the target metal layer 80' at the top of the gate opening 74, so that the target metal layer 80' is mainly formed in the bottom of the gate opening 74. Subsequently, the inert gas (e.g., Ar, He, N 2 etc.) to perform a gas purge to remove excess (eg, unreacted) amounts of the first reactant 86 from the processing chamber.

[0055] Thus, the initial cycle of the deposition process for forming the layers of the lower gate electrode 80L is completed. The process for forming the lower gate electrode 80L can be continued by performing additional deposition cycles for the lower WFM layer ( Fig. 12A 202 and 204) until the desired thickness of the lower WFM layer is achieved. Each deposition cycle may be based at least on Fig. 12CA process flow in which a second precursor 84 flows over a target metal layer 80' (step 202B), and then a first reactant 86 flows to react with the second precursor 84 and form an additional portion (e.g., a monolayer) of the target metal layer 80'. In some embodiments, grain boundaries may be observed between portions of the target metal layer 80' formed in different deposition cycles. After the initial deposition cycle, the second precursor 84 may attach to the exposed surface of the target metal layer 80' formed in the previous deposition cycle and saturate the exposed surface of the target metal layer 80' formed in the previous deposition cycle. In this way, the target metal layer 80' (e.g., the lower WFM layer) of the lower gate electrode may be deposited in a seamless process from bottom to top. The first reactant 86 may also react slowly with the first precursor 82, albeit at a slower rate than with the second precursor 84. For example, the first reactant 86 may react with the first precursor 82 across multiple deposition cycles to form an amount (e.g., a monolayer) of a single deposition cycle of the target metal layer 80'. In this manner, over a plurality of cycles, the bottom-up deposition process may grow the target metal layer 80 ′ (eg, the lower WFM layer of the lower gate electrode 80L) from the bottom of the gate opening 74 to the top of the gate opening 74 .

[0056] In some embodiments, the first precursor 82 may also be flowed in one or more of the subsequent deposition cycles to reduce the growth rate of the target metal layer 80' at the top of the gate opening 74. For example, each deposition cycle for the lower WFM layer may be based on Fig. 12B A process flow (wherein the first precursor 82, the second precursor 84 and the first reactant 86 flow in sequence) or Fig. 12C A process flow in which the first precursor 82 is omitted and only the second precursor 84 and the first reactant 86 are flowed. The first precursor 82 may be flowed every other deposition cycle, every third deposition cycle, and so on.

[0057] In some embodiments, the lower gate electrode 80L may be deposited to completely fill or overfill the gate opening 74. In some embodiments, the lower gate electrode 80L may be deposited to partially fill the gate opening 74, but the lower gate electrode 80L may be deposited to an unacceptably high level. For example, the lower gate electrode 80L may be deposited around the upper semiconductor nanostructure 26U as well as the lower semiconductor nanostructure 26L. Thus, after depositing one or more layers of the lower gate electrode 80L, the lower gate electrode 80L may be deposited to a substantially lower level. Fig. 12AIn step 206 of , an etch-back process is performed to recess the lower gate electrode 80L to a level below the upper semiconductor nanostructure 26U. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be implemented to recess the gate electrode layer of the lower gate electrode 80L. The etching may be isotropic or anisotropic. Due to the seamless bottom-up deposition process used to form the lower gate electrode 80L, the etch-back process may be implemented with improved control, such as improved depth control. Therefore, the profile of the etched-back lower gate electrode 80L may be improved. Etching the lower gate electrode 80L may remove a portion of the lower gate electrode 80L located around the upper semiconductor nanostructure 26U and expose the upper semiconductor nanostructure 26U. In an embodiment in which the lower gate electrode 80L is deposited to overfill the gate opening 74, a planarization process (e.g., CMP) may be performed prior to the etching process. In such an embodiment, the planarization process removes a portion of the lower gate electrode 80L deposited above the gate opening 74.

[0058] In some embodiments, an isolation layer (not explicitly shown) may be optionally formed on the lower gate electrode 80L, such as Fig. 12A The isolation layer is used as an isolation member between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, combinations thereof, etc.) and then recessing the dielectric material to expose the upper semiconductor nanostructure 26U. The resulting structure is Fig.10 Shown in.

[0059] Then, an upper gate electrode 80U is formed on the isolation layer (if any) or the lower gate electrode 80L described above. Fig. 12A 210 and 212). The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U wraps the upper semiconductor nanostructure 26U. The upper gate electrode 80U can be formed of the same candidate material and candidate process used to form the lower gate electrode 80L. For example, the upper gate electrode 80U can include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed of materials suitable for the device type of the upper nanostructure FET. In an embodiment where the stacked transistor is a CFET device, the device type of the upper gate electrode 80U can be opposite to the device type of the lower gate electrode 80L. For example, the upper gate electrode 80U can be n-type and the lower gate electrode 80L is p-type, or the upper gate electrode 80U can be p-type and the lower gate electrode 80L is n-type. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U can include any number of WFM layers and / or any number of barrier layers.

[0060] In various embodiments, the layers of the upper gate electrode 80U may be deposited using a bottom-up deposition process similar to those described above with respect to the lower gate electrode 80L. For example, the upper WFM layer of the gate electrode 80U may be deposited using a conformal deposition process, such as ALD, CVD, or a combination thereof. The conformal deposition process may include performing M deposition cycles until a desired thickness of the upper WFM layer is achieved, where M is any positive integer ( Fig. 12A The conformal deposition may be a bottom-up deposition process similar to that described above with respect to depositing the lower gate electrode 80L. In some embodiments, prior to the conformal deposition process, an optional inhibitor (e.g., a self-assembled monolayer (SAM) or a small molecule inhibitor (SMI)) may be formed to cover the top surface of the gate dielectric 78 to further promote the bottom-up directionality of the conformal deposition process. After the conformal deposition process is completed, an optional annealing process may be performed. For example, the conformal deposition may be performed in an inert gas (e.g., Ar, He, N 2 The upper WFM layer is annealed at a temperature in the range of 200° C. to 600° C. in an environment such as a molten-crystal (eg, a molten-crystal) environment.

[0061] The initial deposition of the M deposition cycles for forming the upper WFM layer of the upper gate electrode 80U may be based on Fig.12D For example, the initial deposition process may include sequentially flowing a fourth precursor having a relatively high adhesion coefficient (similar to the first precursor 82 described above), a fifth precursor having a relatively low adhesion coefficient (similar to the second precursor 84 described above), and a second reactant (similar to the first reactant 86 described above, also referred to as a sixth precursor in some embodiments). In a specific embodiment, the fourth precursor is a metal halide, and the fifth precursor is a metal carbonyl. According to the above in Figure 7 and Figure 8 The fourth precursor is attached to the upper surface in the gate opening 74, and the fifth precursor is attached to the lower surface in the gate opening 74 (eg, the upper surface of the lower gate electrode 80L). Then, according to the mechanism described above in Fig. 9 The second reactant reacts with the fifth precursor at a greater rate than the fourth precursor by the mechanism described in the previous section. After the initial deposition cycle, each subsequent deposition cycle for the upper WFM layer can be based on Fig.12D A process flow (wherein the fourth precursor, the fifth precursor and the second reactant flow in sequence) or Fig.12E A process flow of (wherein the fourth precursor is omitted and only the fifth precursor and the second reactant are flowed). The fourth precursor may be flowed every other deposition cycle, every third deposition cycle, etc. In this manner, the layers of the upper gate electrode 80U may be grown in a bottom-up seamless deposition process for improved electrical performance (e.g., lower resistance).

[0062] In some embodiments, only the WFM layer of the lower gate electrode 80L and the upper gate electrode 80U is deposited using the above process. Subsequently, an optional glue layer ( Fig. 12A The glue layer and fill metal may be formed by any conformal deposition process, such as CVD, ALD, combinations thereof, etc. The deposition process for forming the glue layer and fill metal may or may not be based on the bottom-up seamless process described above.

[0063] In addition, a removal process is performed to make the top surface of the upper gate electrode 80U flush with the second ILD 72. The removal process for forming the gate dielectric 78 can be the same removal process as the removal process for forming the upper gate electrode 80U. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. can be utilized. In an embodiment where the planarization process includes an etch-back process, any acceptable etching process such as dry etching, wet etching, etc. or a combination thereof can be implemented to recess the gate electrode layer of the upper gate electrode 80U. The etching can be isotropic or anisotropic. Due to the seamless bottom-up deposition process for forming the upper gate electrode 80U, the etch-back process can be implemented with improved control, such as improved depth control. Therefore, the profile of the etched-back upper gate electrode 80U can be improved. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including upper gate electrode 80U and / or lower gate electrode 80L) may be collectively referred to as a "gate structure" 90 (including upper gate structure 90U and lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., top surface, sidewall, and bottom surface) of the channel region of semiconductor nanostructure 26 (see Figure 1 ). The lower gate structure 90L may also extend along the sidewalls and / or top surfaces of the semiconductor fin 20 ′.

[0064] Because the first precursor and the second precursor are both used to form at least the WFM layer of the lower gate electrode 80L, and / or the fourth precursor and the fifth precursor are used to form at least the WFM layer of the upper gate electrode 80U, precursor residues from each of the first precursor 82 (and similarly the fourth precursor) and the second precursor 84 (and similarly the fifth precursor) may remain in the lower gate electrode 80L and the upper gate electrode 80U. The precursor residues may include halogens (e.g., chlorine), carbon, oxygen, nitrogen, etc., and the concentration of the precursor residues may vary and have a gradient along arrow 76. For example, when a metal halide is used as the first precursor 82 (or the fourth precursor), the concentration of the halide residue (e.g., Cl) in the lower gate electrode 80L (and / or the upper gate electrode 80U) may decrease in the direction along arrow 76 toward the substrate 20. As another example, when a carbonyl metal is used as the second precursor 84 (or the fifth precursor), the concentration of carbonyl residues (e.g., carbon and / or oxygen) in the lower gate electrode 80L (and / or the upper gate electrode 80U) may increase in a direction along arrow 76 toward the substrate 20.

[0065] Next reference Fig.11 , a gate mask 92 is formed over the gate stack 90. ​​The formation process may include: recessing the gate stack 90; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc.; and performing a planarization process to remove excess portions of the dielectric material located over the second ILD 72.

[0066] Then, a metal semiconductor alloy region 94 and a source / drain contact 96 are formed through the second ILD 72 to electrically couple to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. As an example of forming the source / drain contact 96, an opening through the second ILD 72 and the second CESL 70 is formed using acceptable photolithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process may be implemented to remove excess material from the top surface of the gate spacer 44 and the second ILD 72. The remaining liner and conductive material form a source / drain contact 96 in the opening. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, etc. is utilized. After the planarization process, top surfaces of the gate spacers 44 , the second ILD 72 , and the source / drain contacts 96 are substantially coplanar (within process variations).

[0067] Optionally, a metal semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal semiconductor alloy region 94 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of a metal silicide and a metal germanide, etc. The metal semiconductor alloy region 94 may be formed by depositing a metal in an opening for the source / drain contact 96 before the material of the source / drain contact 96 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the source / drain region 62 to form a low-resistance metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings for the source / drain contacts 96, such as from the surface of the metal semiconductor alloy region 94. The material of the source / drain contacts 96 may then be formed on the metal semiconductor alloy region 94.

[0068] Then, the ESL 104 and the third ILD 106 are formed. In some embodiments, the ESL 104 may include a dielectric material having a high etch selectivity relative to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0069] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming a gate contact 108 and a source / drain via 110, an opening for the gate contact 108 and the source / drain via 110 is formed through the third ILD 106 and the ESL 104. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesive layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 106. The remaining liner and conductive material form a gate contact 108 and a source / drain via 110 in the opening. The gate contact 108 and the source / drain via 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 may be formed in different cross sections, which may avoid shorting of the contacts.

[0070] A front side interconnect structure 114 is formed on the device layer 112. The front side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive features 118 in the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc., or a combination thereof, over the low-k dielectric material. The dielectric layer 116 may also include a polymer layer.

[0071] Conductive features 118 may include wires and vias, which may be formed using a damascene process. Conductive features 118 may include metal lines and metal vias, which include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. There may also be aluminum pads located above and electrically connected to the metal lines and vias. In some embodiments, contacts to the lower gate stack 90L and the lower source / drain region 62L may be made through the back side of the device layer 112 (e.g., the side opposite the front side interconnect structure 114).

[0072] In some embodiments, a method of forming a semiconductor device includes: forming an opening in the semiconductor device; and depositing a target metal layer in the opening, wherein depositing the target metal layer includes performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles includes: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; after flowing the first precursor, flowing a second precursor in the opening, wherein the second precursor is attached to a remaining surface in the opening, and wherein the first precursor does not react with the second precursor; and flowing a reactant in the opening, wherein the reactant reacts with the second precursor at a rate greater than that of the reactant with the first precursor. Optionally, in some embodiments, the first precursor has a greater adhesion coefficient than the second precursor. Optionally, in some embodiments, the first precursor is a metal halide and the second precursor is a metal carbonyl. Optionally, in some embodiments, after flowing the first precursor, the concentration of the first precursor decreases in a direction toward the bottom of the opening. Optionally, in some embodiments, after flowing the second precursor, the concentration of the second precursor increases in a direction toward the bottom of the opening. Optionally, in some embodiments, the method further comprises controlling a process parameter while flowing the reactant so that the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor. Optionally, in some embodiments, the process parameter comprises a process temperature, the presence or absence of a plasma, the presence or absence of an ion beam, the presence of a reagent selective to the first precursor, or a combination thereof. Optionally, in some embodiments, after an initial deposition cycle, each subsequent deposition cycle of a plurality of deposition cycles comprises: flowing the second precursor in the opening; and flowing the reactant in the opening. Optionally, in some embodiments, after an initial deposition cycle, a subsequent deposition cycle of a plurality of deposition cycles comprises: flowing the first precursor in the opening before flowing the second precursor in the opening. Optionally, in some embodiments, the initial deposition cycle further comprises: performing a first inert gas purge between flowing the first precursor and flowing the second precursor; performing a second inert gas purge between flowing the second precursor and flowing the reactant; and performing a third inert gas purge after flowing the reactant.

[0073] In some embodiments, the method includes: forming a dummy gate stack around a plurality of nanostructures above a substrate, wherein the plurality of nanostructures are alternately stacked with a plurality of dummy nanostructures; forming a lower source / drain region above the substrate, wherein a lower nanostructure of the plurality of nanostructures extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein an upper nanostructure of the plurality of nanostructures extends between the upper source / drain regions; removing the dummy gate stack and the plurality of dummy nanostructures to define an opening; and performing a first deposition process to form a lower work function metal (WFM) layer in the opening around the plurality of nanostructures. An initial deposition cycle of the first deposition process includes: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; after flowing the first precursor, flowing a second precursor in the opening, wherein the second precursor is attached to a lower surface in the opening, and wherein the first precursor has a higher adhesion coefficient than the second precursor; and flowing a third precursor in the opening, wherein the third precursor reacts with the second precursor at a greater rate than the third precursor reacts with the first precursor. Optionally, in some embodiments, the method further includes: recessing the lower WFM layer in the opening; and performing a second deposition process to form an upper WFM layer in the opening around the upper nanostructure and over the lower WFM layer. Optionally, in some embodiments, an initial deposition cycle of the second deposition process comprises: flowing a fourth precursor in the opening, wherein the fourth precursor is attached to an upper surface in the opening; after flowing the fourth precursor, flowing a fifth precursor in the opening, wherein the fifth precursor is attached to a remaining surface in the opening, and wherein the fourth precursor has a higher adhesion coefficient than the fifth precursor; and flowing a sixth precursor in the opening, wherein the sixth precursor reacts with the fifth precursor at a rate greater than the sixth precursor reacts with the fourth precursor. Optionally, in some embodiments, the method further comprises: depositing a glue layer over the upper WFM layer; and depositing a filler metal over the glue layer. Optionally, in some embodiments, the first precursor is a metal halide, and wherein the second precursor is a metal carbonyl. Optionally, in some embodiments, the lower WFM layer comprises titanium nitride, wherein the first precursor is TiCl 4 , wherein the second precursor is tetrakis(dimethylamino)titanium (TDMAT), and wherein the third precursor is NH 3 or N 2 H 4 Optionally, in some embodiments, after an initial deposition cycle of the first deposition process, each subsequent deposition cycle of the first deposition process includes: flowing the second precursor in the opening; and flowing the third precursor in the opening.

[0074] In some embodiments, a semiconductor device includes: a lower nanostructure extending between the lower source / drain regions; an upper nanostructure extending between the upper source / drain regions, wherein the upper nanostructure is disposed above the lower nanostructure, and wherein the upper source / drain regions are disposed above the lower source / drain regions; a lower gate electrode disposed around the lower nanostructure, wherein the lower gate electrode includes a halide residue, and wherein the concentration of the halide residue in the lower gate electrode decreases in a direction toward a bottom surface of the lower gate electrode; and an upper gate electrode disposed around the upper nanostructure, wherein the upper gate electrode is disposed above the lower gate electrode. Optionally, in some embodiments, the lower gate electrode further includes a carbonyl residue, and wherein the concentration of the carbonyl residue increases in a direction toward a bottom surface of the lower gate electrode. Optionally, in some embodiments, the halide residue is chlorine, and wherein the carbonyl residue is carbon or oxygen.

[0075] Some embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming an opening in the semiconductor device; and depositing a target metal layer in the opening, wherein depositing the target metal layer comprises implementing multiple deposition cycles, and wherein an initial deposition cycle of the multiple deposition cycles comprises: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; after flowing the first precursor, flowing a second precursor in the opening, wherein the second precursor is attached to a remaining surface in the opening, and wherein the first precursor does not react with the second precursor; and flowing a reactant in the opening, wherein the reactant reacts with the second precursor at a rate greater than the rate at which the reactant reacts with the first precursor.

[0076] In some embodiments, the first precursor has a greater adhesion coefficient than the second precursor. In some embodiments, the first precursor is a metal halide and the second precursor is a metal carbonyl. In some embodiments, after flowing the first precursor, the concentration of the first precursor decreases in a direction toward the bottom of the opening. In some embodiments, after flowing the second precursor, the concentration of the second precursor increases in a direction toward the bottom of the opening. In some embodiments, the method further comprises controlling a process parameter while flowing the reactant so that the reactant reacts with the second precursor at a rate greater than the reactant reacts with the first precursor. In some embodiments, the process parameter comprises a process temperature, the presence or absence of a plasma, the presence or absence of an ion beam, the presence of a reagent selective to the first precursor, or a combination thereof. In some embodiments, after the initial deposition cycle, each subsequent deposition cycle of the plurality of deposition cycles comprises: flowing the second precursor in the opening; and flowing the reactant in the opening. In some embodiments, after the initial deposition cycle, a subsequent deposition cycle of the plurality of deposition cycles comprises: flowing the first precursor in the opening before flowing the second precursor in the opening. In some embodiments, the initial deposition cycle further comprises: performing a first inert gas purge between flowing the first precursor and flowing the second precursor; performing a second inert gas purge between flowing the second precursor and flowing the reactant; and performing a third inert gas purge after flowing the reactant.

[0077] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a dummy gate stack around a plurality of nanostructures above a substrate, wherein the plurality of nanostructures are alternately stacked with a plurality of dummy nanostructures; forming a lower source / drain region above the substrate, wherein the lower nanostructures of the plurality of nanostructures extend between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein the upper nanostructures of the plurality of nanostructures extend between the upper source / drain regions; removing the dummy gate stack and the plurality of dummy nanostructures to define an opening; and performing the step of: A deposition process is provided to form a lower work function metal (WFM) layer in the openings around the plurality of nanostructures, wherein an initial deposition cycle of the first deposition process comprises: flowing a first precursor in the openings, wherein the first precursor is attached to an upper surface in the openings; after flowing the first precursor, flowing a second precursor in the openings, wherein the second precursor is attached to a lower surface in the openings, and wherein the first precursor has a higher adhesion coefficient than the second precursor; and flowing a third precursor in the openings, wherein the third precursor reacts with the second precursor at a rate greater than that of the third precursor with the first precursor.

[0078] In some embodiments, the method further comprises: recessing the lower work function metal layer in the opening; and performing a second deposition process to form an upper work function metal layer in the opening around the upper nanostructure and above the lower work function metal layer. In some embodiments, an initial deposition cycle of the second deposition process comprises: flowing a fourth precursor in the opening, wherein the fourth precursor is attached to an upper surface in the opening; after flowing the fourth precursor, flowing a fifth precursor in the opening, wherein the fifth precursor is attached to a remaining surface in the opening, and wherein the fourth precursor has a higher adhesion coefficient than the fifth precursor; and flowing a sixth precursor in the opening, wherein the sixth precursor reacts with the fifth precursor at a greater rate than the sixth precursor reacts with the fourth precursor. In some embodiments, the method further comprises: depositing a glue layer above the upper work function metal layer; and depositing a filler metal above the glue layer. In some embodiments, the first precursor is a metal halide, and wherein the second precursor is a metal carbonyl. In some embodiments, the lower work function metal layer comprises titanium nitride, wherein the first precursor is TiCl 4 , wherein the second precursor is tetrakis(dimethylamino)titanium (TDMAT), and wherein the third precursor is NH 3 or N 2 H 4In some embodiments, after the initial deposition cycle of the first deposition process, each subsequent deposition cycle of the first deposition process includes: flowing the second precursor in the opening; and flowing the third precursor in the opening.

[0079] Still other embodiments of the present application provide a semiconductor device, comprising: a lower nanostructure extending between lower source / drain regions; an upper nanostructure extending between upper source / drain regions, wherein the upper nanostructure is disposed above the lower nanostructure, and wherein the upper source / drain regions are disposed above the lower source / drain regions; a lower gate electrode located around the lower nanostructure, wherein the lower gate electrode includes halide residues, and wherein a concentration of the halide residues in the lower gate electrode decreases in a direction toward a bottom surface of the lower gate electrode; and an upper gate electrode located around the upper nanostructure, wherein the upper gate electrode is disposed above the lower gate electrode.

[0080] In some embodiments, the lower gate electrode further comprises a carbonyl residue, and wherein the concentration of the carbonyl residue increases in a direction toward the bottom surface of the lower gate electrode. In some embodiments, the halide residue is chlorine, and wherein the carbonyl residue is carbon or oxygen.

[0081] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming an opening in a semiconductor device; as well as Depositing a target metal layer in the opening, wherein depositing the target metal layer comprises performing a plurality of deposition cycles, and wherein an initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; flowing a second precursor in the opening after flowing the first precursor, wherein the second precursor attaches to remaining surfaces in the opening, and wherein the first precursor does not react with the second precursor; and A reactant is flowed in the opening, wherein the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

2. The method according to claim 1, wherein: The first precursor has a greater adhesion coefficient than the second precursor.

3. The method according to claim 1, wherein: The first precursor is a metal halide and the second precursor is a metal carbonyl.

4. The method according to claim 1, wherein: After flowing the first precursor, the concentration of the first precursor decreases in a direction toward the bottom of the opening.

5. The method according to claim 1, wherein: After flowing the second precursor, the concentration of the second precursor increases in a direction toward the bottom of the opening.

6. The method of claim 1, further comprising controlling a process parameter while flowing the reactant so that the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

7. The method according to claim 6, wherein: The process parameters include process temperature, presence or absence of plasma, presence or absence of ion beam, presence of a reagent selective to the first precursor, or a combination thereof.

8. The method according to claim 1, wherein: After the initial deposition cycle, each subsequent deposition cycle of the plurality of deposition cycles comprises: flowing the second precursor in the opening; and The reactant is flowed in the opening.

9. A method of forming a semiconductor device, comprising: forming a dummy gate stack around a plurality of nanostructures over a substrate, wherein the plurality of nanostructures are alternately stacked with a plurality of dummy nanostructures; forming a lower source / drain region over the substrate, wherein a lower nanostructure of the plurality of nanostructures extends between the lower source / drain region; forming an upper source / drain region above the lower source / drain region, wherein an upper nanostructure of the plurality of nanostructures extends between the upper source / drain region; removing the dummy gate stack and the plurality of dummy nanostructures to define an opening; and performing a first deposition process to form a lower work function metal (WFM) layer in the openings around the plurality of nanostructures, wherein an initial deposition cycle of the first deposition process comprises: flowing a first precursor in the opening, wherein the first precursor is attached to an upper surface in the opening; flowing a second precursor in the opening after flowing the first precursor, wherein the second precursor is attached to a lower surface in the opening, and wherein the first precursor has a higher adhesion coefficient than the second precursor; and A third precursor is flowed in the opening, wherein the third precursor reacts with the second precursor at a greater rate than the third precursor reacts with the first precursor.

10. A semiconductor device comprising: a lower nanostructure extending between the lower source / drain regions; an upper nanostructure extending between upper source / drain regions, wherein the upper nanostructure is disposed over the lower nanostructure, and wherein the upper source / drain regions are disposed over the lower source / drain regions; a lower gate electrode located around the lower nanostructure, wherein the lower gate electrode includes halide residues, and wherein a concentration of the halide residues in the lower gate electrode decreases in a direction toward a bottom surface of the lower gate electrode; and An upper gate electrode is located around the upper nanostructure, wherein the upper gate electrode is disposed above the lower gate electrode.

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