Array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a driving transistor, a switching transistor and a dehydrogenation hole, wherein the distance between the dehydrogenation hole and a channel of the driving transistor is smaller than the distance between the dehydrogenation hole and a channel of the switching transistor. Through the dehydrogenation hole, the channel of the driving transistor can be subjected to more thorough dehydrogenation treatment, so that the driving transistor has a relatively large sub-threshold swing, meanwhile, the influence of the dehydrogenation treatment on the switching transistor can be reduced, the leakage current of the switching transistor is improved, and the reliability of the switching transistor is improved. Therefore, the grid voltage of the driving transistor can be well kept in the low-frequency refreshing scene, the influence of current fluctuation on the display brightness is reduced, the splash screen problem caused by overlarge leakage current of the switching transistor is solved, the display effect of the display panel in the low-frequency refreshing scene is improved, and the use experience of a user is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In modern display technology, the refresh rate of a display panel is one of the key parameters for evaluating display effects. A higher refresh rate means better image display effects on the display panel.

[0003] However, when the display panel is in static display, a too high refresh rate may cause the pixel unit to charge and discharge too frequently, thereby increasing the power consumption of the display panel and reducing the battery life of the electronic device. Therefore, reducing the refresh rate when the display panel is in static display is an effective way to reduce the power consumption of the display panel. However, under low refresh rate conditions, the display panel will experience screen flickering, which seriously affects the display effect. Summary of the invention

[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, an object of the present application is to provide an array substrate and a display panel.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, wherein the array substrate comprises a substrate, a semiconductor layer, a gate insulating layer and an interlayer insulating layer stacked in sequence;

[0006] The semiconductor layer includes a first section for forming a channel in a driving transistor and a second section for forming a channel in a switching transistor, wherein the driving transistor and the switching transistor are located in the same pixel circuit;

[0007] The array substrate is provided with a dehydrogenation hole, wherein the dehydrogenation hole at least penetrates the interlayer insulating layer in a direction perpendicular to the plane where the substrate is located;

[0008] There is a first distance between the geometric center of the orthographic projection of the first segment on the substrate and the geometric center of the orthographic projection of the dehydrogenation hole on the substrate, and there is a second distance between the geometric center of the orthographic projection of the second segment on the substrate and the geometric center of the orthographic projection of the dehydrogenation hole on the substrate, and the first distance is smaller than the second distance.

[0009] In a possible implementation manner, an orthographic projection of the first section on the substrate at least partially overlaps with an orthographic projection of the dehydrogenation hole on the substrate;

[0010] Preferably, the orthographic projection of the dehydrogenation hole on the substrate is located within the orthographic projection of the first section on the substrate.

[0011] In a possible implementation manner, a subthreshold swing of the driving transistor is greater than a subthreshold swing of the switching transistor.

[0012] In a possible implementation, one of the pixel circuits includes a driving transistor and a plurality of switch transistors;

[0013] A minimum value of a second distance between a geometric center of an orthographic projection of the second segments of the plurality of switch transistors on the substrate and a geometric center of an orthographic projection of the dehydrogenation hole on the substrate is greater than the first distance.

[0014] In a possible implementation, the number of the dehydrogenation holes is multiple;

[0015] The second distance between any one of the dehydrogenation holes and the switch transistor is greater than the first distance between the dehydrogenation hole and the drive transistor.

[0016] In a possible implementation, one of the pixel circuits includes a driving transistor and a plurality of switch transistors, and the number of the dehydrogenation holes is a plurality;

[0017] The minimum value of the second distance between the geometric center of the orthographic projection of the second segments of the plurality of switching transistors on the substrate and the geometric center of the orthographic projection of the plurality of dehydrogenation holes on the substrate is greater than the maximum value of the first distance between the geometric center of the orthographic projection of the first segment of the driving transistor on the substrate and the geometric center of the orthographic projection of the plurality of dehydrogenation holes on the substrate.

[0018] In a possible implementation, the array substrate further includes a first conductive layer, a second conductive layer, a third conductive layer and a capacitor insulating layer;

[0019] The capacitor insulating layer is located between the gate insulating layer and the interlayer insulating layer;

[0020] The first conductive layer is located between the gate insulating layer and the capacitor insulating layer;

[0021] The second conductive layer is located between the capacitor insulating layer and the interlayer insulating layer;

[0022] The third conductive layer is located on a side of the interlayer insulating layer away from the substrate;

[0023] The first conductive layer, the third conductive layer and the semiconductor layer form the driving transistor and the switching transistor;

[0024] Preferably, in a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole at least penetrates the interlayer insulating layer.

[0025] In a possible implementation, the dehydrogenation hole penetrates the interlayer insulating layer in a direction perpendicular to the plane where the substrate is located; or,

[0026] In a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole penetrates the interlayer insulating layer and the capacitor insulating layer; or,

[0027] In a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole penetrates the interlayer insulating layer, the capacitor insulating layer and the gate insulating layer;

[0028] Preferably, the dehydrogenation hole reuses a film layer through hole through which the source and / or drain of the driving transistor passes.

[0029] In a possible implementation, the array substrate further includes a signal trace;

[0030] The first conductive layer forms a scan signal wiring and a light emitting control signal wiring, the second conductive layer forms an initialization signal wiring, and the third conductive layer forms a data signal wiring and a power signal wiring;

[0031] Preferably, the array substrate further comprises a filling member filled in the dehydrogenation hole, and the material of the filling member comprises an inorganic material or a conductive material;

[0032] Preferably, the filler is a conductive filler, and in a direction perpendicular to the plane where the substrate is located, at least one end of the filler is insulated from the signal trace.

[0033] In a second aspect, an embodiment of the present application further provides a display panel, comprising the array substrate described in any one of the first aspects.

[0034] Based on any of the above aspects, the array substrate and electronic device provided in the embodiments of the present application include a driving transistor, a switching transistor and a dehydrogenation hole, and the distance between the dehydrogenation hole and the channel of the driving transistor is smaller than the distance between the dehydrogenation hole and the channel of the switching transistor. Through the dehydrogenation hole set as above, the channel of the driving transistor can be more thoroughly dehydrogenated, so that the driving transistor has a larger subthreshold swing, and at the same time, the influence of the dehydrogenation treatment on the switching transistor can be reduced, and the leakage current of the switching transistor can be improved, thereby ensuring that the gate voltage of the driving transistor can be well maintained in the low-frequency refresh scenario, reducing the influence of current fluctuations on the display brightness, and solving the problem of screen flickering caused by excessive leakage current of the switching transistor, improving the display effect of the display panel in the low-frequency refresh scenario, and enhancing the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a structural schematic diagram of a pixel circuit in the related art;

[0037] Figure 2 is a schematic structural diagram of another pixel circuit in the related art;

[0038] Figure 3 Schematic diagram of the film structure of the array substrate provided in the embodiment of the present application Figure 1 ;

[0039] Figure 4 Schematic diagram of the film structure of the array substrate provided in the embodiment of the present application Figure 2 ;

[0040] Figure 5 Schematic diagram of the film structure of the array substrate provided in the embodiment of the present application Figure 3 ;

[0041] Figure 6 Schematic diagram of the film structure of the array substrate provided in the embodiment of the present application Figure 4 ;

[0042] Figure 7 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application;

[0043] Figure 8 for Figure 7 The partial structure of the array substrate shown in FIG. Figure 1 ;

[0044] Fig. 9 for Figure 7 The partial structure of the array substrate shown in FIG. Figure 2 ;

[0045] Fig.10 for Figure 7 The partial structure of the array substrate shown in FIG. Figure 3 .

[0046] Label:

[0047] 10-array substrate; 110-substrate; 120-semiconductor layer; 1211-first section; 1221-second section; 1231-gate; 1232-source; 1233-drain; 130-gate insulating layer; 140-interlayer insulating layer; 141-dehydrogenation hole; 150-capacitor insulating layer; 1511-first capacitor plate; 1512-second capacitor plate; 160-buffer layer. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0050] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0051] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0052] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0053] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0054] In the related art, the array substrate may use 6T1C, 7T1C, 8T1C and other types of pixel circuits to drive the pixel devices and control the pixel devices to emit light. For example, taking the pixel circuit as a 7T1C pixel circuit as an example, the pixel circuit may include Figure 1 The driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first initialization transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second initialization transistor T7 and the storage capacitor C1 are shown.

[0055] Specifically, the working state of the above-mentioned pixel driving circuit in a refresh cycle is described below, wherein a refresh cycle includes a reset phase, a data writing phase and a light emitting phase.

[0056] In the reset phase, the first scan signal of the first scan signal line Scan1 controls the first initialization transistor T4 to turn on, so that the initialization signal provided by the initialization signal line can be transmitted to the gate of the driving transistor T1 via the first initialization transistor T4 to initialize the gate of the driving transistor T1.

[0057] During the compensation stage, the second scanning signal on the second scanning signal line Scan2 controls the compensation transistor T3 and the data writing transistor T2 to turn on, and the data voltage on the data signal line Vdata is transmitted to the gate of the driving transistor T1 through the data writing transistor T2, the source and drain of the driving transistor T2, and the compensation transistor T3.

[0058] In the light-emitting stage, the light-emitting control signal line EM controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn on, so that the branch where the light-emitting device is located is turned on, and the driving current used to drive the light-emitting device to emit light is determined by the gate voltage of the driving transistor T1.

[0059] Furthermore, during the light-emitting process, if the display panel is in a static display image rather than a dynamic picture scene, the display panel needs to display at a low refresh rate to reduce the power consumption of the display panel. Under low refresh rate conditions, the refresh cycle becomes longer, and the duration of each stage in the refresh cycle will also increase. Taking the light-emitting stage as an example, the duration of the drive current required to be provided to the light-emitting device also increases. Since the drive current is related to the gate voltage of the drive transistor, to increase the duration of the drive current, the gate voltage holding time of the drive transistor needs to be increased.

[0060] The inventors have found that when the subthreshold swing of the driving transistor is small and the leakage current of the switching transistor is too large, the gate voltage of the driving transistor cannot be maintained, and the display brightness is more sensitive to electrical fluctuations, which causes the display panel to have uneven brightness or inconsistent colors, i.e., display mura problems. The subthreshold swing is a parameter that measures the conductivity of the transistor in the subthreshold region (i.e., the weak inversion region). The smaller the subthreshold swing, the higher the sensitivity of the transistor to electrical fluctuations. In the light-emitting stage, the driving transistor T1 may be Figure 1 Leakage current is generated in the directions of I1 and I2 shown, which causes the gate voltage of the driving transistor to drop rapidly and cannot be maintained for a long time, resulting in a screen flicker problem.

[0061] Please refer to Figure 2 In some related technologies, the compensation transistor T3 and the first initialization transistor T4 are usually replaced by a double-gate thin film transistor (ie Figure 2 Specifically, the dual-gate thin film transistor controls the threshold voltage of the transistor independently through two gates. Although this solution can reduce the leakage current of the switching transistor to a certain extent, its effect is not ideal and cannot really solve the flicker problem.

[0062] In addition, in some other related technologies, the screen flickering problem may be solved by optimizing the process. Specifically, the channel defects of the switching transistor can be reduced by optimizing the process, thereby improving the leakage current of the switching transistor. However, the optimized process will adjust the electrical properties of all transistors. The reduction of channel defects will also reduce the subthreshold swing of the driving transistor, thereby increasing the sensitivity of the display brightness to electrical fluctuations, which may cause display mura problems.

[0063] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0064] Please refer to Figure 3 The embodiment of the present application provides an array substrate 10, which includes a substrate 110, a semiconductor layer 120, a gate insulating layer 130 and an interlayer insulating layer 140 stacked in sequence, wherein the substrate 110 may be a glass substrate.

[0065] The semiconductor layer 120 includes a first section 1211 for forming a channel in a driving transistor and a second section 1221 for forming a channel in a switching transistor, wherein the semiconductor layer 120 also includes a source S1 and a drain D1 constituting the driving transistor, and a source S2 and a drain D2 constituting the switching transistor. The driving transistor and the switching transistor are located in the same pixel circuit, and the driving current formed by the driving transistor and the switching transistor can drive the pixel device in the display panel to emit light.

[0066] In the embodiment of the present application, the semiconductor layer 120 can be formed of an inorganic semiconductor (such as amorphous silicon or polycrystalline silicon), an organic semiconductor or an oxide semiconductor, wherein the channel can be formed of P-Si. The gate insulating layer 130 and the interlayer insulating layer 140 can be a double-layer or triple-layer structure made of materials such as silicon oxide and silicon nitride.

[0067] The interlayer insulating layer 140 is provided with a dehydrogenation hole 141. In the direction perpendicular to the plane where the substrate 110 is located, the dehydrogenation hole 141 at least penetrates the interlayer insulating layer 140, that is, the dehydrogenation hole 141 can penetrate the interlayer insulating layer 140, and can also penetrate other film layers outside the interlayer insulating layer 140, such as the gate insulating layer 130. Dehydrogenation treatment can be performed on a specific area through the dehydrogenation hole 141.

[0068] There is a first distance between the geometric center of the first segment 1211 projected on the substrate 110 and the geometric center of the dehydrogenation hole 141 projected on the substrate, and there is a second distance between the geometric center of the second segment 1221 projected on the substrate 110 and the geometric center of the dehydrogenation hole 141 projected on the substrate 110. The first distance is smaller than the second distance, that is, the spatial distance between the dehydrogenation hole 141 and the channel of the driving transistor is smaller than the spatial distance between the dehydrogenation hole 141 and the channel of the switching transistor.

[0069] In the above structure, the array substrate 10 includes a driving transistor, a switching transistor and a dehydrogenation hole 141, and the distance between the dehydrogenation hole 141 and the channel of the driving transistor is smaller than the distance between the dehydrogenation hole 141 and the channel of the switching transistor. Through the above-mentioned dehydrogenation hole 141, not only can the channel of the driving transistor be dehydrogenated more thoroughly, so that the driving transistor has a larger subthreshold swing, but also the effect of the dehydrogenation on the switching transistor can be reduced, and the leakage current of the switching transistor can be improved, thereby ensuring that the gate voltage of the driving transistor can be well maintained in the low-frequency refresh scenario, reducing the effect of current fluctuations on the display brightness, and solving the problem of screen flickering caused by excessive leakage current of the switching transistor, improving the display effect of the display panel in the low-frequency refresh scenario, and enhancing the user experience.

[0070] Furthermore, in order to minimize the spatial distance between the dehydrogenation hole 141 and the channel of the driving transistor, the orthographic projection of the first segment 1211 on the substrate 110 may at least partially overlap with the orthographic projection of the dehydrogenation hole 141 on the substrate 110. Preferably, the orthographic projection of the first segment 1211 on the substrate 110 is located within the orthographic projection of the dehydrogenation hole 141 on the substrate 110, that is, the dehydrogenation hole 141 is located above the first segment 1211.

[0071] It is not difficult to understand that the above design can effectively shorten the path of hydrogen atoms in the first segment 1211 to reach the dehydrogenation holes 141, making it easy for hydrogen atoms in the first segment 1211 to overflow from the dehydrogenation holes 141, thereby increasing the dehydrogenation force on the channel in the driving transistor, thereby making the subthreshold swing of the driving transistor greater than the subthreshold swing of the switching transistor, reducing the sensitivity of the driving transistor to electrical changes, reducing the possibility of display mura problems, and ensuring the display effect of the display panel.

[0072] In some possible embodiments, a pixel circuit includes a driving transistor and multiple switching transistors. When the number of dehydrogenation holes 141 in the array substrate 10 is one, in order to reduce the impact of dehydrogenation treatment on the switching transistor, the minimum value of the second distance between the geometric center of the orthographic projection of the second segments 1221 of the multiple switching transistors on the substrate 110 and the geometric center of the orthographic projection of the dehydrogenation holes 141 on the substrate 110 is greater than the first distance.

[0073] Further, when there are multiple dehydrogenation holes 141 in the array substrate 10, the second distance between any dehydrogenation hole 141 and the switching transistor is greater than the first distance between the dehydrogenation hole 141 and the driving transistor. Specifically, when there are multiple dehydrogenation holes 141 and a pixel circuit includes a driving transistor and multiple switching transistors, the minimum value of the second distance between the geometric center of the orthographic projection of the second segment 1221 of the multiple switching transistors on the substrate 110 and the geometric center of the orthographic projection of the multiple dehydrogenation holes 141 on the substrate 110 is greater than the maximum value of the first distance between the geometric center of the orthographic projection of the first segment 1211 of the driving transistor on the substrate 110 and the geometric center of the orthographic projection of the multiple dehydrogenation holes 141 on the substrate 110, that is, the minimum value of the spatial distance between the dehydrogenation hole 141 and the channel of the switching transistor is greater than the maximum value of the spatial distance between the dehydrogenation hole 141 and the channel of the driving transistor.

[0074] Such a setting can not only perform a more thorough dehydrogenation treatment on the channel of the driving transistor, so that the driving transistor has a larger subthreshold swing, but also reduce the impact of the dehydrogenation treatment on the switching transistor, improve the leakage current of the switching transistor, thereby ensuring that the gate voltage of the driving transistor can be well maintained in the low-frequency refresh scenario, reduce the impact of current fluctuations on the display brightness, and solve the screen flickering problem caused by excessive leakage current of the switching transistor, improve the display effect of the display panel in the low-frequency refresh scenario, and enhance the user experience.

[0075] For some possible implementations, please refer to Figure 3-5 The array substrate 10 may further include a first conductive layer M1 , a second conductive layer M2 , a third conductive layer M3 and a capacitor insulating layer 150 .

[0076] The capacitor insulating layer 150 is located between the gate insulating layer 130 and the interlayer insulating layer 140, the first conductive layer M1 is located between the gate insulating layer 130 and the capacitor insulating layer 150, the second conductive layer M2 is located between the capacitor insulating layer 150 and the interlayer insulating layer 140, and the third conductive layer M3 is located on the side of the interlayer insulating layer 140 away from the substrate 110. The first conductive layer M1, the third conductive layer M3 and the semiconductor layer 120 form a driving transistor and a switching transistor. Specifically, the first conductive layer M1 can form the gates 1231 and the first capacitor plates 1511 of multiple transistors, the second conductive layer M2 can form the second capacitor plates 1512, and the third conductive layer M3 can form the source 1232 and the drain 1233 of multiple transistors. The capacitor insulating layer 150 can not only insulate and isolate the first capacitor plates 1511 and the second capacitor plates 1512, but also form a capacitor with the first capacitor plates 1511 and the second capacitor plates 1512. The capacitor insulating layer 150 and the interlayer insulating layer 140 insulate and isolate the gates 1231 , the sources 1232 , and the drains 1233 of the multiple transistors from each other, wherein the capacitor insulating layer 150 may be made of an inorganic material (eg, silicon nitride, silicon oxide, etc.).

[0077] The first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 are metal layers. Exemplarily, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 can be made of one or more of metal Al, Mo, Cu, Ti or other metal materials with low resistivity.

[0078] Furthermore, in a direction perpendicular to the plane where the substrate 110 is located, the dehydrogenation hole 141 at least penetrates the interlayer insulating layer 140. Specifically, the dehydrogenation hole 141 may penetrate the interlayer insulating layer 140 (the specific structure is as follows: Figure 3 As shown), it can also penetrate the interlayer insulating layer 140 and the capacitor insulating layer 150 (the specific structure is as shown Figure 4As shown), it may also penetrate the interlayer insulating layer 140, the capacitor insulating layer 150 and the gate insulating layer 130 (the specific structure is as shown in Figure 5 shown).

[0079] The inventors also found that in the related art, in the process of making the third conductive layer M3, a film through hole is usually made on the side of the interlayer insulating layer 140 away from the substrate 110, and then metal deposition is performed on the film through hole to form the third conductive layer M3. After making the film through hole, some related processes will perform a dehydrogenation treatment on the array substrate 10 through the film through hole to increase the subthreshold swing of the driving transistor. However, in the above process, the switching transistor is greatly affected by the dehydrogenation treatment, and its leakage current also increases accordingly, resulting in a flickering screen problem caused by excessive leakage current of the switching transistor.

[0080] In this embodiment, the film through hole and the dehydrogenation hole 141 can be made first, wherein the dehydrogenation hole 141 can penetrate the interlayer insulating layer 140, or penetrate the interlayer insulating layer 140 and the capacitor insulating layer 150, or penetrate the interlayer insulating layer 140, the capacitor insulating layer 150 and the gate insulating layer 130. Then, metal deposition is performed on the film through hole to form the third conductive layer M3, and then the channel of the driving transistor is dehydrogenated through the dehydrogenation hole 141, which can not only ensure that the driving transistor has a large subthreshold swing, thereby ensuring that the gate voltage of the driving transistor can be well maintained in the low-frequency refresh scenario, but also reduce the impact of the dehydrogenation treatment on the switching transistor, solve the problem of screen flickering caused by excessive leakage current of the switching transistor, improve the display effect of the display panel in the low-frequency refresh scenario, and enhance the user experience.

[0081] It should be noted that when the dehydrogenation hole 141 penetrates the interlayer insulating layer 140, the capacitor insulating layer 150 and the gate insulating layer 130, the dehydrogenation hole 141 in the embodiment of the present application can be a film through hole through which the source and / or drain of the driving transistor passes. Specifically, after the film through hole is made, the film through hole of the driving transistor can be temporarily blocked, and metal deposition is performed on the film through hole of the switching transistor to form the source and / or drain of the switching transistor, and then the channel of the driving transistor is dehydrogenated through the film through hole of the driving transistor, and finally metal deposition is performed on the film through hole of the driving transistor to form the source and / or drain of the driving transistor.

[0082] In addition, please refer to Figure 6 The array substrate 10 may further include a buffer layer 160 between the substrate 110 and the semiconductor layer 120. The buffer layer 160 may be formed of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). Exemplarily, the buffer layer 160 may be a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer formed on the substrate.

[0083] Furthermore, the array substrate 10 also includes multiple signal lines connecting the pixel circuits. Specifically, the multiple signal lines may include a power signal line, a data signal line Vdata, an initialization signal line Vref, a light-emitting control signal line EM, and multiple scan signal lines, wherein the power signal line may include a first power signal line ELVDD and a second power signal line ELVSS, and the multiple scan signal lines include a first scan signal line Scan1, a second scan signal line Scan2, and a third scan signal line Scan3.

[0084] Please refer to Figure 7-10 The first conductive layer M1 can form a plurality of scan signal lines and a light emitting control signal line EM, the second conductive layer M2 can form an initialization signal line Vref, and the third conductive layer M3 can form a data signal line Vdata and a power signal line (including ELVDD and ELVSS).

[0085] The data signal line Vdata can provide a data voltage signal for the data writing transistor T2, the initialization signal line Vref can provide an initialization voltage for the first initialization transistor T4 and the second initialization transistor T7, the first power signal line ELVDD can provide a first power voltage signal for the first light-emitting control transistor, and the second power signal line ELVSS can provide a second power voltage signal for the light-emitting device. The voltage of the first power voltage signal provided by the first power signal line ELVDD is greater than the voltage of the second power voltage signal provided by the second power signal line ELVSS.

[0086] Furthermore, when the dehydrogenation hole 141 is not a membrane through hole through which the source and / or drain of the driving transistor passes, the array substrate 10 also includes a filling member filled in the dehydrogenation hole 141, and the material of the filling member includes a metal material. In a direction perpendicular to the plane where the substrate 110 is located, at least one end of the filling member is insulated from the signal line, and preferably, in a direction perpendicular to the plane where the substrate 110 is located, both ends of the filling member are insulated from the signal line.

[0087] Based on the same inventive concept, an embodiment of the present application also provides a display panel, which includes any one of the array substrates 10 in the above embodiments. The display panel including the above array substrate can ensure that there is no display mura problem when refreshing at a low refresh rate in a static picture scene, that is, it can not only reduce power consumption but also ensure display effect.

[0088] In summary, the embodiment of the present application provides an array substrate and a display panel, wherein the array substrate includes a driving transistor, a switching transistor and a dehydrogenation hole, wherein the distance between the dehydrogenation hole and the channel of the driving transistor is smaller than the distance between the dehydrogenation hole and the channel of the switching transistor. By setting the dehydrogenation hole as described above, the channel of the driving transistor can be more thoroughly dehydrogenated, so that the driving transistor has a larger subthreshold swing, and at the same time, the effect of the dehydrogenation treatment on the switching transistor can be reduced, and the leakage current of the switching transistor can be improved, thereby ensuring that the gate voltage of the driving transistor can be well maintained in a low-frequency refresh scenario, reducing the effect of current fluctuations on display brightness, and solving the problem of screen flickering caused by excessive leakage current of the switching transistor, thereby improving the display effect of the display panel in the low-frequency refresh scenario and enhancing the user experience.

[0089] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a substrate, a semiconductor layer, a gate insulating layer and an interlayer insulating layer which are stacked in sequence; The semiconductor layer includes a first section for forming a channel in a driving transistor and a second section for forming a channel in a switching transistor, wherein the driving transistor and the switching transistor are located in the same pixel circuit; The array substrate is provided with a dehydrogenation hole, wherein the dehydrogenation hole at least penetrates the interlayer insulating layer in a direction perpendicular to the plane where the substrate is located; There is a first distance between the geometric center of the orthographic projection of the first segment on the substrate and the geometric center of the orthographic projection of the dehydrogenation hole on the substrate, and there is a second distance between the geometric center of the orthographic projection of the second segment on the substrate and the geometric center of the orthographic projection of the dehydrogenation hole on the substrate, and the first distance is smaller than the second distance.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first section on the substrate at least partially overlaps with the orthographic projection of the dehydrogenation hole on the substrate; Preferably, the orthographic projection of the dehydrogenation hole on the substrate is located within the orthographic projection of the first section on the substrate.

3. The array substrate according to claim 1, characterized in that: The subthreshold swing of the driving transistor is greater than the subthreshold swing of the switching transistor.

4. The array substrate according to claim 1, wherein: One of the pixel circuits includes a driving transistor and a plurality of switching transistors; A minimum value of a second distance between a geometric center of an orthographic projection of the second segments of the plurality of switch transistors on the substrate and a geometric center of an orthographic projection of the dehydrogenation hole on the substrate is greater than the first distance.

5. The array substrate according to claim 1, wherein: The number of the dehydrogenation holes is multiple; The second distance between any one of the dehydrogenation holes and the switch transistor is greater than the first distance between the dehydrogenation hole and the drive transistor.

6. The array substrate according to claim 1, characterized in that: One of the pixel circuits includes a driving transistor and a plurality of switch transistors, and the number of the dehydrogenation holes is a plurality; The minimum value of the second distance between the geometric center of the orthographic projection of the second segments of the plurality of switching transistors on the substrate and the geometric center of the orthographic projection of the plurality of dehydrogenation holes on the substrate is greater than the maximum value of the first distance between the geometric center of the orthographic projection of the first segment of the driving transistor on the substrate and the geometric center of the orthographic projection of the plurality of dehydrogenation holes on the substrate.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further comprises a first conductive layer, a second conductive layer, a third conductive layer and a capacitor insulating layer; The capacitor insulating layer is located between the gate insulating layer and the interlayer insulating layer; The first conductive layer is located between the gate insulating layer and the capacitor insulating layer; The second conductive layer is located between the capacitor insulating layer and the interlayer insulating layer; The third conductive layer is located on a side of the interlayer insulating layer away from the substrate; The first conductive layer, the third conductive layer and the semiconductor layer form the driving transistor and the switching transistor; Preferably, in a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole at least penetrates the interlayer insulating layer.

8. The array substrate according to any one of claims 1 to 6, characterized in that: In a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole penetrates the interlayer insulating layer; or, In a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole penetrates the interlayer insulating layer and the capacitor insulating layer; or, In a direction perpendicular to the plane where the substrate is located, the dehydrogenation hole penetrates the interlayer insulating layer, the capacitor insulating layer and the gate insulating layer; Preferably, the dehydrogenation hole reuses a film layer through hole through which the source and / or drain of the driving transistor passes.

9. The array substrate according to claim 7, characterized in that: The array substrate also includes signal wiring; The first conductive layer forms a scan signal wiring and a light emitting control signal wiring, the second conductive layer forms an initialization signal wiring, and the third conductive layer forms a data signal wiring and a power signal wiring; Preferably, the array substrate further comprises a filling member filled in the dehydrogenation hole, and the material of the filling member comprises an inorganic material or a conductive material; Preferably, the filler is a conductive filler, and in a direction perpendicular to the plane where the substrate is located, at least one end of the filler is insulated from the signal trace.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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