Adjustable gate Miller platform voltage detection circuit suitable for power tube

Abstract

The invention discloses an adjustable gate Miller platform voltage detection circuit suitable for a power tube. The adjustable gate Miller platform voltage detection circuit comprises a voltage slope detection circuit, a current comparison circuit and two inverter circuits, the output end of the voltage slope detection circuit is connected with the input end of the current comparison circuit; the output end of the current comparison circuit is connected with the input ends of the two inverter circuits; high and low levels are output through the two inverter circuits; the voltage slope detection circuit comprises a capacitor, a bias current source, a PMOS (P-channel Metal Oxide Semiconductor) tube, two NMOS (N-channel Metal Oxide Semiconductor) tubes and two switch tubes; the current comparison circuit comprises an NMOS (N-channel Metal Oxide Semiconductor) tube, three PMOS (P-channel Metal Oxide Semiconductor) tubes and a pull-down resistor; and each phase inverter circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube and an NMOS (N-channel Metal Oxide Semiconductor) tube. The circuit is wide in application, the working speed of the current comparison network is high, and the working requirement of the power supply under high frequency is met. In addition, the detection capability of the circuit can be changed by adjusting the resistance, so that the non-ideal Miller platform can be detected.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to an adjustable gate Miller platform voltage detection circuit suitable for a power tube. Background Art

[0002] With the increasing shortage of energy, how to improve the efficiency of energy utilization has become a focal issue in society. Compared with linear power supplies, switching power supplies are widely used in all walks of life due to their advantages such as lower power consumption, higher efficiency, and greater power density. Power semiconductor devices are the core components of switching power supply chips. Currently, the commonly used power semiconductor devices are gallium nitride devices, which have excellent switching frequency and switching speed compared to traditional silicon-based devices. In the process of switching power devices, relatively large dv / dt and di / dt will be generated, causing voltage ringing problems at the switching nodes, thereby generating electromagnetic interference (EMI). In addition, as the switching frequency of power semiconductor devices increases, the switching loss problem becomes more prominent.

[0003] It is difficult for traditional drive circuits to optimize both EMI and switching loss problems at the same time. Therefore, a multi-stage drive circuit is required to control the drive current size at different stages. When EMI problems occur, the drive current is reduced, and when other stages are increased, the drive current is increased. This way, the voltage and current spike problems and switching loss problems can be optimized at the same time. Usually, the EMI problem of power semiconductor devices in the conduction stage generally occurs during the Miller platform. Using a large current to conduct before and after the Miller platform appears, and using a small current to conduct during the Miller platform can optimize the voltage and current spike problems and switching loss problems at the same time. Therefore, it is very important to detect the position of the Miller platform.

[0004] There are generally two common Miller platform detection circuits. One is to cleverly use the half-bridge circuit. We know that the Miller voltage increases with the increase of load current. In the half-bridge circuit, such as the synchronous rectification Buck circuit, when the high-side tube (main switch tube) is turned off, the low-side tube (freewheeling tube) is the inductor current. The voltage difference across the low-side tube is the inductor current multiplied by the on-resistance of the low-side tube. It can be found that the voltage drop across the low-side tube is proportional to the load current, but this method has limitations and can only be applied to the half-bridge circuit. Another way to get the Miller voltage is to directly use the gate voltage of the power tube. For example, the gate voltage of the power device is detected by an RC high-pass filter, but the Miller voltage detection speed of this circuit is still not fast enough. For this reason, it is necessary to explore a new Miller voltage detection circuit. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide an adjustable gate Miller platform voltage detection circuit suitable for power tubes. The circuit solves the problems of slow detection speed, limited application and inaccurate detection of the above detection circuit, and realizes the Miller platform detection function with adjustable detection resolution.

[0006] Technical solution: The detection circuit of the present invention is composed of a voltage slope detection circuit, a current comparison circuit and two inverters; wherein the voltage slope detection circuit relies on the differential formula of the voltage and current on the capacitor When the voltage slope changes, a corresponding current will be generated on the capacitor. Then, through the current mirror, the current generated by the voltage slope detection network is transmitted to the current comparison network, compared with the original stored current information, and the corresponding voltage is generated, and then the high and low level outputs are realized through two inverters. This circuit is widely used, and the current comparison network works very fast, which can meet the working requirements of the power supply at high frequency. In addition, when the Miller platform is a non-ideal Miller platform, the voltage may still have a certain slope during the platform. The circuit can also change the detection capability of the circuit by adjusting the resistance, thereby realizing the detection of the non-ideal Miller platform.

[0007] The invention discloses an adjustable gate Miller platform voltage detection circuit suitable for a power tube, comprising a voltage slope detection circuit, a current comparison circuit and two inverter circuits; the output end of the voltage slope detection circuit is connected to the input end of the current comparison circuit; the output end of the current comparison circuit is connected to the input ends of the two inverter circuits; high and low levels are output through the two inverter circuits;

[0008] The voltage slope detection circuit includes a capacitor Cd, a bias current source Ibias, a PMOS tube, two NMOS tubes and two switch tubes;

[0009] The current comparison circuit includes an NMOS tube, three PMOS tubes and a pull-down resistor;

[0010] Each of the inverter circuits includes a PMOS tube and an NMOS tube.

[0011] Further, the voltage slope detection circuit includes a capacitor Cd, a bias current source Ibias, NMOS tubes M1, M2, PMOS tube M3 and switch tubes M12, M13; wherein one end of the capacitor Cd is connected to the input voltage signal, and the other end is connected to the input of the bias current source Ibias, and is commonly connected to the drain of the NMOS tube M1; the gate of the NMOS tube M1 is connected to the gate of M2 and the drain of M1, and the sources of M1 and M2 are connected to the ground VSS, so that M1 and M2 form a current mirror; the drain of the NMOS tube M2 is connected to the drain of the PMOS tube M3 and the drain of the switch tube M12; the source of the PMOS tube M3 is connected to the power supply VDD, the source of the switch tube M12 is connected to the gate of M3, and is commonly connected to the drain of the switch tube M13, and finally connected to the current comparison circuit through the source of M13.

[0012] Further, the current comparison circuit includes an NMOS tube M6, a PMOS tube M4, M5 and M7 and a pull-down resistor R1; wherein the source of the PMOS tube M4 is connected to the power supply VDD, and the drain is connected to the gate of M5 and the source of M13; the source of M5 is connected to the power supply VDD, and the drain is connected to the drain of the NMOS tube M6 and the drain of the NMOS tube M7 and connected to the inverter circuit; the gate of M6 is connected to the gate of M1 in the voltage slope detection network, and the source is connected to the upper end of the pull-down resistor R1, and the lower end of the pull-down resistor R1 is connected to the ground VSS.

[0013] Furthermore, the two inverter circuits include a first-stage inverter and a second-stage inverter; the first-stage inverter includes a PMOS tube M8 and an NMOS tube M9; the source of M8 is connected to a power supply VDD, the drain is connected to the drain of the NMOS tube M9, the source of M9 is connected to a ground VSS, and the gates of M8 and M9 are connected together; the input end of the first-stage inverter is connected to the output end of the current comparison circuit; the second-stage inverter includes a PMOS tube M11 and an NMOS tube M10; the source of M11 is connected to the power supply VDD, the drain is connected to the drain of the NMOS tube M10, the source of M10 is connected to the ground VSS, and the gates of M11 and M10 are connected together; the input end of the second-stage inverter is connected to the output end of the first-stage inverter, and the output end of the second-stage inverter is the output end of the adjustable gate Miller platform voltage detection circuit.

[0014] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0015] 1) The size of the devices used in the circuit of the present invention is relatively small. Only MOS tubes, resistors with relatively small resistance values ​​and small capacitors are used in the circuit, and no inductors are used, which saves cost and space and is conducive to miniaturization and integration.

[0016] 2) The circuit of the present invention has low power consumption. When the circuit works normally, the current in each branch is between tens and hundreds of microamperes. The small working current makes the power consumption of the circuit very small. In addition, the small power consumption makes the circuit have low requirements for heat dissipation.

[0017] 3) The circuit of the present invention has a wide range of applications. The resistance value can be adjusted to change the detection resolution of the circuit. For non-ideal Miller platforms, the detection capability can be improved to meet the requirements, and the scope of application is relatively wide. In addition, the circuit control signal is simple and the system stability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram of the present invention;

[0019] Figure 2 It is a module diagram of the control signal of the present invention;

[0020] Figure 3 This is a power tube gate drive voltage detection circuit diagram applicable to the present invention;

[0021] Figure 4 It is the key waveform timing diagram of the circuit of the present invention;

[0022] Figure 5 It is a simulation diagram of the key waveform of the circuit of the present invention under the ideal Miller platform;

[0023] Figure 6 It is a simulation diagram of the key waveform of the circuit of the present invention under the non-ideal Miller platform. DETAILED DESCRIPTION

[0024] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown, the adjustable gate Miller platform detection circuit is mainly divided into three parts, namely the voltage slope detection network, the current comparison network and the inverter network. SN, SP and EN are the gate control signals of the switch tube, which are controlled by the PWM signal wave generated by the function signal generator. Among them, SN and SP are two completely opposite signals, indicating that the MOS tubes M12 and M13 will not be turned on at the same time. The output signal of the current comparison network is connected to the input end of the inverter network, so the voltage range of the output of the entire circuit is 0 to VDD. In addition, the detection capability can be adjusted by adjusting the resistance value of the resistor R1 in the current comparison network.

[0026] like Figure 2 This is the control signal input module of the present invention. The function generator provides square wave signals PWM1, PWM2 and PWM3 with adjustable frequency and duty cycle. These three signals control the conduction of the switch tubes M12, M13, M4 and M7 respectively.

[0027] like Figure 3 This is a power tube applicable to the present invention. The input end of the present invention is connected to the gate of the power tube. The output end signal of the present invention is the detection result. When the gate voltage VG of the power tube begins to change, the output end signal of the present invention changes from a high level to a low level. When the Miller platform is reached, the output end signal of the present invention changes from a low level to a high level. By analyzing the output signal of the present invention, the function of Miller platform voltage detection can be realized.

[0028] like Figure 4 ,This is Figure 1 The key waveform timing diagram of the circuit includes control signals, output voltage signals and key currents. EN is the control signal of switch tube M7, SN is the control signal of switch tubes M4 and M13, and SP is the control signal of switch tube M12, where SN and SP are two completely opposite signals. Ibias is a very small bias current, which allows M1 to work in the saturation region and provides a static bias voltage to M2 and M6 so that they can work quickly when VG rises. When the PWM signal is at a low level, the power tube is in the cut-off state. The working process of the Miller platform detection circuit is mainly divided into the following five stages:

[0029] During 0-t1, the gate voltage of the power tube is close to 0, and the power tube is in the cut-off state. In this stage, the EN signal is at a low level, the MOS tube M7 is turned on, and the output VOUT is at a high level.

[0030] During t1-t2, the gate voltage VG of the power tube begins to change and rises from zero, the slope detection module starts to work, EN becomes high level, SN is low level, SP is high level, then MOS tube M7 is turned off, M13 is turned off, M12 is turned on, M4 is turned on, and the capacitor Cd converts the change of the gate voltage VG of the power tube into the current Isense. Isense is approximately given by the following formula.

[0031]

[0032] Among them, Cd represents the input capacitance value, VG represents the gate voltage of the power tube, and t represents time.

[0033] MOS tubes M1, M2 and M6 form a current mirror structure, and M2 amplifies the current Isense through mirroring. Since M12 is turned on at this time, the source and drain of M3 are connected together, and M3 works in the saturation region. M3 converts the mirror current of M2 into the gate voltage and records the Isense information at this moment. Similarly, M6 also generates a mirror current Isen through the current mirror structure. Since M4 is turned on, the gate voltage of M5 is high, and M5 is in the cut-off region. At this time, the current Iref flowing through M5 is approximately 0. Therefore, the drain voltage of M6 quickly decreases to 0, and the output terminal VOUT also quickly decreases to 0.

[0034] During t2-t3, the gate voltage VG of the power tube continues to rise, the SN signal rises to a high level at t2, the SP drops to a low level, the EN signal always remains at a high level, the switch tube M12 is turned off, M13 is turned on, and M4 is turned off. The gate of M5 is connected to the gate of M3, so the gate voltage of M5 will remain at the gate voltage of M3 when VOUT becomes low. If the size of M3 and M5 is appropriate, Iref is close to the peak current Isenpeak of Isen. During this period, the output terminal VOUT remains at a low level.

[0035] During t3-t4, the gate voltage of the power tube reaches the Miller platform, and the gate voltage VG remains unchanged. During this period, EN remains high, SN is high, SP is low, MOS tube M7 is turned off, M4 is turned off, M12 is turned off, and M13 is turned on. Since the gate voltage of the power tube remains unchanged during this period, it can be seen from formula 1 that the current Isense decreases rapidly, and its mirror current Isen will also decrease. The current Iref flowing through M5 will still remain close to Isenpeak until the drain voltage of M5 rises to close to VDD, causing the M5 tube to enter the linear region, at which time the output terminal VOUT is pulled up to VDD.

[0036] After time t4, the EN signal becomes low, the output terminal VOUT is fixed at the high level VDD, the slope detection module does not work, and the output terminal VOUT remains high until the next cycle arrives. The purpose of this is to prevent the slope detection from being triggered incorrectly.

[0037] like Figure 5 To follow the Cadence software Figure 1 Circuit and Figure 3 The simulation waveform of the control signal, the simulation waveform and Figure 4 The analyzed waveform timing diagrams are the same, which further verifies the feasibility of the circuit of the present invention.

[0038] like Figure 6When the Miller platform is non-ideal, the slope of the gate voltage VG of the power tube is not zero during the Miller platform. During this period, the gate voltage VG will still increase slowly, but the slope of the voltage change is much smaller than other time periods. In order to detect this inconspicuous Miller platform, the circuit detection capability can be improved by adjusting the resistor R1. Figure 6 The simulation waveform of the non-ideal Miller platform in Cadence software is shown in Figure 2. Figure 4 This is consistent with the analysis in , further verifying the function of the circuit in adjusting the detection capability.

[0039] In summary, the present invention realizes the function of Miller platform detection through a voltage slope detection network, a current comparison network and an inverter network. In addition, the present invention can change the detection capability by adjusting the size of the resistor to realize the detection of a non-ideal Miller platform. The present invention has low power consumption, stable structure, and a wide range of applications. Its input end can be directly connected to the input end of the power tube. This implementation case is one of the circuits applicable to the present invention, and the applicable circuits are not limited to this. Any changes, replacements, and modifications to the present invention or the application circuit are still included in the scope of technical protection.

Claims

1. An adjustable gate Miller platform voltage detection circuit suitable for a power tube, characterized in that: It includes a voltage slope detection circuit, a current comparison circuit and two inverter circuits; the output end of the voltage slope detection circuit is connected to the input end of the current comparison circuit; the output end of the current comparison circuit is connected to the input ends of the two inverter circuits; high and low levels are output through the two inverter circuits; The voltage slope detection circuit includes a capacitor Cd, a bias current source Ibias, a PMOS tube, two NMOS tubes and two switch tubes; The current comparison circuit includes an NMOS tube, three PMOS tubes and a pull-down resistor; Each of the inverter circuits includes a PMOS tube and an NMOS tube.

2. The adjustable gate Miller platform voltage detection circuit suitable for a power tube according to claim 1, characterized in that: The voltage slope detection circuit includes a capacitor Cd, a bias current source Ibias, NMOS tubes M1, M2, PMOS tube M3 and switch tubes M12, M13; one end of the capacitor Cd is connected to the input voltage signal, and the other end is connected to the input of the bias current source Ibias, and is commonly connected to the drain of the NMOS tube M1; the gate of the NMOS tube M1 is connected to the gate of M2 and the drain of M1, and the sources of M1 and M2 are connected to the ground VSS, so that M1 and M2 form a current mirror; the drain of the NMOS tube M2 is connected to the drain of the PMOS tube M3 and the drain of the switch tube M12; the source of the PMOS tube M3 is connected to the power supply VDD, the source of the switch tube M12 is connected to the gate of M3, and is commonly connected to the drain of the switch tube M13, and finally connected to the current comparison circuit through the source of M13.

3. The adjustable gate Miller platform voltage detection circuit suitable for a power tube according to claim 1, characterized in that: The current comparison circuit includes an NMOS tube M6, a PMOS tube M4, M5 and M7 and a pull-down resistor R1; wherein the source of the PMOS tube M4 is connected to the power supply VDD, and the drain is connected to the gate of M5 and the source of M13; the source of M5 is connected to the power supply VDD, and the drain is connected to the drain of the NMOS tube M6 and the drain of the NMOS tube M7 and connected to the inverter circuit; the gate of M6 is connected to the gate of M1 in the voltage slope detection network, and the source is connected to the upper end of the pull-down resistor R1, and the lower end of the pull-down resistor R1 is connected to the ground VSS.

4. The adjustable gate Miller platform voltage detection circuit suitable for a power tube according to claim 1, characterized in that: The two inverter circuits include a first-stage inverter and a second-stage inverter; the first-stage inverter includes a PMOS tube M8 and an NMOS tube M9; the source of M8 is connected to a power supply VDD, the drain is connected to the drain of the NMOS tube M9, the source of M9 is connected to a ground VSS, and the gates of M8 and M9 are connected together; the input end of the first-stage inverter is connected to the output end of the current comparison circuit; the second-stage inverter includes a PMOS tube M11 and an NMOS tube M10; the source of M11 is connected to the power supply VDD, the drain is connected to the drain of the NMOS tube M10, the source of M10 is connected to the ground VSS, and the gates of M11 and M10 are connected together; the input end of the second-stage inverter is connected to the output end of the first-stage inverter, and the output end of the second-stage inverter is the output end of the adjustable gate Miller platform voltage detection circuit.

5. A detection method based on the adjustable gate Miller platform voltage detection circuit applicable to a power tube according to claim 1, characterized in that: EN is defined as the control signal of the switch tube M7, SN is the control signal of the switch tubes M4 and M13, and SP is the control signal of the switch tube M12, wherein SN and SP are two completely opposite signals, Ibias is the bias current, which makes M1 work in the saturation region and provides a static bias voltage to M2 and M6. When the PWM signal is at a low level, the power tube is in a cut-off state. The detection method comprises the following steps: Step 1: During the period 0-t1, the gate voltage of the power tube is close to 0, and the power tube is in the cut-off state. In this stage, the EN signal is at a low level, the MOS tube M7 is turned on, and the output VOUT is at a high level; Step 2, during the period t1-t2, the gate voltage VG of the power tube starts to change and rises from zero, the slope detection module starts to work, EN becomes high level, SN is low level, SP is high level, then MOS tube M7 is cut off, M13 is cut off, M12 is turned on, M4 is turned on, and the capacitor Cd converts the change of the gate voltage VG of the power tube into the current Isense; MOS tube M1, M2 and M6 form a current mirror structure, and M2 amplifies the current Isense through the mirror; since M12 is turned on at this time, the source and drain of M3 are connected together, and M3 works in the saturation region, M3 converts the mirror current of M2 into the gate voltage, and records the Isense information at this moment; similarly, M6 also generates a mirror current Isen through the current mirror structure; since M4 is turned on, the gate voltage of M5 is high level, and M5 is in the cut-off region, and the current Iref flowing through M5 is 0 at this time, so the drain voltage of M6 is reduced to 0, and the output terminal VOUT is reduced to 0; Step 3, during the period t2-t3, the gate voltage VG of the power tube continues to rise, the SN signal rises to a high level at time t2, the SP drops to a low level, the EN signal always remains at a high level, the switch tube M12 is turned off, M13 is turned on, and M4 is turned off; the gate of M5 is connected to the gate of M3, then the gate voltage of M5 will remain at the gate voltage of M3 when VOUT becomes a low level, and Iref is close to the peak current Isenpeak of Isen; during this period, the output terminal VOUT remains at a low level; Step 4: After time t4, the EN signal becomes low level, the output terminal VOUT is fixed at the high level VDD, the slope detection module does not work, and the output terminal VOUT remains at a high level until the next cycle arrives.

6. The detection method according to claim 5, characterized in that: In step 2, the capacitor Cd converts the change of the power tube gate voltage VG into the current Isense, which is given by the following formula: Among them, Cd represents the input capacitance value, VG represents the gate voltage of the power tube, and t represents time.

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