Kelvin test method in chip FT test

Abstract

The invention discloses a Kelvin test method in a chip FT test, which is applied to an FT test circuit, the FT test circuit comprises a system loading circuit, a resistor R1, an analog contact impedance R2, an analog contact impedance R3, a sampling resistor R4, a switch S1 and an external operational amplifier U1, the positive end of the sampling resistor R4 is electrically connected with the CSP end of a chip through a series connection resistor R1, and the negative end of the sampling resistor R4 is electrically connected with the CSP end of the chip through a series connection resistor R2. The negative end of the sampling resistor R4 and one end of the analog contact resistor R2 are respectively connected with a system GND, the other end of the analog contact resistor R2 is electrically connected with the GNDK (CSN) end of the chip, the switch S1 is connected with the sampling resistor R4 in parallel, the positive end of the sampling resistor R4 is further electrically connected with the positive input end of the external operational amplifier U1 and the system load pulling circuit, one end of the analog contact resistor R3 is electrically connected with the GNDP (CSN) end of the chip, and the other end of the analog contact resistor R2 is electrically connected with the GNDK (CSN) end of the chip. And the other end of the analog contact impedance R3 is electrically connected with the reverse input end of the external operational amplifier U1.

Description

Technical Field

[0001] The invention relates to the technical field of chip testing, in particular to a Kelvin testing method in chip FT testing. Background Art

[0002] Many chips are designed with two sampling pins for external current detection, one is the positive sampling terminal CSP, and the other is the negative sampling terminal CSN. For some chips, in order to save pin resources during packaging, the bonding lines of CSN and GND are bonded together. In this case, it will be found in the FT test that the calibration related to CSP / CSN, such as OP offset calibration or overcurrent detection OCP calibration, will be calibrated incorrectly. The reason is that the pin corresponding to GND (CSN) of the test socket will present a corresponding contact impedance as the contact quality changes during the test, which will affect the relevant calibration. Figure 1For OP offset calibration, the S1 switch needs to be closed, CSP and CSN are shorted together, and the calibration register is adjusted to adjust the OP offset. For IC, when 5V supplies power to the power pin, the chip will have a working current of several hundred uA to several mA. This current will pass through the GND of the chip and eventually flow to the GND of the entire system. Then this current I1 will cause a certain voltage drop through the contact impedance R2 on the GND pin, resulting in the voltage difference between V1 and V2 seen inside the chip is not the voltage difference between V3 and V4 when the external short is connected. There is a certain difference, which leads to the deviation of OP offset calibration. Similarly, for the overcurrent detection OCP calibration, this calibration requires the system to load a certain current, and adjust the calibration register to adjust the chip to trigger the overcurrent detection. If you want to calibrate the overcurrent detection under 360mA, when the system load circuit loads a constant current of 360mA, the external op amp monitors to ensure the accuracy of the pulled current. Similarly, when the chip's working current I1 passes through the contact impedance R2 on the GND pin, a certain voltage drop will be generated, resulting in the voltage difference between V1 and V2 seen inside the chip is not the voltage difference between V3 and V4 at both ends of the external sampling resistor, that is, the op amp inside the chip does not see the accurate 360mA, which affects the overcurrent detection OCP calibration and causes calibration deviation. From the above description, it can be seen that the reason for affecting the calibration is that the contact impedance R2 causes the voltage of CSN, that is, GND, to be not the real system GND voltage. There is a voltage difference between them due to the working current and impedance R2, which causes the chip to see the voltage difference between V3 and V4 at both ends of the real sampling resistor R4 during calibration. There is currently no better solution to this effect. The only way is to constantly clean the socket manually to ensure ideal contact during the test. However, this method is very labor-intensive and time-consuming, and sometimes if it is not cleaned in time, it will cause related calibration deviations. If the quality inspection process is not discovered in time, the related defective chips will flow out. Once there is an impact, re-schedule the test, which will result in a waste of production costs and time costs. Summary of the invention

[0003] The object of the present invention is to solve at least one of the technical problems existing in the prior art and to provide a Kelvin test method in chip FT test which compensates for the influence of contact impedance on calibration.

[0004] According to the Kelvin test method in the chip FT test of the first aspect of the present invention, the embodiment is used to detect OP offset calibration and is applied to the FT test circuit, wherein the FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, a switch S1 and an external operational amplifier U1, wherein the positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the switch S1 is connected in parallel with the sampling resistor R4, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1, and the method includes the following steps:

[0005] Step 1: The chip is not powered on. Close the switch S1 to short the CSP terminal and GND_K (CSN) terminal of the chip, and measure the voltage difference between the two ends of the external operational amplifier U1 to be V0.

[0006] Step 2, power on the chip, close the switch S1 to short the CSP terminal and GND_K (CSN) terminal of the chip, then the chip has a working current I1 flowing through the simulated contact impedance R2, and the voltage difference between the two ends of the external operational amplifier U1 is measured to be V0';

[0007] Step 3, real-time monitoring of the voltage difference across the external operational amplifier U1, and compensation by loading a constant current I2 through the system loading circuit, so that the voltage difference V0' across the external operational amplifier U1 is consistent with V0.

[0008] According to the Kelvin test method in the chip FT test of the second aspect of the embodiment of the present invention, which is used for overcurrent detection OCP calibration, is applied to the FT test circuit, wherein the FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, and an external operational amplifier U1, wherein the positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1, and the method includes the following steps:

[0009] Step S1, the chip is not powered on, a constant current I2 is pulled by the system pull circuit, and the voltage difference across the external operational amplifier U1 is measured to be Va;

[0010] Step S2, the chip is powered on, at which time the chip has a working current I1 flowing through the simulated contact impedance R2, and the system load circuit continues to load a constant current I2, and the voltage difference across the external operational amplifier U1 is measured to be Va';

[0011] Step S3, real-time monitoring of the voltage difference across the external operational amplifier U1, adjusting the magnitude of the constant current I2 loaded by the system loading circuit, so that the voltage difference Va' across the external operational amplifier U1 is consistent with Va.

[0012] The Kelvin test method in the chip FT test according to the embodiment of the present invention has at least the following beneficial effects: since the GND_P (CSN) terminal is connected to the input terminal of the external operational amplifier U1 and the chip internal operational amplifier, and is in a high impedance state, if the chip has a working current I1, this working current I1 flows from the GND_K (CSN) terminal to the system GND through the contact impedance R2, and will not flow through the contact impedance R3, therefore, the contact impedance R3 has a negligible effect on the voltage difference between the two ends of the external operational amplifier U1 and the voltage difference between the two ends of the chip internal operational amplifier. If the chip is not powered on, there is no working current I1, then when the chip CSP terminal and the GND_K (CSN) terminal are short-circuited or the target calibration current is pulled, there is no working current I1 flowing through the simulated contact impedance R2 of the pin GND_K (CSN), which is equivalent to ignoring the influence of the contact impedance at this time, and the voltage difference V0 / Va across the external operational amplifier U1 is the ideal voltage difference between CSP and GND (CSN) when there is no impedance, so V0 / Va is used as the basis for subsequent compensation. Then the chip is powered on, and the voltage difference across the external operational amplifier U1 is monitored in real time. The system load circuit pulls the corresponding constant current to compensate the voltage difference across the external operational amplifier U1 to V0 / Va, so that the voltage difference across the operational amplifier U1 after compensation can reflect the real voltage of the operational amplifier inside the chip. This method has a simple circuit structure, low cost, and is easy to implement.

[0013] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings;

[0015] Figure 1 This is the schematic diagram of the FT test circuit;

[0016] Figure 2 is a flow chart of a calibration method for detecting OP offset;

[0017] Figure 3 is a flow chart of the OCP calibration method for over-current detection. DETAILED DESCRIPTION

[0018] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0019] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] Reference Figure 1 and Figure 2 The present invention discloses a Kelvin test method in a chip FT test, which is used to detect OP offset calibration and is applied to an FT test circuit. The FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, a switch S1 and an external operational amplifier U1. The positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the switch S1 is connected in parallel with the sampling resistor R4, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1. The method includes the following steps:

[0022] Step 1, the chip is not powered on, and the switch S1 is closed to short the CSP terminal and GND_K (CSN) terminal of the chip. At this time, the chip has no working current I1 flowing through the simulated contact impedance R2, which is equivalent to ignoring the influence of the contact impedance at this time. The voltage difference between the two ends of the external operational amplifier U1 is measured to be V0, that is, the ideal voltage difference between CSP and GND (CSN) when there is no impedance is V0;

[0023] Step 2, power on the chip, close the switch S1 to short the CSP terminal and GND_K (CSN) terminal of the chip, and then the working current I1 flows through the analog contact impedance R2. The voltage difference between the two ends of the external operational amplifier U1 is measured as V0'. At this time, the voltage difference V0' is the voltage difference when there is contact impedance, which cannot accurately reflect the voltage difference of the operational amplifier inside the chip.

[0024] Step 3, real-time monitoring of the voltage difference across the external operational amplifier U1, and compensation by the system loading circuit loading constant current I2, so that the voltage difference V0' across the external operational amplifier U1 is consistent with V0 (that is, according to the difference between V0' and V0, see whether the system loading circuit loads a certain current for compensation. If there is a difference between V0' and V0, the loading circuit needs to load a constant current for compensation, and continuous real-time monitoring is performed, and the voltage difference across the external operational amplifier U1 is consistent with V0 by continuously adjusting the size of the loading current).

[0025] Reference Figure 1 and Figure 3 The present invention discloses a Kelvin test method in chip FT test, which is used for overcurrent detection OCP calibration and is applied to FT test circuit. The FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, and an external operational amplifier U1. The positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1. The method includes the following steps:

[0026] Step S1, the chip is not powered on. At this time, there is no working current I1 flowing through the simulated contact impedance R2, which is equivalent to ignoring the influence of the contact impedance at this time. The system load circuit pulls a constant current I2. This constant current I2 is determined according to how much current OCP detection the chip needs to calibrate. For example, if 360mA overcurrent detection needs to be calibrated, a constant current of 360mA is pulled at this time. The voltage difference between the two ends of the external operational amplifier U1 is Va, that is, the voltage difference between CSP and GND (CSN) is Va when there is no impedance at this time;

[0027] Step S2, the chip is powered on. At this time, the chip has a working current I1 flowing through the simulated contact impedance R2, and the system load circuit continues to load a constant current I2. This constant current I2 is still determined by the OCP detection of how much current the chip needs to calibrate. The voltage difference across the external operational amplifier U1 is Va'. At this time, this voltage difference Va' is the voltage difference across the external operational amplifier U1 when there is impedance, and cannot accurately reflect the voltage difference of the chip's internal operational amplifier;

[0028] Step S3, real-time monitoring of the voltage difference across the external operational amplifier U1, adjusting the size of the constant current I2 pulled by the system load circuit, so that the voltage difference Va' across the external operational amplifier U1 is consistent with Va (that is, according to the difference between Va' and Va, see whether the system load circuit pulls a certain current for compensation. If there is a difference between Va' and Va, then the load circuit needs to pull a certain constant current for compensation. Continuous real-time monitoring is performed, and the voltage difference across the external operational amplifier U1 is consistent with Va by continuously adjusting the size of the load constant current).

[0029] The above detection OP offset calibration method and overcurrent detection OCP calibration method are based on Figure 1In the FT test circuit, since the GND_P (CSN) terminal is connected to the input terminal of the external op amp U1 and the chip internal op amp, it is in a high impedance state. If the chip has a working current I1, this working current I1 flows from the GND_K (CSN) terminal to the system GND through the contact impedance R2, and will not flow through the contact impedance R3. Therefore, the contact impedance R3 has a negligible effect on the voltage difference between the two ends of the external op amp U1 and the voltage difference between the two ends of the chip internal op amp. If the chip is not powered on, there is no working current I1. When the chip CSP terminal and the GND_K (CSN) terminal are short-circuited or the target calibration current is pulled, there is no working current I1 flowing through the simulated contact impedance R2 of the pin GND_K (CSN), which is equivalent to ignoring the influence of the contact impedance at this time. The voltage difference V0 / Va across the external op amp U1 is the ideal voltage difference between CSP and GND (CSN) when there is no impedance, so V0 / Va is used as the basis for subsequent compensation. Then the chip is powered on, and the voltage difference across the external operational amplifier U1 is monitored in real time. The system load circuit pulls the corresponding constant current to compensate the voltage difference across the external operational amplifier U1 to V0 / Va, so that the voltage difference across the operational amplifier U1 after compensation can reflect the real voltage of the operational amplifier inside the chip. This method has a simple circuit structure, low cost, and is easy to implement.

[0030] It is easy for those skilled in the art to understand that the above preferred embodiments can be freely combined and superimposed without conflict.

[0031] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or directly or indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A Kelvin test method in chip FT test, used to detect OP offset calibration, applied to FT test circuit, characterized in that: The FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, a switch S1 and an external operational amplifier U1, the positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the switch S1 is connected in parallel with the sampling resistor R4, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1, and the method includes the following steps: Step 1: The chip is not powered on. Close the switch S1 to short the CSP terminal and GND_K (CSN) terminal of the chip, and measure the voltage difference between the two ends of the external operational amplifier U1 to be V0. Step 2, power on the chip, close the switch S1 to short the CSP terminal and GND_K (CSN) terminal of the chip, then the chip has a working current I1 flowing through the simulated contact impedance R2, and the voltage difference between the two ends of the external operational amplifier U1 is measured to be V0'; Step 3, real-time monitoring of the voltage difference across the external operational amplifier U1, and compensation by loading a constant current I2 through the system loading circuit, so that the voltage difference V0' across the external operational amplifier U1 is consistent with V0.

2. A Kelvin test method in chip FT test, used for overcurrent detection OCP calibration, applied to FT test circuit, characterized in that: The FT test circuit includes a system load circuit, a resistor R1, a simulated contact impedance R2, a simulated contact impedance R3, a sampling resistor R4, and an external operational amplifier U1. The positive end of the sampling resistor R4 is electrically connected to the CSP end of the chip via the series resistor R1, the negative end of the sampling resistor R4 and one end of the simulated contact impedance R2 are respectively connected to the system GND, the other end of the simulated contact impedance R2 is electrically connected to the GND_K (CSN) end of the chip, the positive end of the sampling resistor R4 is also electrically connected to the positive input end of the external operational amplifier U1 and the system load circuit, one end of the simulated contact impedance R3 is electrically connected to the GND_P (CSN) end of the chip, and the other end of the simulated contact impedance R3 is electrically connected to the reverse input end of the external operational amplifier U1. The method includes the following steps: Step S1, the chip is not powered on, a constant current I2 is pulled by the system pull circuit, and the voltage difference across the external operational amplifier U1 is measured to be Va; Step S2, the chip is powered on, at which time the chip has a working current I1 flowing through the simulated contact impedance R2, and the system load circuit continues to load a constant current I2, and the voltage difference across the external operational amplifier U1 is measured to be Va'; Step S3, real-time monitoring of the voltage difference across the external operational amplifier U1, adjusting the magnitude of the constant current I2 loaded by the system loading circuit, so that the voltage difference Va' across the external operational amplifier U1 is consistent with Va.

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