Flow control module for optimizing flow control time sequence of data flow and chip integrated circuit

Abstract

The invention provides a flow control module and a chip integrated circuit for optimizing a flow control time sequence of a data flow, the flow control module comprises a receiving end unit, a data processing unit, a data flow control unit and a sending unit, the receiving unit is used for receiving external data and transmitting the external data to the data processing unit; the data processing unit receives the data from the receiving unit, performs data processing in the data processing unit, obtains a data processing result and transmits the data processing result to the sending unit; the sending unit is used for receiving the data processing result from the data processing unit and outputting the data processing result according to a clock period; and the data flow control unit communicates with the receiving unit and the sending unit and is used for controlling the receiving unit so as to perform flow control on data transmission. According to the technical scheme, flow control of the data flow can be achieved, meanwhile, extra consumed time is reduced, transmission efficiency is improved, and the time sequence requirement is met more easily.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a flow control module and a chip integrated circuit for optimizing data flow control timing. Background Art

[0002] Flow control is a measure to control data transmission by software or hardware. Data flow, as the name implies, is a large amount of data that flows continuously like water. For example, in a network processing device, network data enters from one network port and is output from other network ports after complex routing processing. From the outside of the device, network data flows in and out of the device continuously like water. Assuming that the source device sends data quickly and the destination device receives data slowly, if this speed difference is not controlled, the destination device will inevitably receive excessive data that exceeds its carrying capacity, resulting in discarding or processing errors. For this example, if you want the destination device to correctly receive all data, an effective way is to reduce the average sending speed of the source device, for example, pausing for a period of time after sending part of the data so that the total amount of data it sends does not exceed the carrying capacity of the destination device. This is flow control. For large amounts of continuous data transmission, flow control is essential.

[0003] Figure 1 A schematic diagram of a flow control architecture in the prior art is shown.

[0004] Data transmission within a chip is usually implemented in the form of a bus. A widely used bus architecture is the Advanced Microcontroller Bus Architecture (ARM's AMBA). Take AMBA's AXI bus interface as an example. Figure 1 , its flow control function is realized by the cooperation of two signals in opposite directions, namely the valid signal (valid) and the ready signal (ready). The valid and data signals (data) are sent by the sender, so the two have the same direction, both from the sender to the receiver. Data is the data to be transmitted. The valid signal is 1, indicating that the current data is valid data, and it must be ensured to be correct during transmission. The valid signal is 0, indicating that the current data is invalid data and can be ignored. Ready is sent by the receiver, so its direction is opposite to that of valid / data. Ready is 1, indicating that the receiver can (or is able to) receive data, and ready is 0, indicating that the receiver cannot (or is unable to) receive data. For example Figure 1 As shown in the figure, the direction relationship of valid / data / ready is shown. Both valid and ready are single-bit signals.

[0005] This flow control must comply with the following rules:

[0006] 1. Data data uses valid as a validity indicator.

[0007] 2. The only condition for the receiving end to receive data is that valid and ready are both 1, because valid is 1 at this time, which means that the data is valid and must be passed on, and ready is 1, which means that the receiving end is able to receive the data. If valid is 0, it means that the data is invalid at this time, and the receiving end obviously does not need to receive this data. If ready is 0, it means that the receiving end is unable to receive data at this time, for example, the limited storage space of the receiving end has been filled up by a lot of data received earlier.

[0008] 3. When valid is 1, if ready is continuously 0, valid must remain 1 and cannot become 0 by itself. Data must also remain unchanged. When the valid data sent is not received, it must remain until it is received. Only when ready also becomes 1, and valid and ready are 1 at the same time (the receiving end receives this data), can the sending end update valid and data. It is precisely because when ready is 0, the sending end must keep the valid data unchanged and cannot arbitrarily change new data to achieve the flow control effect. Obviously, for the ready signal, not only the receiving end but also the sending end must detect it.

[0009] In digital logic, any operation must meet the timing requirements. To simply say that the timing requirements are met is that the physical connection path from the transmitter to the receiver should not be too long or too short. If it is too long, the delay (delay is the time delay, that is, the time it takes for data to pass through the connection path) will be too large, and if it is too short, the delay will be too small. Too large or too small delay will cause the timing requirements to not be met (the professional term is called timing violation), which will cause the receiver to be unable to correctly receive (sample) the data. For example, the data sent by the transmitter is 1234, but because of the timing violation, the data actually obtained by the receiver after sampling is 1220.

[0010] Figure 2 A schematic diagram of a flow control model in the prior art is shown.

[0011] See also Figure 2 To simplify the understanding, Figure 2The data flow control timing is described by taking the simplest synchronous receiving and sending model as an example, and both use the rising edge of the clock to work. The sender and the receiver both work under the same clock, and the delay from the clock to both ends is consistent (which means that the sender uses the rising edge of the clock at a certain moment, and the receiver also uses it at the same time). The sender sends valid / data on the rising edge of the clock, and the receiver sends ready on the rising edge of the clock. The sender samples valid / data on the rising edge of the clock, and the receiver also samples valid / data / ready on the rising edge of the clock.

[0012] Figure 3 Show satisfaction Figure 2 Timing diagram of the flow control model timing requirements in the example.

[0013] Figure 4 Shows dissatisfaction Figure 2 Timing diagram of the flow control model timing requirements in the example.

[0014] See also Figure 3 , the figure shows that for Figure 2 The timing diagram of the flow control model described in the flow control model meets the timing requirements. As shown in the figure, at the rising edge of the T0 clock, the transmitter outputs valid and data 8'ha5 as 1, and the receiver outputs ready as 1. Due to the physical delay, the dotted line under T0 in the above figure is not aligned with the rising edge of valid. The misalignment indicates that there is a delay. Because the transmitter sends valid and data at the same time, it can be simply assumed that the output delays of valid and data are consistent. Similarly, the rising edge of ready is not aligned with the rising edge of the T0 clock. At the rising edge of T1, the receiver samples valid / data and ready. At this time, valid and ready are both stable 1, so the receiver can correctly sample data 8'ha5. At this time, the transmitter also samples valid and ready. At this time, both are 1. The transmitter can update and output new data and continue to send valid and new data as 1. If there is no new data to be sent, valid will be changed to 0.

[0015] For comparison, see Figure 4 , the figure shows that for Figure 2The flow control model described in the timing diagram does not meet the timing requirements. As shown in the figure, the sender still sends valid / data at the rising edge of T0, but the valid / data path between the sender and the receiver is very long, resulting in a large delay, and it does not reach the receiver until T1. For the receiver, valid is changing from 0->1 at T1, and the receiver cannot sample a stable 0 or 1, so there is a high probability that the receiver cannot receive data correctly at this time. This example shows that excessive signal delay can easily lead to timing violations.

[0016] Figure 5 A schematic diagram of another flow control model in the prior art is shown.

[0017] Figure 2 The simple model in the figure only includes one send and one receive, but the entire data chain inside the actual chip contains many intermediate components, most of which, such as registers, can both receive and send. Figure 5 As shown in, to simplify the understanding, assume Figure 5 The sender can only send, and the receiver can only receive. Figure 5 , the three registers reg1 / reg2 / reg3 in the middle can both receive data from the left and send data to the right. The data sent by the transmitter is transmitted through the three registers and finally reaches the receiver. In order to maximize the transmission efficiency and allow the data from the transmitter to reach the receiver as quickly as possible, the ready signal of the receiver must be directly connected to the transmitter and the three registers, trying to make them receive ready at the same time. Only by directly connecting to ready can the data from the transmitter reach the receiver in the shortest total time, but this is likely to cause a timing violation of the ready signal. Because the physical location of the transmitter and the three registers is definitely far from the receiver, the delay of ready from the receiver to the transmitter and the three registers is inconsistent. The delay to reg3 may be the smallest, and the delay to the transmitter may be the largest. From the timing requirements, it can be seen that excessive delay is likely to cause timing violations, resulting in abnormal operation of the entire system.

[0018] Usually, for long-distance transmission of signals, pipeline registers are inserted between components, commonly known as beats. For example, assuming that there is no reg2 between reg1 and reg3 in the above figure, the signals are directly connected and far apart, and the signal delay from reg1 to reg3 is very large, reg2 can be inserted in the middle to turn a long-distance connection into two short-distance connections. The original timing requirements for reg1->reg3 have become the timing requirements for reg1->reg2 and reg2->reg3, and reg2 plays a beat role. However, since the ready signal used in flow control is very special, it only indicates whether the receiving end can receive data at the next moment (the moment generally refers to the rising edge of the clock). For example, the receiving end outputs ready 1 at time T0 in the previous figure, which means that it can receive data at time T1. If the receiving end outputs ready 0 at time T1, it means that it cannot receive data at the next moment. Ready only indicates the state of the receiving end, so it can be changed at will by the receiving end and has nothing to do with valid / data. Therefore, if you want to beat this kind of flow control, you cannot beat it directly like a conventional co-directional signal. Take conventional co-directional signal transmission as an example. If a signal in valid / data has a timing violation, valid / data can be beat once or multiple times (valid is beaten as many times as data is beaten to keep the number of beats consistent). However, this kind of beating is wrong for reverse valid / ready flow control because of the characteristics of ready itself.

[0019] Figure 6 A schematic diagram of another flow control model in the prior art is shown.

[0020] The purpose of tapping is to eliminate excessive delays by inserting registers, but valid / ready cannot be simply tapped, so the conventional approach to this type of flow control is to let the receiver of ready regenerate a new ready and send the new ready to the upstream data sender. Figure 6 As shown in the flow control model, the receiver on the far right sends out ready, which only indicates whether the receiver can receive data. The receiver samples data4 with valid4 and ready. Intermediate component 3 (usually a fifo-type memory) sends out ready1, which only indicates whether intermediate component 3 can receive data. Intermediate component 3 samples data3 with valid3 and ready1, and updates outputs valid4 and data4 with valid4 and ready. The same is true for the others. Whether it is ready or ready1 / 2 / 3, they are only connected to the adjacent ones, with a short distance, making it easier to meet timing requirements.

[0021] However, there are also disadvantages. First, the intermediate component has to generate a new ready signal, which is directly connected to the same ready signal. Compared with multiple components, it takes extra time and reduces the efficiency of data transmission. Second, although inserting intermediate components can improve the timing, valid / ready flow control still needs to be used frequently, which is not as simple and easy to use as the conventional one-way beat without ready, and it is easier to meet the timing requirements.

[0022] To this end, a technical solution is needed that can achieve data flow control while reducing extra time consumption, improving transmission efficiency, and making it easier to meet timing requirements. Summary of the invention

[0023] The present invention aims to provide a flow control module and a chip integrated circuit for optimizing the timing of data flow control, which can realize data flow control while reducing extra consumption time, improving transmission efficiency, and more easily meeting timing requirements.

[0024] According to one aspect of the present invention, a flow control module for optimizing the flow control timing of a data stream is provided, comprising: a receiving unit, a data processing unit, a data flow control unit, and a sending unit, wherein:

[0025] The receiving unit is used to receive external data and transmit the external data to the data processing unit;

[0026] The data processing unit receives the data from the receiving unit, processes the data inside the data processing unit, obtains the data processing result and transmits it to the sending unit;

[0027] The sending unit is used to receive the data processing result from the data processing unit and output the data processing result according to a clock cycle;

[0028] The data flow control unit communicates with the receiving unit and the sending unit, and controls the receiving unit, thereby performing flow control on data transmission.

[0029] According to some embodiments, the receiving unit is configured to: receive an external first data signal and a first valid signal, and a first flow control signal from the data flow control unit, and store the first data signal according to the first valid signal, send a first storage feedback signal to the data flow control unit according to the external data reception situation, and output a second data signal and a second valid signal to the data processing unit according to the first flow control signal from the data flow control unit;

[0030] The data processing unit is configured to: receive the second data signal and the second valid signal from the receiving unit, perform data processing on the second data signal according to the second valid signal inside the data processing unit, and convert the data processing result into a third data signal and a third valid signal and transmit them to the sending unit;

[0031] The sending unit is configured to: receive the third data signal, the third valid signal and a data read signal from the data processing unit, store the third data signal according to the third valid signal, and output a fourth data signal and a fourth valid signal to the outside according to a clock cycle.

[0032] According to some embodiments, the data flow control unit is configured to output the first flow control signal to the receiving unit according to the first storage feedback signal from the receiving unit, the fourth valid signal from the sending unit, and the data read signal from the outside.

[0033] According to some embodiments, the data flow control unit includes a counter, and when a count value of the counter is non-zero, outputs a valid read request signal to the receiving unit.

[0034] According to some embodiments, the counter is configured to:

[0035] The counter is configured according to the clock cycle, and the value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal.

[0036] According to some embodiments, the counter is further configured to:

[0037] When the fourth valid signal output by the sending unit and the data read signal are both at high levels, the counter is configured according to the clock cycle, and the value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal, plus 1.

[0038] According to some embodiments, the sending unit is configured to:

[0039] When the receiving unit is in an empty state, the first storage feedback signal outputs a high level.

[0040] According to some embodiments, the data flow control unit is configured as:

[0041] When the first storage feedback signal outputs a low level and the read request signal is valid, the data flow control unit outputs the first flow control signal to control the receiving unit to output the stored data.

[0042] According to some embodiments, the capacity of the sending unit is at least the sum of the maximum delay between the receiving unit and the sending unit of the flow control module, the read delay of the receiving unit, and the write and read delay of the sending unit.

[0043] According to another aspect of the present invention, there is provided a chip integrated circuit, characterized in that it comprises: a flow control module as described in any one of the above items.

[0044] According to an embodiment of the present invention, the data flow control part and the data processing are separated by adding the data flow control unit. The data flow control unit is responsible for controlling the timing of the transmission interface data, and the data processing unit is responsible for calculation or business protocol processing, etc., which is convenient for independent development and timing optimization. Valid / ready flow control is used for both the receiving unit and the sending unit interface, and the data processing unit only needs to use valid, not ready. It can reduce the time consumption caused by signal recognition, improve data processing efficiency, simplify the design, and be more friendly to timing.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0047] Figure 1 A schematic diagram of a flow control architecture in the prior art is shown.

[0048] Figure 2 A schematic diagram of a flow control model in the prior art is shown.

[0049] Figure 3 Show satisfaction Figure 2 Timing diagram of the flow control model timing requirements in the example.

[0050] Figure 4 Shows dissatisfaction Figure 2 Timing diagram of the flow control model timing requirements in the example.

[0051] Figure 5 A schematic diagram of another flow control model in the prior art is shown.

[0052] Figure 6 A schematic diagram of another flow control model in the prior art is shown.

[0053] Figure 7 A schematic diagram of a flow control module device for optimizing flow control timing of data streams according to an example embodiment is shown.

[0054] Figure 8 A timing diagram is shown that satisfies the timing requirements of the flow control module according to an example.

[0055] Fig. 9 A schematic diagram of the application process of the flow control module according to an example embodiment is shown. DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0057] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0058] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0059] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0060] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0061] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0062] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0063] Timing control is an important aspect in digital circuit design, especially in synchronous circuits. It involves ensuring that data is correctly transmitted between different parts of the circuit, avoiding problems such as clock deviation, competition conditions, glitches, etc., and ensuring that data reaches its destination at the right time. Timing control technology is crucial for high-performance processors, communication systems, storage systems and other fields.

[0064] In complex SoC designs, ensuring timing closure for the entire system is a challenge. Designers must balance performance, power, and area to achieve the best timing results.

[0065] To this end, the present invention proposes a flow control module and chip integrated circuit that optimize the timing of data flow control, which can achieve data flow control while reducing additional consumption time, improving transmission efficiency, and more easily meeting timing requirements. According to an embodiment, by separating the data flow control part and the data processing, the data flow control unit is responsible for controlling the timing of the transmission interface data, and the data processing unit is responsible for calculation or business protocol processing, etc., which is convenient for independent development and timing optimization. If you want to improve the internal timing of the flow control module, just insert valid / data into the pipeline and beat it, which is very convenient, with good results and fewer iterations.

[0066] According to some embodiments, valid / ready flow control is used for both the receiving unit and the sending unit interfaces, and the data processing unit only needs to use valid, not ready, which can reduce the time consumption caused by signal recognition, improve data processing efficiency, simplify the design, and be more friendly to timing.

[0067] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0068] Figure 7 A schematic diagram of a flow control module device for optimizing flow control timing of data streams according to an example embodiment is shown.

[0069] See also Figure 7According to an example embodiment, a flow control module for optimizing data flow flow control timing includes: a receiving unit 01, a data processing unit 02, a data flow control unit 03, and a sending unit 04, wherein the receiving unit 01 is used to receive external data and transmit the external data to the data processing unit 02; the data processing unit 02 receives data from the receiving unit, and processes the data inside the data processing unit 02 to obtain a data processing result and transmit it to the sending unit 04; the sending unit 04 is used to receive the data processing result from the data processing unit 02, and output the data processing result according to a clock cycle; the data flow control unit 03 communicates with the receiving unit 01 and the sending unit 04, and controls the receiving unit 01, so as to perform flow control on data transmission.

[0070] According to some embodiments, the receiving unit 01 and the sending unit 04 adopt a valid / ready flow control protocol, and the data input / output interface of the data processing unit 02 only includes valid signals and data signals in the same direction.

[0071] According to some embodiments, see Figure 7 The receiving unit 01 is configured to: receive an external first data signal (data1) and a first valid signal (valid1), and a first flow control signal (read) from the data flow control unit 03, and store the first data signal (data1) according to the first valid signal (valid1), send a first storage feedback signal (empty) to the data flow control unit 03 according to the external data reception situation, and output a second data signal (data2) and a second valid signal (valid2) to the data processing unit 02 according to the first flow control signal (read) from the data flow control unit 03.

[0072] According to some embodiments, the data processing unit 02 is configured to: receive the second data signal (data2) and the second valid signal (valid2) from the receiving unit 01, perform data processing on the second data signal (data2) according to the second valid signal (valid2) within the data processing unit 02, and convert the data processing result into a third data signal (data3), and transmit the third valid signal (valid3) to the sending unit 04.

[0073] According to some embodiments, the sending unit 04 is configured to: receive the third data signal (data3), the third valid signal (valid3) and the data read signal (ready4) from the data processing unit 02, store the third data signal (data3) according to the third valid signal (valid3), and output the fourth data signal (data4) and the fourth valid signal (valid4) to the outside according to the clock cycle.

[0074] According to some embodiments, the data flow control unit 03 is configured as: including a counter 0301, outputting the first flow control signal (read) to the receiving unit 01 based on the first storage feedback signal (empty) from the receiving unit 01, the fourth valid signal (valid4) from the sending unit 04 and the data read signal (ready4) from the outside.

[0075] According to some embodiments, see Figure 7 , both the receiving unit 01 and the sending unit 04 of the flow control module use valid / ready flow control, the receiving unit 01 on the left is responsible for receiving data, and the sending unit 04 on the right is responsible for sending data. The receiving unit 01 and the sending unit 04 can be random access memory (RAM). The flow control module coordinates the receiving RAM and the sending RAM on both sides to jointly achieve the flow control function.

[0076] According to some embodiments, the data processing module 02 is used to implement business needs, and its function does not need to be concerned about in this design scheme. The key point is that the data interface of this module only contains valid / data in the same direction, and there is no ready in the opposite direction. In other words, the flow control module has an external data interface that uses valid / ready flow control, while only valid is used internally, and the data flow cannot be paused during internal data processing. Such an architecture separates the data flow control part from the data service part. The data flow control unit 03 is only responsible for controlling the timing of the transmission interface data, and the data processing unit 02 is responsible for calculation or business protocol processing, etc., which is convenient for independent development and timing optimization. If you want to improve the internal timing of the flow control module, just insert valid / data into the pipeline to beat it, which is very convenient, with good results and fewer iterations.

[0077] According to some embodiments, in the existing technical solutions, the flow control part and the actual business part are not separated, so the business part will always be brought into the valid / ready flow control, and any processing must detect the status of valid and ready. It can also be said that any processing may have a timing violation of ready, resulting in a business error. In the solution of the present invention, the data processing unit 02 part does not have ready. Compared with the business processing with ready, it reduces the need to generate many new readys step by step, the design is simpler, and the resource consumption is less. In addition, any processing is unlikely to have a timing violation of ready, which reduces the probability of timing errors. Using valid / ready for flow control requires always checking the timing of the two signals valid and ready, but without ready, only the timing of the valid signal needs to be checked. Obviously, the conditions are more relaxed and easier to meet the requirements, which can reduce the time consumption of data processing and further improve the efficiency of data processing.

[0078] According to some embodiments, the counter 0301 is configured to output a valid read request signal to the receiving unit 01 when the count value of the counter 0301 is non-zero. The flow control module 03 has a counter 0301 inside, and the count value is represented by cnt, which is not 0 by default. As long as cnt is not 0, a valid read request signal (rd_req) is generated, assuming that 1 represents valid. When cnt is 0, the rd_req value is 0. Therefore, rd_req is the result of taking or taking each bit of cnt, that is, rd_req = |cnt, and it is obvious that the initial value of rd_req is 1.

[0079] According to some embodiments, the sending unit 04 is configured as follows: when the receiving unit 01 is in an empty state, the first storage feedback signal (empty) outputs a high level. Assuming the initial state, the system has not started to transmit data, the receiving unit 01 does not store any data and is in an empty state (the empty state means that there is no data stored in the RAM. If there is data in the RAM but it is all read out, it is also in an empty state. Corresponding Figure 7 Therefore, only when the receiving unit 01 is not empty, a valid first storage feedback signal (empty) is generated and output to the data flow control unit 03.

[0080] According to some embodiments, the data flow control unit 03 is configured as follows: when the first storage feedback signal (empty) outputs a low level and the read request signal is valid, the data flow control unit 03 outputs the first flow control signal (read) to control the receiving unit 01 to output the stored data, that is, set read = rd_req&(~empty), that is, when cnt is not 0 and the receiving RAM is not empty, the data flow control unit 03 reads the receiving RAM to allow the receiving RAM to output data.

[0081] According to some embodiments, the storage capacity of the receiving unit 01 is at least 2 data, so that the data flow is continuous. In order to ensure that the receiving RAM can output continuously and consume the least hardware resources, the receiving RAM has a capacity of at least 2 data to achieve ping-pong output.

[0082] Figure 8 A timing diagram is shown that satisfies the timing requirements of the flow control module according to an example.

[0083] See also Figure 8 , the figure shows a timing diagram that meets the timing requirements of the flow control module according to an example embodiment, and the maximum capacity stores at least 2 data, so that the data can flow continuously. For example, at T0, data 1 enters the receiving ram (at this time, the ram stores 1 data, namely data 1), and at T1, data 2 enters the receiving ram (at this time, the ram stores 2 data, namely data 1 and data 2, reaching the maximum capacity limit and is full). At the same time, at T1, the receiving ram outputs data 1, so at T2, data 3 can enter the receiving ram (at this time, the ram stores 2 data, namely data 2 and data 3, reaching the maximum capacity limit and is full. Data 3 can be stored because data 1 has been output at the previous moment T1), and at this time, the receiving ram can output data 2, and the next moment the ram can receive data 4. In this way, the receiving ram is continuously input and output.

[0084] According to some embodiments, the capacity of the sending unit 04 is at least the sum of the maximum delay between the receiving unit 01 and the sending unit 04 of the flow control module, the read delay of the receiving unit 01, and the write and read delay of the sending unit 04. Figure 7 as well as Figure 8 , from the output of the receiving RAM to the input of the sending RAM, there is no reverse ready in this path. Once the data is output by the receiving RAM, it can only be passed down in sequence without stopping in the middle. Therefore, the sending RAM must be able to store all the data output by the receiving RAM, including the data still in the data processing module. The capacity of the sending RAM must be large enough to cover the maximum delay of the data path between the two RAMs.

[0085] According to some embodiments, see Figure 8 At T0, the default value of cnt is X (X is not equal to 0), the default value of rd_req is 1, and the default value of empty is 1. Assuming that only one data enters the receiving ram, empty changes from 1 to 0, and a valid read signal is generated at T1. At this time, read reads the only 1 data in the receiving ram, and empty changes from 0 to 1, so the subsequent reads are all 0 and no longer read the ram. Because the read signal is generated at T1, the receiving ram outputs valid valid2 and data2 at T2 (the above figure is only to show how to calculate the delay, and there is no need to draw data). Assuming that the data processing module takes at least 4 cycles to output, it outputs valid valid3 at T6. Read the sending ram at T7, and output valid valid4 at T8. Therefore, the maximum delay from reading the receiving ram to sending the ram outputting valid is delay1+delay2+delay3+delay4 in the figure, which is 8. From the perspective of saving resources, the sending ram capacity only needs to be enough to store 8 data.

[0086] According to some embodiments, the counter 0301 is configured as follows: the counter 0301 is configured according to the clock cycle, and the value of the counter 0301 in the next cycle is configured to be the value of the counter 0301 in the current cycle minus the level value of the first flow control signal (read). Assuming that ready4 is always 0, the 8 data in the sending ram cannot be truly output, which means that the receiving ram must stop outputting after outputting 8 data, that is, under this condition, the receiving ram can only be read 8 times at most, and rd_req must be set to 0 after reading the receiving ram 8 times, so the default value of cnt can be set to X=8, and cnt (new value)=cnt (old value)-read.

[0087] According to some embodiments, the counter 0301 is further configured as follows: when the fourth valid signal output by the sending unit 04 and the data read signal are both at a high level, the counter 0301 is configured according to the clock cycle, and the value of the counter 0301 in the next cycle is configured to be the value of the counter 0301 in the current cycle minus the level value of the first flow control signal (read), plus 1. As the number of reads increases, cnt is reduced in sequence until it is reduced to 0, and rd_req is also 0 to stop reading the receiving ram. However, cnt is 0, which means that the flow control module no longer reads the receiving ram, this ram does not output, and the entire data flow stops, so cnt cannot be reduced but not increased. From the background knowledge of valid / ready flow control, it can be known that when valid4 / ready4 of the sending ram are both valid, it means that the sending ram has actually output data. Therefore, cnt (new value) = cnt (old value) - read + (valid4 & ready4) can be set to allow the data flow to continuously enter and exit this component. The function of subtracting read is to make cnt smaller until it is 0, to prevent the default value of cnt from being too large and reading too much data beyond the capacity limit of the sending ram. The function of adding (valid4&ready4) is to make cnt larger, to prevent cnt from being 0 all the time and stopping the data flow. In summary, the meaning of cnt (new value) = cnt (old value) - read + (valid4&ready4) is that subtracting a read means outputting a data from the receiving ram, and adding a (valid4&ready4) means outputting a data from the sending ram. The addition and subtraction effects cancel each other out, allowing the data flow to pass through this component continuously.

[0088] Fig. 9 A schematic diagram of the application process of the flow control module according to an example embodiment is shown.

[0089] See also Fig. 9 , the figure shows a schematic diagram of the application process of the flow control module. First, the flow control module is divided into three parts, namely the receiving and sending interfaces responsible for input and output at both ends and the data processing unit 02. Among them, the receiving and sending interfaces both use valid / ready flow control, and the middle data processing unit 02 only needs to transmit valid / data without using ready. Simplify the design and optimize the timing. Set the capacity of the receiving side RAM to at least 2 data, and the data flow here can be guaranteed to be continuous through ping-pong output. After that, determine the maximum input to output delay of the business processing of the flow control module, assuming it is A. Then, set the capacity of the sending side RAM to A+constant B, and this constant B depends on the read delay of the receiving RAM and the write and read delay of the sending RAM.

[0090] According to some embodiments, the default value of the counter is the maximum delay between the receiving unit and the sending unit of the flow control module, as well as the sum of the read delay of the receiving unit and the write and read delay of the sending unit. Generally speaking, once the design is completed, the read delay of the receiving RAM and the write and read delay of the sending RAM are fixed, so they are considered to be constants. Finally, when configuring the flow control timer in the flow control module, let the default value of the flow control counter 0301cnt be A+B, and let the next moment cnt = current moment cnt-read+(valid&ready). Read is the read enable signal of the receiving RAM, and valid and ready are the output flow control interface signals of the sending RAM.

[0091] According to some embodiments, the design scheme of the present invention can be applied to the design of a chip integrated circuit, wherein the chip integrated circuit includes: the flow control module as described above, which is used for data flow control inside the chip, so that the data flow can be processed efficiently and quickly.

[0092] According to some embodiments, in the design scheme of the present invention, the data flow control part and the data service part are separated, the data flow control unit part is responsible for controlling the timing of the transmission interface data, and the data processing unit is responsible for calculation or service protocol processing, etc., which is convenient for their independent development and their respective timing optimization. If you want to improve the internal timing of the flow control module, just insert valid / data into the pipeline and beat it, which is very convenient, with good results and fewer iterations. Valid / ready flow control is used for both the receiving unit and the sending unit interfaces, and the data processing unit only needs to use valid, not ready, which can reduce the time consumption caused by signal recognition, improve data processing efficiency, simplify the design, and be more friendly to timing.

[0093] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0094] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0097] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0099] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A flow control module for optimizing the flow control timing of data streams, characterized in that: include: A receiving unit, a data processing unit, a data flow control unit, and a sending unit, wherein: The receiving unit is used to receive external data and transmit the external data to the data processing unit; The data processing unit receives the data from the receiving unit, processes the data inside the data processing unit, obtains the data processing result and transmits it to the sending unit; The sending unit is used to receive the data processing result from the data processing unit and output the data processing result according to a clock cycle; The data flow control unit communicates with the receiving unit and the sending unit, and controls the receiving unit, thereby performing flow control on data transmission.

2. The flow control module according to claim 1, characterized in that: The receiving unit is configured to: receive an external first data signal and a first valid signal, and a first flow control signal from the data flow control unit, and store the first data signal according to the first valid signal, send a first storage feedback signal to the data flow control unit according to the external data reception situation, and output a second data signal and a second valid signal to the data processing unit according to the first flow control signal from the data flow control unit; The data processing unit is configured to: receive the second data signal and the second valid signal from the receiving unit, perform data processing on the second data signal according to the second valid signal inside the data processing unit, and convert the data processing result into a third data signal and a third valid signal and transmit them to the sending unit; The sending unit is configured to: receive the third data signal, the third valid signal and a data read signal from the data processing unit, store the third data signal according to the third valid signal, and output a fourth data signal and a fourth valid signal to the outside according to a clock cycle.

3. The flow control module according to claim 2, characterized in that: The data flow control unit is configured to output the first flow control signal to the receiving unit according to the first storage feedback signal from the receiving unit, the fourth valid signal from the sending unit, and the data read signal from the outside.

4. The flow control module according to claim 3, characterized in that: The data flow control unit comprises a counter, and when the count value of the counter is non-zero, the counter outputs a valid read request signal to the receiving unit.

5. The flow control module according to claim 4, characterized in that: The counter is configured as follows: The counter is configured according to the clock cycle, and the value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal.

6. The flow control module according to claim 4, characterized in that: The counter is also configured as: When the fourth valid signal output by the sending unit and the data read signal are both at high levels, the counter is configured according to the clock cycle, and the value of the counter in the next cycle is configured to be the value of the counter in the current cycle minus the level value of the first flow control signal, plus 1.

7. The flow control module according to claim 2, characterized in that: The sending unit is configured as follows: When the receiving unit is in an empty state, the first storage feedback signal outputs a high level.

8. The flow control module according to claim 2, characterized in that: The data flow control unit is configured as follows: When the first storage feedback signal outputs a low level and the read request signal is valid, the data flow control unit outputs the first flow control signal to control the receiving unit to output the stored data.

9. The flow control module according to claim 1, characterized in that: The capacity of the sending unit is at least the sum of the maximum delay between the receiving unit and the sending unit of the flow control module, the read delay of the receiving unit, and the write and read delay of the sending unit.

10. A chip integrated circuit, characterized in that: include: A flow control module as described in any one of claims 1 to 9.

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