Clock tree generation method, medium and electronic equipment

Abstract

The invention is applied to the technical field of integrated circuits, and provides a clock tree generation method, a medium and electronic equipment, and the method comprises the steps: obtaining a netlist file of a circuit, and recognizing a clock network according to a network identifier in the netlist file. Identifying the type of the device according to the identification information and the like of the device in the netlist file, and determining the pin information of the device; and determining a clock link according to the connection relationship of the devices in the netlist file. Furthermore, the flow direction of the clock signal can be determined according to the clock link and the pin information of the device. The electronic equipment can automatically draw the clock tree, and the circuit development efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a clock tree generation method, a medium and an electronic device. Background Art

[0002] The circuit system of electronic equipment usually includes a clock circuit that generates a clock signal, which can also be called a clock network. The clock network outputs the clock signal to each clock-demanding device that needs the clock signal, so that the clock-demanding devices can work in an orderly manner according to the clock signal. In order to facilitate the analysis of the flow of clock signals in the circuit system, developers usually need to draw the corresponding clock tree. The architecture diagram of the clock tree includes information such as the clock source, the flow of clock signals, and the frequency of clock signals.

[0003] However, the scale of current circuit systems is getting larger and larger, which makes the design of clock circuits more complex. In addition, the application scenarios of circuit systems may change, which may cause the clock requirements of circuit systems to change. For example, it is necessary to add a new clock source, modify the clock frequency, etc., which requires frequent modification of the clock tree architecture diagram. Due to the lack of automatic methods, developers need to spend a lot of time drawing clock tree architecture diagrams, which reduces the development efficiency of circuit systems. Summary of the invention

[0004] The present application provides a clock tree generation method, medium and electronic device, which can identify the types of various devices and the flow direction of clock signals according to a netlist file, and then automatically draw a clock tree.

[0005] In a first aspect, a clock tree generation method is provided, which is applied to an electronic device, and the method includes: obtaining a network identification of at least one network in a circuit system, identification information of a device in at least one network, and a connection status between the devices; determining a clock network in at least one network according to the network identification of at least one network, the clock network being used to output at least one clock signal; determining identification information of at least one device in the clock network and a connection relationship between at least one device and other devices in the circuit system; determining a type of at least one device according to the identification information of at least one device; and, determining a flow direction of at least one clock signal in the circuit system according to the connection relationship of at least one device; and generating a clock tree corresponding to the circuit system according to the type of at least one device and the flow direction of at least one clock signal.

[0006] In the above scheme, the network identification of the circuit system, the identification information of the device, and the connection status between the devices can be obtained from the netlist file of the circuit system. By identifying the network identifications of multiple networks, the clock network can be identified. Then, based on the identification information of the device in the circuit system, the clock source device, the clock conversion device, and the clock demand device connected to the clock network can be identified. In addition, based on the pin connection relationship of the device in the netlist file, the flow direction of the clock signal can be determined. Finally, a clock tree can be drawn according to the flow direction of each device and the clock signal. In this way, there is no need for developers to spend a lot of time drawing the clock tree. The method can automatically draw the clock tree, thereby improving the development efficiency of the circuit system.

[0007] In combination with the first aspect, in some implementations, the method further includes: determining a clock source device in at least one device of the clock network based on identification information of at least one device, the clock source device being used to generate a clock signal.

[0008] In the above scheme, the electronic device can identify the clock source device according to the device code, bit number, keyword and other identification information. For example, if the device name includes "XTAL", such as "XTAL10", the device can be considered as a crystal oscillator. In this way, the electronic device can identify the device type in the circuit system, and then the method can automatically draw the clock tree, without developers spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0009] In combination with the first aspect, in some implementations, the method also includes: obtaining identification information of devices connected to the clock network based on identification information of devices in at least one network in the circuit system and connection status between devices; determining a clock demand device based on the identification information of the devices connected to the clock network, where the clock demand device is a device that consumes a clock signal.

[0010] In the above scheme, if the device is connected to a clock source device and the device is not a small device or a small device that can be penetrated, it can be considered as a device that needs to use a clock signal, that is, a clock demanding device. In this way, the electronic device can identify the device type in the circuit system, and then the method can automatically draw a clock tree, without developers spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0011] In combination with the first aspect, in some implementations, the method further includes: determining a clock conversion device in at least one device of the clock network based on identification information of at least one device, the clock conversion device being used to change a parameter value of the clock signal.

[0012] In the above scheme, the electronic device can identify the clock conversion device according to the device's code, bit number, keyword and other identification information. For example, if the device name includes "MUX", the device can be considered to be a multiplexer. In this way, the electronic device can identify the device type in the circuit system, and then the method can automatically draw the clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0013] In combination with the first aspect, in some implementations, the method also includes: generating a clock tree corresponding to the circuit system based on a clock source device, a clock conversion device, a clock demand device, and the flow direction of at least one clock signal, the clock tree including parameter values ​​of at least one clock signal at the pins of the clock source device, the clock conversion device, and the clock demand device.

[0014] In the above scheme, the electronic device can obtain the specifications of each clock device according to the type of clock device identified, and then calculate the parameter size of the clock signal at each pin, and mark the parameters of the clock signal in the clock tree. This method can automatically draw a clock tree without developers spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0015] In combination with the first aspect, in some implementations, the method further includes: obtaining device identification configuration data, the device identification configuration data including a correspondence between identification information and a type of at least one device; and determining the type of at least one device based on the device identification configuration data and the identification information of at least one device.

[0016] In the above scheme, the electronic device identifies the type of the device, which can be obtained based on the device identification configuration data. The device identification configuration data can be preset by the user in advance, or it can be obtained by the electronic device 100 from the device identification database, which includes a large number of correspondences between device identifications and device types. In this way, the electronic device can identify the device type in the circuit system, and then the method can automatically draw a clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0017] In conjunction with the first aspect, in some implementations, the device identification configuration data comes from a device identification database connected to the electronic device.

[0018] In combination with the first aspect, in some implementations, the method also includes: obtaining network identification configuration data, the network identification configuration data including a correspondence between at least one network identification and a network type; and determining a clock network in at least one network based on the network identification configuration data and the network identification of at least one network.

[0019] In the above scheme, the electronic device identifies the type of network, which can be obtained based on the network identification configuration data. The network identification configuration data can be preset by the user in advance, or it can be obtained by the electronic device 100 from the network identification database, which includes a large number of correspondences between network identifications and network types. In this way, the electronic device can identify the network type in the circuit system, and then the method can automatically draw a clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0020] In conjunction with the first aspect, in some implementations, the network identification configuration data comes from a network identification database connected to the electronic device.

[0021] In combination with the first aspect, in some implementations, the method also includes: determining a netlist file corresponding to the circuit system; parsing the netlist file to obtain the network identification of at least one network in the circuit system and the identification information of the devices in at least one network and the connection status between the devices.

[0022] In the above scheme, the electronic device can obtain the netlist file of the circuit system, and according to the type of the device in the netlist file and the direction of the clock signal, a clock tree can be drawn. In this way, the developer does not need to spend a lot of time drawing the clock tree. The method can automatically draw the clock tree, thereby improving the development efficiency of the circuit system.

[0023] In combination with the first aspect, in some implementations, the identification information of the at least one device includes one or more of a code, a bit number, and a keyword of the at least one device.

[0024] In combination with the first aspect, in some implementations, the circuit system also includes one or more of a power supply network and a bus network; the clock source device includes one or more of a crystal oscillator, a clock oscillator, a resonant tank circuit, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; the clock conversion device includes one or more of a frequency synthesizer, a divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; and the parameter value of the clock signal includes one or more of frequency, signal strength, and phase.

[0025] In a second aspect, the present application provides an electronic device, characterized in that it includes a processor and a memory, the memory is used to store instructions, and the processor is used to execute instructions. When the processor executes the instructions, the method described in the first aspect is performed.

[0026] In a third aspect, the present application provides a computer-readable storage medium, characterized in that instructions are stored in the computer-readable storage medium, and when the instructions are run on a computing device, the method described in the first aspect is executed.

[0027] In a fourth aspect, the present application provides a computer program product, characterized in that the computer program product includes computer instructions, and when the computer program product is executed by a computing device, the computing device executes the method described in the first aspect.

[0028] In summary, through the clock tree generation method, medium and electronic device provided by this application, the electronic device can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments are briefly introduced below.

[0030] Figure 1 It is a schematic diagram of a clock tree structure provided in an embodiment of the present application;

[0031] Figure 2 It is a flowchart of a clock tree generation method provided in an embodiment of the present application;

[0032] Figure 3 It is a structural schematic diagram of a clock tree generation system provided in an embodiment of the present application;

[0033] Figure 4 It is a flowchart of a clock tree generation method in which a database including a network identification database and a device identification database is provided in an embodiment of the present application;

[0034] Figure 5 This is a schematic diagram of an interface for obtaining a netlist file provided in an embodiment of the present application;

[0035] Figure 6 is a circuit structure diagram of a circuit system provided in an embodiment of the present application;

[0036] Figure 7 is a schematic diagram of a netlist file of a circuit system provided in an embodiment of the present application;

[0037] Figure 8 It is an interface data for modifying network identification configuration data provided by an embodiment of the present application;

[0038] Fig. 9 It is a flowchart of a clock device identification method provided in an embodiment of the present application;

[0039] Fig.10 This is a schematic diagram of an interface of device pin information provided by an embodiment of the present application;

[0040] Fig.11 This is a schematic diagram of an interface of clock link information provided by an embodiment of the present application;

[0041] Fig.12 It is a schematic diagram of an interface including clock link information of a clock link structure provided in an embodiment of the present application;

[0042] Fig.13 This is a schematic diagram of an interface for modifying clock link information provided in an embodiment of the present application;

[0043] Fig.14 This is a schematic diagram of an interface for displaying a generated clock tree provided in an embodiment of the present application;

[0044] Fig.15 It is a flowchart of a clock tree generation method in a database including a device identification database provided by an embodiment of the present application;

[0045] Fig.16 It is a flowchart of a clock tree generation method in a database including a network identification database provided in an embodiment of the present application;

[0046] Fig.17 It is a flowchart of a clock tree generation method without a database provided in an embodiment of the present application;

[0047] Fig.18 It is a structural schematic diagram of a clock tree generating device provided in an embodiment of the present application;

[0048] Fig.19 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] Illustrative embodiments of the present application include, but are not limited to, clock tree generation methods, media, and electronic devices.

[0050] The circuit system is composed of multiple circuit networks, such as power network, clock network, bus network, etc. The clock network usually connects the clock demand device, generates and processes the clock signal, and then outputs the processed clock signal to the clock demand device.

[0051] The devices in the clock network can be specifically divided into clock source devices and clock conversion devices. In addition, the clock network can include one or more clock source devices and clock conversion devices, that is, the same circuit system can include one or more clock signals.

[0052] Clock source devices are used to generate clock signals, such as crystal oscillators (crystal oscillators), clock oscillators, resonant tank circuits, resistor-capacitor oscillators (RC oscillators), silicon oscillators, and atomic clocks. Crystal oscillators can also be specifically divided into voltage-controlled crystal oscillators, constant temperature crystal oscillators, and vehicle-mounted crystal oscillators. Atomic clocks can also be specifically divided into cesium atomic clocks, hydrogen atomic clocks, and rubidium atomic clocks. Clock source devices can exist alone in a circuit system or be integrated with other devices. For example, clock-demanding devices such as field-programmable gate arrays (FPGAs) and clock management units (CMUs) have clock sources that generate clock signals. Clock-demanding devices that integrate these clock sources can use the clock signals generated by these clock sources, and these clock signals can also be used by other clock-demanding devices.

[0053] Clock conversion devices are used to process clock signals, such as changing the frequency, phase, voltage, etc. of clock signals. Clock conversion devices may include frequency synthesizers, frequency dividers, phase locked loops (PLLs), direct digital synthesizers (DDSs), clock drivers, etc.

[0054] Clock-demanding devices are logic devices that require clock signals, such as FPGA, central processing unit (CPU), application specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc.

[0055] For example, Figure 1 FIG. 1 shows a schematic diagram of the structure of a clock tree. Figure 1 As shown, the clock tree includes external input frequency A and input frequency B. The range of input frequency A is 0-1000 kilohertz (KHz), and 32768Hz is taken as an example here. The range of input frequency B is 4-64 megahertz (MHz), and 8MHz is taken as an example here. The clock sources included in the clock tree are: low speed external clock (LSE), low speed internal clock (LSI), high speed internal clock (HSI), and high speed external clock (HSE). Among them, LSI and HSI use RC oscillators. Figure 1In the example, the output of LSI is 100KHz and the output of HSI is 8KHz, while LSE and HSE use external input frequency A and / or input frequency B.

[0056] The signal output by HSE is recorded as HSE_RTC after being divided by 32. After the signals of HSE_RTC, LSE and LSI are input into the multiplexer MUX1, the clock signal (to RTC) input to the real-time clock (RTC) can be output, and here to RTC is 100KHz as an example. The signal output by LSI can also be directly used as the clock signal (to IWDG) of the watchdog (independent watchdog, IWDG), and here to IWDG is 100KHz as an example. The signal output by HSI can also be output to the flash programming interface (FLI), and here to FLI is 100KHz as an example. After HSE is divided by one and input to multiplexer MUX2 with HSI, it is output to PLL. After the output of PLL and to IWDG and to FLI are input to multiplexer MUX3, the clock signal of high performance bus clock (HCLK), the clock signal of processor Cortex (CorCLK), and free running clock (FCLK) can be obtained. The figure takes HCLK, CorCLK and FCLK as 48KHz as an example for explanation.

[0057] As can be seen from the above, in order to analyze the clock design of the current circuit system, developers can use the clock tree to analyze the flow direction, frequency, voltage, and phase noise of each clock signal in the circuit system. However, the clock tree needs to be drawn by the developer according to the circuit diagram, and when the clock requirements of the circuit system change, the developer also needs to modify the clock tree again. Therefore, developers spend a lot of time drawing the clock tree architecture diagram, which reduces the development efficiency of the circuit system.

[0058] In order to solve the problem that manually drawing a clock tree consumes a lot of time, the present application provides a clock tree generation method applied to an electronic device 100. The electronic device 100 first obtains network identifiers of multiple networks in a circuit system, and pin connection states of devices in multiple networks. For example, the electronic device 100 can obtain a netlist file of the circuit system, and the netlist file includes network identifiers of each network and pin connection relationships of each device.

[0059] The electronic device 100 can identify the clock network by identifying the network identifiers of multiple networks. Then, based on the identification information of the devices in the circuit system, the clock source devices, clock conversion devices, and clock demand devices connected to the clock network can be identified. In addition, based on the pin connection relationship of the devices in the netlist file, the flow direction of the clock signal in these clock source devices, clock conversion devices, and clock demand devices can be determined. Finally, a clock tree can be drawn based on the flow direction of the clock source devices, clock conversion devices, clock demand devices, and clock signals.

[0060] Optionally, the electronic device 100 may also obtain device identification configuration data, and then the electronic device 100 may determine the type of each device according to the device identification configuration data. The device identification configuration includes the corresponding relationship between the identification information of multiple devices and their types. For example, a device whose identification information contains the keyword "XTAL" is a crystal oscillator, and a device whose identification information contains the keyword "MUX" is a multiplexer.

[0061] Optionally, the electronic device 100 may also obtain network identification configuration data, and then the electronic device 100 may determine the type of each network according to the network identification configuration data. The network identification configuration data includes the corresponding relationship between the identification of multiple networks and their types. For example, a network whose network identification includes keywords such as "clk" and "XTAL" is a clock network.

[0062] In this way, through the clock tree generation method provided by the present application, the electronic device can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers do not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0063] The electronic device 100 can be a mobile phone, tablet computer, wearable device, vehicle-mounted device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA) or a special camera (such as SLR camera, card camera) and other terminal devices. The electronic device 100 can also be a physical server or cloud device, such as X86 server, ARM server, etc., or a virtual machine (VM) based on a general physical server combined with network function virtualization (NFV) technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment. This application does not impose any restrictions on the specific type of the electronic device 100.

[0064] The clock tree generation method provided by the present application is described in detail below. The clock tree generation method can be applied to the above electronic device 100, such as Figure 2 As shown, the clock tree generation method may include the following steps:

[0065] S210: Acquire network identifications of multiple networks in the circuit system, identification information of devices, and connection relationships.

[0066] The electronic device 100 may obtain the network identification of the circuit system, the identification information of the components and the connection relationship through the circuit diagram or netlist file uploaded by the user. The netlist file may be in the format of a telnet host file (TEL), a circuit description language (RPT) or a report file (RPT).

[0067] The network identification may include the network name, keyword, network code, etc. The device identification information may include the device code, bit number, name, specification, etc. The device connection relationship includes the connection relationship between the pins of each device and the identification of the input / output signal at each pin.

[0068] S220: Identify a clock network in the circuit system according to the network identifier.

[0069] The electronic device 100 can identify the clock network in the circuit system according to the network identifiers of the obtained multiple networks. For example, the clock network can be identified according to whether the name of the network in the circuit system contains a clock network keyword. For example, a network name including clock keywords such as "CLK" and "XTAL" is a clock network.

[0070] In some embodiments, the electronic device 100 may also identify the clock network based on preset network identification configuration data, which includes identification information of multiple clock networks and may also include correspondences between other network identifications and their network types. The network identification configuration data may be preset by the user in advance, or may be obtained by the electronic device 100 from a network identification database, which includes a large number of correspondences between network identifications and network types. This application does not impose specific restrictions on this.

[0071] In other embodiments, the electronic device 100 may also obtain network identification filtering data, and the network identification filtering data includes multiple network name keywords that need to be filtered. The electronic device 100 will also identify whether the network name contains the keywords in the network identification filtering data. If so, even if the network name contains the clock network keyword, the network will not be determined as a clock network. That is, only the network name contains the clock network keyword, and the network name does not contain the keyword in the network identification filtering data, will be determined as a clock network.

[0072] For example, the network identification filtering data may include keywords such as "VCC", "EN_IN", etc. When the network name includes "CLK" and "VCC", the electronic device 100 may determine that the network is not a clock network, and the network may be a power supply network determined to supply power to the clock network. When the network name includes "CLK" and "EN_IN", the electronic device 100 may also determine that the network is not a clock network, and the network may be determined to be a network of an enable signal input to the clock network.

[0073] S230: Determine the type and pin information of each device according to the identification information of the device.

[0074] The type of a device may specifically refer to the functional type and specification information of the device, for example, the functional type includes resistors, capacitors, multiplexers, crystal oscillators, frequency dividers, etc., and the specification information includes the resistance value of the resistor, the capacitance value of the capacitor, etc. The electronic device will determine the type of the device based on the device code, bit number, name, and keywords.

[0075] For example, if the device name includes "R", such as "R5287", the device can be considered as a resistor, and if the device name includes "XTAL", such as "XTAL10", the device can be considered as a crystal oscillator. Alternatively, the electronic device 100 can also determine the type of the device through the device sub-category code. For example, the device with the sub-category code "1201" is a clock oscillator, the device with the sub-category code "1202" is a crystal oscillator, the device with the sub-category code "1203" is an ordinary voltage-controlled crystal oscillator, the device with the sub-category code "1206" is a rubidium atomic clock, the device with the sub-category code "1208" is a constant temperature crystal oscillator, the device with the sub-category code "1271" is a vehicle-mounted clock oscillator, and the device with the sub-category code "1272" is a vehicle-mounted clock oscillator.

[0076] The electronic device 100 will also determine the pin information corresponding to the device according to the type of the identified device. The pin information may specifically include the pin number, pin name, pin type, pin direction, and pin matching relationship of the device, wherein the pin direction includes whether the signal of the pin is an output signal (out) or an input signal (in). For example, the pin direction of pin A1 of device A is OUT, and the pin direction of pin B1 of device B is IN.

[0077] In some embodiments, the electronic device 100 may also identify the device type according to preset device identification configuration data, and the device identification configuration data includes the corresponding relationship between the identification information of multiple devices and their types. Similarly, the device identification configuration data may be preset by the user in advance, or may be obtained by the electronic device 100 from a device identification database, and the device identification database includes a large number of corresponding relationships between device identifications and types.

[0078] In other embodiments, the device identification configuration data may also include whether the device belongs to a clock link device, and the clock link device includes type information of a clock source device, a clock conversion device, and a clock demand device. The electronic device 100 may further identify whether the device is a clock source device, a clock conversion device, and a clock demand device according to the type of the device and the device identification configuration data. For example, when the type of the device is identified as a crystal oscillator, a clock oscillator, a resonant tank circuit, an RC oscillator, a silicon oscillator, and an atomic clock, etc., it can be determined that the device is a clock source device. When the device is identified as a frequency synthesizer, a frequency divider, a PLL, a DDS, a clock driver, etc., it can be determined that the device is a clock conversion device. When the device is identified as a chip such as an FPGA, CPU, ASIC, DSP, etc., it can be considered that the device is a clock demand device.

[0079] In other embodiments, the device identification configuration data may also include type information of whether the device is a penetrable device. The electronic device 100 may also determine whether the device is a penetrable device based on the device identification configuration data. For example, devices with small DC impedance such as resistors, inductors, magnetic beads, copper foil, fuses, forward-connected diodes, etc. with small resistance values ​​may be identified as penetrable devices. Optionally, when a clock tree is subsequently generated, the penetrable device will not be drawn in the clock tree.

[0080] S240: Determine a clock link according to the connection relationship of the device, and determine the flow direction of the clock signal according to the pin information of the device.

[0081] The electronic device 100 determines the clock link according to the identified clock network and the connection relationship of each device. Among them, the clock link includes the connection relationship of each device in the clock network and the connection relationship of the devices connected to the clock network. The electronic device 100 then determines the flow direction of the clock signal in combination with the connection relationship and pin direction of the clock link devices. For example, the electronic device 100 first obtains the clock link according to the identified clock network. Then, according to the connection relationship of the clock link devices, such as the connection between the pin A1 of device A and the pin B1 of device B. Then obtain the type of the clock link device, such as obtaining that device A belongs to the clock source device, device B belongs to the clock conversion device, and the pin direction of the pin A1 of device A is OUT, and the pin direction of the pin B1 of device B is IN. Furthermore, the electronic device 100 can determine that the clock signal flows from the pin A1 of device A to the pin B1 of device B.

[0082] S250: Generate a clock tree according to the type of device and the flow direction of the clock signal.

[0083] After the electronic device 100 obtains the flow direction of the clock signal, it will also combine the type of device to determine the source end of the clock signal and the device through which the clock signal mainly flows, and then generate a clock tree. For example, the electronic device 100 can obtain the device type according to step S230, and can determine the clock link devices through which the clock signal mainly passes, such as the clock source device, the clock conversion device, and the clock demand device, and regard the penetrable device as a conductive path. Then, according to the clock link devices through which the clock signal mainly passes and the flow direction of the clock signal, a clock tree is generated.

[0084] In some embodiments, the electronic device 100 will also determine the parameter information of the clock signal in combination with the types of the clock source device and the clock conversion device. For example, the identification information of the crystal oscillator may include the specification information of the crystal oscillator. For example, when the specification of the crystal oscillator is 50MHz, it can be determined that the frequency of the clock signal at the pin where the crystal oscillator outputs the clock signal is 50MHz. The electronic device 100 will also mark the parameter information of the clock signal at each pin in the clock tree. Among them, the parameter information may specifically include the frequency, signal strength, phase, etc. of the clock signal.

[0085] In some embodiments, the electronic device 100 will also obtain the user interface (UI) graphics corresponding to each device in the clock tree, and draw the connection relationship of each device in the clock tree and mark the flow direction of the clock signal. The electronic device 100 will also display the drawn clock tree structure on the display interface. In other words, the clock tree displayed by the electronic device 100 can be text data such as a netlist file, or it can be graphic data. This application does not make specific restrictions on this.

[0086] In summary, through the clock tree generation method provided by the present application, the electronic device 100 can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0087] Next, combine Figure 3 A clock tree generation system provided in an embodiment of the present application is introduced, and the clock tree generation system can be run in an electronic device 100. Figure 3 As shown, the clock tree generation system includes an application layer, a business logic layer and a data layer. The application layer includes an interface display module 301, the business logic layer includes a netlist parsing module 302, a clock network analysis module 303, a clock link analysis module 304, a device symbol generation module 305, a clock source identification module 306, a clock tree generation module 307 and an application program interface (API) 308, and the data layer includes a database module 309. Among them,

[0088] The interface display module 301 can be used to display an interface for obtaining circuit system information and an interface for displaying a generated clock tree. The interface display module 301 is specifically a web page or a client. The user can upload information such as a circuit diagram or a netlist file of the circuit system through the interface for obtaining circuit system information displayed by the interface display module 301. The following is an example of the circuit system information being a netlist file. Then the interface display module 301 will send the netlist file to the business logic layer through the API 308. After the business logic layer generates a clock tree, the generated clock tree is obtained through the API 308 and the clock tree is displayed on the interface.

[0089] In some embodiments, the interface display module 301 can also be used to display interfaces such as clock link information and device pin information. Figure 8 , Figures 10 to 14 and its related description.

[0090] The netlist parsing module 302 is used to parse the netlist file obtained by the interface display module 301 to obtain the identification information of each network in the circuit system, the identification information of the device, and the connection relationship of the device. Optionally, the netlist file obtained by the netlist parsing module 302 can also come from the task database in the database module 309. The netlist parsing module 302 is also used to send the identification information of each network obtained by parsing to the clock network analysis module 303, and send the connection relationship of the device obtained by parsing to the clock link analysis module 304, and send the identification information of the device obtained by parsing to the device symbol generation module 305 and the clock source identification module 306.

[0091] The clock network analysis module 303 is used to identify the clock network in the circuit system according to the identification information of each network parsed by the netlist parsing module 302. Optionally, the clock network analysis module 303 can also send the identification information of the clock network to the clock link analysis module 304 and / or the device symbol generation module 305.

[0092] In some embodiments, the clock network analysis module 303 may identify the clock network according to preset network identification configuration data. The network identification configuration data may be preset in advance by a user or obtained from a network identification database in the database module 309 .

[0093] The clock link analysis module 304 is used to identify the clock link. The clock link analysis module 304 may first obtain the clock network identified by the clock network analysis module 303, and then identify the connection relationship between the devices in the clock network and the connection relationship between the devices connected to the clock network to obtain the clock link.

[0094] Alternatively, the clock link analysis module 304 may also obtain the connection relationship between the clock link device and the clock source device identified in the netlist file after the device symbol generation module 305 identifies the clock link device and the clock source identification module 306 identifies the clock source device, thereby obtaining the clock link.

[0095] The device symbol generation module 305 is used to identify the type of the device according to the identification information of the device parsed by the netlist parsing module 302. The device symbol generation module 305 can identify the type of each device in the circuit system, including the pin direction of the device, according to the identification information of the device parsed by the netlist parsing module 302. Then the device type is sent to the clock link analysis module 304, which then identifies the clock link and determines the flow direction of the clock signal according to the pin direction of the device in the clock link.

[0096] Alternatively, the device symbol generation module 305 may identify the type of each device in the clock link after the clock link analysis module 304 identifies the clock link, and the device symbol generation module 305 determines the flow direction of the clock signal according to the pin information of the device.

[0097] In some embodiments, the device symbol generation module 305 may identify the device type according to preset device identification configuration data. The device identification configuration data may be preset in advance by a user, or may be obtained from a device identification database in the database module 309 .

[0098] The clock source identification module 306 is used to identify the clock source device according to the identification information of the device. The clock source identification module 306 may first identify the clock source device in the circuit system and send the information of the clock source device to the clock link analysis module 304. It may also directly obtain the clock link identified by the clock link analysis module 304, and then identify the clock source device in the clock link. Optionally, the clock source identification module 306 and the device symbol generation module 305 may also be combined into the same module, that is, the device symbol generation module 305 directly determines the clock source device according to the type of the device.

[0099] In some embodiments, the clock source identification module 306 may identify the device type according to preset device identification configuration data. The device identification configuration data may be preset in advance by a user or obtained from a device identification database in the database module 309 .

[0100] The clock tree generation module 307 is used to obtain the clock signal flow direction identified by the clock link analysis module 304, the device type identified by the device symbol generation module 305, and the clock source device identified by the clock source identification module 306. The clock tree generation module 307 is also used to generate a clock tree according to the clock signal flow direction, the device type and the identified clock source device. The clock tree includes the flow direction of the clock signal and may also include parameter information of the clock signal.

[0101] Optionally, after the clock tree generation module 307 generates the clock tree, the clock tree can be sent to the interface display module 301 through the API 308, so that the interface display module 301 can also display the clock tree on the interface. Alternatively, the clock tree generation module 307 can also send the generated clock tree to other business modules, and other business modules use the clock tree to perform circuit system detection or simulation. For example, other business modules can also use the clock tree to perform signal integrity (SI) simulation, clock detection, phase noise detection, and level matching detection.

[0102] API 308 is used to obtain circuit system information such as the netlist file obtained by the interface display module 301, and send it to the netlist parsing module 302. It is also used to obtain the clock tree generated by the clock tree generation module 307, and send the clock tree to the interface display module 301 for display, or send the clock tree to other business modules for other business modules to perform circuit system detection or simulation.

[0103] The database module 309 includes a task database, a network identification database, and a device identification database. The netlist parsing module 302 can obtain information such as the netlist file of the circuit system from the task database. The clock network analysis module 303 can obtain network identification configuration data from the network identification database. The device symbol generation module 305 and the clock source identification module 306 can obtain device identification configuration data from the device identification database.

[0104] In summary, the clock tree generation system provided by this application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0105] The following is combined with the above Figure 3 The clock tree generation system shown in the figure introduces another clock tree generation method provided by the present application, in which the database module 309 includes a network identification database and a device identification database. And, Figure 4 The circuit system information is also described as a netlist file. Figure 4 As shown, the clock tree generation method of the database including the network identification database and the device identification database specifically includes:

[0106] S401: The interface display module 301 obtains a netlist file and a request to generate a clock tree.

[0107] The user can upload information such as a circuit diagram or a netlist file of the circuit system through the interface for obtaining circuit system information displayed by the interface display module 301. The type and content of the circuit system information can be referred to the aforementioned step S210, which will not be repeated here. The following description is made by taking the circuit system information as a netlist file as an example.

[0108] In addition, the interface display module 301 may also display related controls for generating a clock tree, and the user may select the control by clicking or other operations to trigger the clock tree generation system to execute subsequent steps to generate a clock tree.

[0109] For example, Figure 5 An interface 501 for obtaining circuit system information is shown. Control 502 in interface 501 can be used by the user to select whether to generate an SI use case. If the user chooses to generate an SI use case, the circuit system can be subjected to signal simulation analysis, including the generation of a clock tree, etc. Control 503 can be used by the user to upload a netlist file of the circuit system, such as a TEL file with a file suffix of .tel. Input box 504 can be used by the user to input relevant remarks information of the circuit system. Input box 505 can be used by the user to select a co-analyst for the circuit system.

[0110] For example, Figure 6 A partial circuit diagram of a circuit system is shown, which includes a crystal oscillator OSC1, a resistor R5287, and a clock driver U2. OSC1 includes a pin NC / 3-ST (serial number 1), NC / 3-ST indicates that the pin does not need to be connected (no connection, NC) and the OSC1 has a three-state output (three-state output, 3-ST), OSC1 also includes a ground pin GND (serial number 2), an output pin OUT (serial number 3) and a power pin VDD (serial number 4). U2 includes a clock signal input pin CLKIN (serial number 1), an enable (output enable) pin OE (serial number 2), a ground pin GND (serial number 4), a power pin VDD (serial number 6), and output pins 1Y0 to 1Y3 (serial number 3, serial number 5, serial number 7, and serial number 8). In addition, the output pin OUT of OSC1 is connected to one end of R5287, and the signal output from the other end of R5287 is recorded as RMII_CLK_50M_IN and input to the clock signal input pin CLKIN of U2.

[0111] Figure 7 for Figure 6 The netlist file corresponding to the circuit diagram shown in the figure includes a declaration package ($PACKAGES), a property package ($A_PROPERTIES), a connection information package ($NETS), and a schedule ($SCHEDULE). $PACKAGES defines the names and specifications of each device in the circuit system, including the frequency of the OSC1 output signal is 50MHz, the resistance of R5287 is 33Ω, etc. $A_PROPERTIES defines the bit number of each device, such as Figure 7 As shown in the figure, the bit number of R5287 is "07XXX36", the bit number of OSC1 is "12XXX00", and the bit number of U2 is "39XXX95". The connection relationship between the devices is defined in $NETS. For example, "'$1N524'; OSC1.3 R5287.1" means that the pin 3 of OSC1 is connected to one end of R5287, and the signal is recorded as "$1N524". "'RMII_CLK_50MHZ_IN'; R5287.2 U2.1" means that the other end of R5287 is connected to the pin 1 of U2, and the signal is recorded as "RMII_CLK_50MHZ_IN".

[0112] S402: The interface display module 301 sends the netlist file to the netlist parsing module 302.

[0113] After the interface display module 301 obtains the netlist file, it will also send the netlist file to the netlist parsing module 302 through the API 308, and the netlist parsing module 302 will parse the netlist file.

[0114] S403: The netlist parsing module 302 parses the netlist file to obtain the network identification and device connection relationship of each network.

[0115] After the netlist parsing module 302 obtains the netlist file, it will parse and obtain the network identification of each network in the circuit system, as well as the identification information and connection relationship of each device in each network. Figure 6 and Figure 7 Related description.

[0116] S404: The netlist parsing module 302 sends the network identification of each network to the clock network analysis module 303.

[0117] The netlist parsing module 302 sends the network identifiers of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze and obtain the clock network in the circuit system.

[0118] S405a: The clock network analysis module 303 sends a request to the database module 309 to obtain network identification configuration data.

[0119] The request for obtaining network identification configuration data is used to request the database module 309 to send the network identification configuration data to the clock network analysis module 303. The network identification configuration data includes identification information of multiple clock networks, and may also include the correspondence between other network identifications and their network types. Optionally, the network identification configuration data may also include network identification filtering data. The network identification configuration data in the database module 309 may be obtained by summarizing the network identifications of a large number of circuit systems.

[0120] S405b: The database module 309 sends the network identification configuration data to the clock network analysis module 303.

[0121] After acquiring the network identification configuration data, the clock network analysis module 303 may also display the network identification configuration data on the interface. Figure 8 As shown, a display box 802 of network identification configuration data is displayed on interface 801. Control 803 of display box 802 can be used for users to add keywords of network identifications that need to be identified and network identifications that need to be filtered. Display box 804 displays some clock keywords ("CLK", "XTAL") and corresponding keywords that need to be filtered ("VCC", "EN_IN" and "OUT"). Controls 805a to 805c can be used to delete corresponding keywords. Control 806 can restore the network identification configuration data to the system default state, for example, without saving the user's operation, and restore it to the original state. Control 807 can be used for the user to save the current modification. Control 808 can be used for the user to cancel the current operation and / or close display box 804.

[0122] S406: The clock network analysis module 303 identifies the clock network according to the network identifiers of each network.

[0123] The clock network analysis module 303 will identify the network identifier of the clock network according to the network identifier configuration data. For example, a network name including clock keywords such as "CLK" and "XTAL" is a clock network. For details, please refer to the aforementioned step S220, which will not be repeated here.

[0124] Optionally, the clock network analysis module 303 will also obtain whether the clock network is complete. Specifically, the clock network may be sent to the interface display module 301, and after the interface display module 301 displays the clock network, the user will judge whether the clock network is complete based on the displayed clock network, and obtain the user's judgment result.

[0125] S407: The clock network analysis module 303 sends the network identifier of the clock network to the clock link analysis module 304.

[0126] The clock network analysis module 303 sends the network identifier of the identified clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0127] S408: The netlist parsing module 302 sends the device connection relationship to the clock link analysis module 304.

[0128] The netlist parsing module 302 may send the device connection relationship to the clock link analysis module 304 after parsing the device connection relationship, that is, step S408 is executed first after step S403, or step S408 may be executed at any time after step S403.

[0129] S409: The clock link analysis module 304 determines the device through which the clock signal flows.

[0130] The clock link analysis module 304 can determine the connection relationship between the components in the clock network and the components connected to the clock network and their connection relationship based on the clock network and the connection relationship between the components, and further determine the clock components through which the clock signal flows.

[0131] S410: The clock link analysis module 304 sends identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0132] The clock link analysis module 304 can send the identification information of the devices through which the clock signal passes to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and then obtain the flow direction of the clock signal in the clock link.

[0133] S411a: The device symbol generation module 305 sends a request to the database module 309 to obtain device identification configuration data.

[0134] The device symbol generation module 305 obtains the device identification configuration data in the database module 309 to identify the type and pin direction of each device. The device identification configuration data includes the corresponding relationship between the identification information of multiple devices and their types, and also includes the pin information of each device. The device identification configuration data may also include type information of whether the device belongs to a clock source device, a clock conversion device, a clock demand device, etc., and type information of whether the device belongs to a penetrable device. For details, please refer to the aforementioned step S230, which will not be repeated here.

[0135] S411b: The database module 309 sends the device identification configuration data to the device symbol generation module 305.

[0136] S412: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0137] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. And obtain the pin information corresponding to each clock device, and determine the flow direction of the clock signal between the clock devices according to the pin information, that is, determine the direction of the clock link.

[0138] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can be Fig. 9 The process shown in the figure determines the clock device. Fig. 9 As shown, including:

[0139] S901: Acquire a clock network.

[0140] Specifically, the clock link analysis module 304 acquires the clock network according to the network identifier of the clock network identified by the clock network analysis module 303 .

[0141] S902: Determine whether the type of device connected to the network is a small device.

[0142] The device symbol generation module 305 determines whether the device connected to the clock network is a small device, and if so, executes step S904 ; otherwise, executes step S903 .

[0143] Specifically, the clock link analysis module 304 can determine the clock device through which the clock signal flows according to the clock network and the device connection relationship. The device symbol generation module 305 will determine whether the device connected to the clock network is a small device. Among them, a small device refers to a single device other than an integrated chip, such as a resistor, a capacitor, a magnetic bead, etc.

[0144] S903: Draw a cutoff device.

[0145] If the device connected to the clock network is not a small device, it means that the device is a clock demand device, and the device symbol generation module 305 needs to draw it in the clock tree. Then the device symbol generation module 305 draws the device as a clock cutoff device.

[0146] S904: Determine whether the small device penetrates.

[0147] If the device connected to the clock network is a small device, the device symbol generation module 305 will further determine whether the small device can be penetrated. If so, step S906 is executed, if not, step S905 is executed. The small device is a device with a small impedance in a DC circuit, such as a resistor, inductor, magnetic bead, copper foil, fuse, or forward-connected diode with a small resistance value.

[0148] Specifically, the device symbol generation module 305 can also obtain the pin information of the small device from the device identification configuration data, and judge whether it is penetrable by the polarity of the pin in the pin information. For example, if the pin type is collector (C), its pin polarity is positive, if the pin type is drain (D), its pin polarity is negative, and if the pin type is L, its pin polarity is nonpolar.

[0149] S905: Draw a cutoff device.

[0150] If the small device connected to the clock network is not a penetrable device, it means that it can also consume the clock signal and needs to be drawn in the clock tree, then the device symbol generation module 305 will also draw the device as a cut-off device.

[0151] S906: Determine whether the network at the other end of the small device is a power supply / ground.

[0152] If the small device is a penetrable device, it is further determined whether the small device is a power supply / ground, and if so, step S907 is executed. If not, the process ends, or the method steps are executed again to determine the next clock network.

[0153] S907: Draw power / ground symbols.

[0154] If the small device is a power supply / ground, the device symbol generation module 305 draws it as a power supply / ground.

[0155] After determining the type of the device, the device symbol generation module 305 will also obtain the pin information corresponding to the clock device. Fig.10As shown, interface 1001 shows the pin information of device "39130129". Among them, display box 1002 shows the name of the device "39130129", and display box 1003 shows the description of the device, including that the device belongs to a clock driver, its output frequency is 100MHz-133.33MHz, and the operating voltage can be 3.3V-3.3V-4.6V, etc. Display box 1004 shows the serial number, name, type and direction of each pin of the device. Specifically, it includes the clock signal input pin CLKIN (pin number 1), whose pin direction is IN, that is, the input end. Enable (output enable) pin OE (pin number 2), whose pin direction is IN, that is, the input end. Ground pin GND (pin number 4), whose pin direction is BI, that is, the low level end. Power pin VDD (pin number 6), whose pin direction is IN, that is, the input end. And the output pins 1Y0 to 1Y3 (pin number 3, pin number 5, pin number 7 and pin number 8), the pin directions of which are all OUT.

[0156] After the device symbol generation module 305 obtains the pin direction of the clock device, it can determine the signal source segment and signal destination end of the clock signal. Fig.11 As shown, the device symbol generation module 305 sends the determined signal source segment and signal destination to the interface display module 301, and the interface display module 301 displays the clock network information of the task "Board1" on the interface 1101. The display box 1102 in the interface 1101 can operate the source end information of multiple clock networks, wherein the display box 1107 displays the signal source end and signal destination end of multiple clock networks, for example, the signal source end of the clock network with the network name "CLK1" is "U43<93DGLF>-OUT", and the signal destination end is "U42 <lewis>-BIU29<9ZLF>-IN". In addition, the display box 1102 also includes controls 1103 to 1106. Control 1103 can be used by the user to manually add a clock network, control 1104 can be used by the user to batch manage the identified clock networks, and control 1105 can be used by the user to batch delete the identified clock networks. Control 1106 can be used to generate a clock tree. After the user clicks control 1106, the clock tree generation system can be triggered to generate a clock tree according to the currently identified clock network.

[0157] Furthermore, the device symbol generation module 305 can also draw a schematic diagram according to the signal source segment and the signal destination end of the clock signal, and send it to the interface display module 301. Fig.12 As shown in the schematic diagram, Fig.11 The schematic diagram of the clock network information includes CLK_PCIE7_P input to CLKOUT_SRC_P_7 of U4214, CLK_100M_DB1900R_1_P input to DF_IN of U29, and CLK_100M_DB1900_1_P output as CLK_100M_DB1900_1R_P after passing through R10349.

[0158] Optionally, the user can also set the signal source and signal destination by himself. Fig.13 The interface 1301 shown is used to set a clock signal through a display box 1302. For example, by clicking on a control 1303, the signal can be set as a signal source, by clicking on a control 1304, the signal can be set as a signal destination, or by clicking on a control 1305, the signal can be set not to be displayed in the form. In addition, the user can confirm the above modification by clicking on a control 1306, or exit the setting and close the display box 1302 by clicking on a control 1307.

[0159] S413: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0160] The device symbol generation module 305 may send the type of the clock device to the clock tree generation module 307 , and may also send the signal source segment and the signal destination end of the clock signal to the clock tree generation module 307 .

[0161] S414: The netlist parsing module 302 sends the identification and connection relationship of the devices in each network to the clock source identification module 306.

[0162] The netlist parsing module 302 sends the identifiers and connection relationships of the devices in each network to the clock source identification module 306, so that the clock source identification module 306 can identify the clock source device in each device. It should be understood that this step can also be performed by the device symbol generation module 305 in step S412, and this application does not limit this.

[0163] S415: The clock source identification module 306 determines the clock source device.

[0164] The clock source identification module 306 may identify the clock source device according to the identification information of each device according to the preset device identification configuration data. For details, please refer to the aforementioned step S230 and its related description.

[0165] S416: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0166] After identifying the clock source device, the clock source identification module 306 sends the identification information of the clock source device to the clock tree generation module 307 .

[0167] S417: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0168] The clock tree generation module 307 can determine the clock tree according to the flow of the clock signal and the type of the device.

[0169] Optionally, the clock tree generation module 307 will also determine the parameter information of the clock signal in combination with the types of the clock source device and the clock conversion device. The parameter information may specifically include the frequency, signal strength, phase, etc. of the clock signal. For details, please refer to the aforementioned step S250 and its related description.

[0170] S418: The clock tree generating module 307 sends the clock tree to the interface display module 301.

[0171] The clock tree generation module 307 sends the clock tree, which may be text data such as a netlist file, or graphic data of the clock tree to the interface display module 301 .

[0172] S419: The interface display module 301 displays the clock tree.

[0173] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307 .

[0174] For example, Fig.14 As shown, a schematic diagram of the structure of a clock tree is displayed in the display column 1402 of the interface 1401. Among them, the crystal oscillator X10 is a clock source device, which is numbered "1212", and the pin 2 of X10 inputs the signal "$3165 / XTAL..." to the K17 pin (pin name is "RTCX1") of the document encoder U42.

[0175] The pin K2 (pin name is "SPIO_CLK") of U42 inputs the signal "SPI_PCH_CLK" to the pin 1 (pin name is "A1") of the common socket J1 and the pin 3 (pin name is "A1") of the logic bus (LOGIC BUS) U3 respectively. Pin AP18 of U42 (pin name "GPP_F22...") inputs the signal "SGPIO_SA_CLK_R" to pin R8 of complex programmable logic device (CPLD) U4 (pin name "PB12D"), pin T2 of U42 (pin name "GPP_A16...") inputs the signal "CLK_CPLD_DET.." to pin F14 of U4 (pin name "PR2C"), and pin C13 of U42 (pin name "GPD8_SUS..") inputs the signal "CLK_PCH_SUSCLK_33.." to pin B9 of port physical layer (Physical, PHY) U4 (pin name "PT18B / PC"). Pin BW6 of U42 (pin name is "GPP_J14..") inputs the signal "LAN_SCL" to pin 7 of U4 (pin name is "MDC").

[0176] Pin 27 of U3 (pin name is "B9") inputs the signal "SPI_CLK" to pin 16 (pin name is "SLCK") of the non-volatile flash memory (NOR Flash) U7. Pin T7 of U4 (pin name is "PB10C") inputs the signal "SGPIO_RAID_CLK_X6..." to pin 22 (pin name is "A6") of the high-speed backplane connector J2. Pin T7 of U4 (pin name is "PB10C") inputs the signal "SGPIO_RAID_CLK_X6..." to pin 50 (pin name is "TX2N") of the transceiver equalizer U42.

[0177] In summary, the clock tree generation system provided by this application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0178] The following is combined with the above Figure 3 The clock tree generation system shown in the figure introduces another clock tree generation system provided by the present application. Fig.15 The clock tree generation method shown in the figure, in which the database module 309 includes a device identification database. And, Fig.15 The circuit system information is also described by taking the netlist file as an example. Fig.15 The specific implementation of similar steps in the process shown can refer to the aforementioned Figure 2 or Figure 4 And its related contents are not mentioned here. Fig.15 As shown, the clock tree generation method of the database including the device identification database specifically includes:

[0179] S1501: The interface display module 301 obtains the netlist file and a request to generate a clock tree.

[0180] The user can upload information such as a circuit diagram or a netlist file of the circuit system through the interface for obtaining circuit system information displayed by the interface display module 301 .

[0181] S1502: The interface display module 301 sends the netlist file to the netlist parsing module 302.

[0182] After the interface display module 301 obtains the netlist file, it will also send the netlist file to the netlist parsing module 302 through the API 308, and the netlist parsing module 302 will parse the netlist file.

[0183] S1503: The netlist parsing module 302 parses the netlist file to obtain the network identification and device connection relationship of each network.

[0184] After acquiring the netlist file, the netlist parsing module 302 will parse and obtain the network identification of each network in the circuit system, as well as the identification information and connection relationship of each device in each network.

[0185] S1504: The netlist parsing module 302 sends the network identification of each network to the clock network analysis module 303.

[0186] The netlist parsing module 302 sends the network identifiers of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze and obtain the clock network in the circuit system.

[0187] S1505: The clock network analysis module 303 identifies the clock network according to the network identifiers of each network.

[0188] The clock network analysis module 303 will identify the network identification of the clock network according to the network identification configuration data. For example, a network name including clock keywords such as "CLK" and "XTAL" is a clock network. The network identification configuration data can be determined based on a user-preset file, can be pre-loaded during operation, or can be input through other ports.

[0189] S1506: The clock network analysis module 303 sends the network identifier of the clock network to the clock link analysis module 304.

[0190] The clock network analysis module 303 sends the network identifier of the identified clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0191] S1507: The netlist parsing module 302 sends the device connection relationship to the clock link analysis module 304.

[0192] The netlist parsing module 302 may send the device connection relationship to the clock link analysis module 304 after parsing the device connection relationship, that is, step S1507 is executed first after step S1503, or step S1507 may be executed at any time after step S1503.

[0193] S1508: The clock link analysis module 304 determines the device through which the clock signal flows.

[0194] The clock link analysis module 304 can determine the connection relationship between the various devices in the clock network and the connection relationship between the devices connected to the clock network according to the clock network and the device connection relationship, and further determine the clock device through which the clock signal flows.

[0195] S1509: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0196] The clock link analysis module 304 can send the identification information of the devices through which the clock signal passes to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and then obtain the flow direction of the clock signal in the clock link.

[0197] S1510a: The device symbol generation module 305 sends a request to the database module 309 to obtain device identification configuration data.

[0198] The device identification configuration data includes the corresponding relationship between the identification information of multiple devices and their types, and also includes the pin information of each device. The device identification configuration data may also include type information such as whether the device is a clock source device, a clock conversion device, and a clock demand device, and whether the device is a penetrable device.

[0199] S1510b: The database module 309 sends the device identification configuration data to the device symbol generation module 305.

[0200] S1511: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0201] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. And obtain the pin information corresponding to each clock device, and determine the flow direction of the clock signal between the clock devices according to the pin information, that is, determine the direction of the clock link.

[0202] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can be Fig. 9 The process shown in the figure determines the clock device. For details, please refer to the above Fig. 9 The related descriptions will not be repeated here.

[0203] After determining the type of the device, the device symbol generation module 305 will also obtain the pin information corresponding to the clock device. After the device symbol generation module 305 obtains the pin direction of the clock device, it can determine the signal source segment and signal destination of the clock signal. Further, the device symbol generation module 305 can also draw a schematic diagram based on the signal source segment and signal destination of the clock signal, and send it to the surface display module 301. Optionally, the user can also set the signal source and signal destination by himself.

[0204] S1512: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0205] The device symbol generation module 305 may send the type of the clock device to the clock tree generation module 307 , and may also send the signal source segment and the signal destination end of the clock signal to the clock tree generation module 307 .

[0206] S1513: The netlist parsing module 302 sends the identification and connection relationship of the devices in each network to the clock source identification module 306.

[0207] The netlist parsing module 302 sends the identifiers and connection relationships of the devices in each network to the clock source identification module 306 , so that the clock source identification module 306 can identify the clock source device in each device.

[0208] S1514: The clock source identification module 306 determines the clock source device.

[0209] The clock source identification module 306 may identify the clock source device according to the identification information of each device based on the preset device identification configuration data.

[0210] S1515: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0211] S1516: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0212] The clock tree generation module 307 can determine the clock tree according to the flow of the clock signal and the type of the device.

[0213] S1517: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0214] The clock tree generation module 307 sends the clock tree, which may be text data such as a netlist file, or graphic data of the clock tree to the interface display module 301 .

[0215] S1518: The interface display module 301 displays the clock tree.

[0216] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307 .

[0217] In summary, the clock tree generation system provided by this application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0218] The following is combined with the above Figure 3 The clock tree generation system shown in the figure introduces the clock tree generation system provided by the present application. Fig.16 Another clock tree generation method shown, in which the database module 309 includes a network identification database. And, Fig.16 The circuit system information is also described by taking the netlist file as an example. Fig.16 The specific implementation of similar steps in the process shown can refer to the aforementioned Figure 2 or Figure 4 And its related contents are not mentioned here. Fig.16 As shown, the clock tree generation method of the database including the network identification database specifically includes:

[0219] S1601: The interface display module 301 obtains the netlist file and a request to generate a clock tree.

[0220] The user can upload information such as a circuit diagram or a netlist file of the circuit system through the interface for obtaining circuit system information displayed by the interface display module 301 .

[0221] S1602: The interface display module 301 sends the netlist file to the netlist parsing module 302.

[0222] After the interface display module 301 obtains the netlist file, it will also send the netlist file to the netlist parsing module 302 through the API 308, and the netlist parsing module 302 will parse the netlist file.

[0223] S1603: The netlist parsing module 302 parses the netlist file to obtain the network identification and device connection relationship of each network.

[0224] After acquiring the netlist file, the netlist parsing module 302 will parse and obtain the network identification of each network in the circuit system, as well as the identification information and connection relationship of each device in each network.

[0225] S1604: The netlist parsing module 302 sends the network identification of each network to the clock network analysis module 303.

[0226] The netlist parsing module 302 sends the network identifiers of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze and obtain the clock network in the circuit system.

[0227] S1605a: The clock network analysis module 303 sends a request to the database module 309 to obtain network identification configuration data.

[0228] The network identification configuration data includes identification information of multiple clock networks, and may also include correspondences between other network identifications and their network types. Optionally, the network identification configuration data may also include network identification filtering data. The network identification configuration data in the database module 309 may be obtained by summarizing network identifications of a large number of circuit systems.

[0229] S1605b: The database module 309 sends the network identification configuration data to the clock network analysis module 303.

[0230] After acquiring the network identification configuration data, the clock network analysis module 303 may also display the network identification configuration data on the interface.

[0231] S1606: The clock network analysis module 303 identifies the clock network according to the network identifiers of each network.

[0232] The clock network analysis module 303 will identify the network identifier of the clock network according to the network identifier configuration data. For example, a network name including clock keywords such as "CLK" and "XTAL" is a clock network.

[0233] S1607: The clock network analysis module 303 sends the network identifier of the clock network to the clock link analysis module 304.

[0234] The clock network analysis module 303 sends the network identifier of the identified clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0235] S1608: The netlist parsing module 302 sends the device connection relationship to the clock link analysis module 304.

[0236] The netlist parsing module 302 may send the device connection relationship to the clock link analysis module 304 after parsing the device connection relationship, that is, step S1608 is executed first after step S1603, or step S1608 may be executed at any time after step S1603.

[0237] S1609: The clock link analysis module 304 determines the device through which the clock signal flows.

[0238] The clock link analysis module 304 can determine the connection relationship between the various devices in the clock network and the connection relationship between the devices connected to the clock network according to the clock network and the device connection relationship, and further determine the clock device through which the clock signal flows.

[0239] S1610: The clock link analysis module 304 sends identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0240] The clock link analysis module 304 can send the identification information of the devices through which the clock signal passes to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and then obtain the flow direction of the clock signal in the clock link.

[0241] S1611: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0242] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. And obtain the pin information corresponding to each clock device, and determine the flow direction of the clock signal between the clock devices according to the pin information, that is, determine the direction of the clock link. Among them, the device identification configuration data can be determined based on a user-preset file, can be pre-loaded during operation, or can be input through other ports.

[0243] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can be Fig. 9 The process shown in the figure determines the clock device. For details, please refer to the above Fig. 9 The related descriptions will not be repeated here.

[0244] After determining the type of the device, the device symbol generation module 305 will also obtain the pin information corresponding to the clock device. After the device symbol generation module 305 obtains the pin direction of the clock device, it can determine the signal source segment and signal destination of the clock signal. Furthermore, the device symbol generation module 305 can also draw a schematic diagram based on the signal source segment and signal destination of the clock signal, and send it to the interface display module 301. Optionally, the user can also set the signal source and signal destination by himself.

[0245] S1612: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0246] The device symbol generation module 305 may send the type of the clock device to the clock tree generation module 307 , and may also send the signal source segment and the signal destination end of the clock signal to the clock tree generation module 307 .

[0247] S1613: The netlist parsing module 302 sends the identification and connection relationship of the devices in each network to the clock source identification module 306.

[0248] The netlist parsing module 302 sends the identifiers and connection relationships of the devices in each network to the clock source identification module 306 , so that the clock source identification module 306 can identify the clock source device in each device.

[0249] S1614: The clock source identification module 306 determines the clock source device.

[0250] The clock source identification module 306 may identify the clock source device according to the identification information of each device based on the preset device identification configuration data.

[0251] S1615: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0252] S1616: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0253] The clock tree generation module 307 can determine the clock tree according to the flow of the clock signal and the type of the device.

[0254] S1617: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0255] The clock tree generation module 307 sends the clock tree, which may be text data such as a netlist file, or graphic data of the clock tree to the interface display module 301 .

[0256] S1618: The interface display module 301 displays the clock tree.

[0257] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307 .

[0258] In summary, the clock tree generation system provided by this application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0259] The following is combined with the above Figure 3 The clock tree generation system shown in the figure introduces the clock tree generation system provided by the present application. Fig.17 Another clock tree generation method shown in FIG. 1 does not include the database module 309. In addition, Fig.17 The circuit system information is also described by taking the netlist file as an example. Fig.17 The specific implementation of similar steps in the process shown can refer to the aforementioned Figure 2 or Figure 4 And its related contents are not mentioned here. Fig.17 As shown, the clock tree generation method without a database specifically includes:

[0260] S1701: The interface display module 301 obtains the netlist file and a request to generate a clock tree.

[0261] The user can upload information such as a circuit diagram or a netlist file of the circuit system through the interface for obtaining circuit system information displayed by the interface display module 301 .

[0262] S1702: The interface display module 301 sends the netlist file to the netlist parsing module 302.

[0263] After the interface display module 301 obtains the netlist file, it will also send the netlist file to the netlist parsing module 302 through the API 308, and the netlist parsing module 302 will parse the netlist file.

[0264] S1703: The netlist parsing module 302 parses the netlist file to obtain the network identification and device connection relationship of each network.

[0265] After acquiring the netlist file, the netlist parsing module 302 will parse and obtain the network identification of each network in the circuit system, as well as the identification information and connection relationship of each device in each network.

[0266] S1704: The netlist parsing module 302 sends the network identification of each network to the clock network analysis module 303.

[0267] The netlist parsing module 302 sends the network identifiers of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze and obtain the clock network in the circuit system.

[0268] S1705: The clock network analysis module 303 identifies the clock network according to the network identifiers of each network.

[0269] The clock network analysis module 303 will identify the network identification of the clock network according to the network identification configuration data. For example, a network name including clock keywords such as "CLK" and "XTAL" is a clock network. The network identification configuration data can be determined based on a user-preset file, can be pre-loaded during operation, or can be input through other ports.

[0270] S1706: The clock network analysis module 303 sends the network identifier of the clock network to the clock link analysis module 304.

[0271] The clock network analysis module 303 sends the network identifier of the identified clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0272] S1707: The netlist parsing module 302 sends the device connection relationship to the clock link analysis module 304.

[0273] The netlist parsing module 302 may send the device connection relationship to the clock link analysis module 304 after parsing the device connection relationship, that is, step S1707 is executed first after executing step S1703, or step S1707 may be executed at any time after step S1703.

[0274] S1708: The clock link analysis module 304 determines the device through which the clock signal flows.

[0275] The clock link analysis module 304 can determine the connection relationship between the various devices in the clock network and the connection relationship between the devices connected to the clock network according to the clock network and the device connection relationship, and further determine the clock device through which the clock signal flows.

[0276] S1709: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0277] The clock link analysis module 304 can send the identification information of the devices through which the clock signal passes to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and then obtain the flow direction of the clock signal in the clock link.

[0278] S1710: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0279] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. And obtain the pin information corresponding to each clock device, and determine the flow direction of the clock signal between the clock devices according to the pin information, that is, determine the direction of the clock link. Among them, the device identification configuration data can be determined based on a user-preset file, can be pre-loaded during operation, or can be input through other ports.

[0280] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can be Fig. 9 The process shown in the figure determines the clock device. For details, please refer to the above Fig. 9 The related descriptions will not be repeated here.

[0281] After determining the type of the device, the device symbol generation module 305 will also obtain the pin information corresponding to the clock device. After the device symbol generation module 305 obtains the pin direction of the clock device, it can determine the signal source segment and signal destination of the clock signal. Furthermore, the device symbol generation module 305 can also draw a schematic diagram based on the signal source segment and signal destination of the clock signal, and send it to the interface display module 301. Optionally, the user can also set the signal source and signal destination by himself.

[0282] S1711: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0283] The device symbol generation module 305 may send the type of the clock device to the clock tree generation module 307 , and may also send the signal source segment and the signal destination end of the clock signal to the clock tree generation module 307 .

[0284] S1712: The netlist parsing module 302 sends the identification and connection relationship of the devices in each network to the clock source identification module 306.

[0285] The netlist parsing module 302 sends the identifiers and connection relationships of the devices in each network to the clock source identification module 306 , so that the clock source identification module 306 can identify the clock source device among the devices.

[0286] S1713: The clock source identification module 306 determines the clock source device.

[0287] The clock source identification module 306 may identify the clock source device according to the identification information of each device based on the preset device identification configuration data.

[0288] S1714: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0289] S1715: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0290] The clock tree generation module 307 can determine the clock tree according to the flow of the clock signal and the type of the device.

[0291] S1716: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0292] The clock tree generation module 307 sends the clock tree, which may be text data such as a netlist file, or graphic data of the clock tree to the interface display module 301 .

[0293] S1717: The interface display module 301 displays the clock tree.

[0294] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307 .

[0295] In summary, the clock tree generation system provided by this application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And there is no need for developers to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0296] In order to solve the problem that manually drawing a clock tree consumes a lot of time, the present application provides a clock tree generation device 1800, which can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Fig.18 As shown, the clock tree generating device 1800 may include an acquiring unit 1810 , a determining unit 1820 , and a generating unit 1830 .

[0297] The acquisition unit 1810 is used to acquire the network identification of at least one network in the circuit system, the identification information of the devices in at least one network, and the connection status between the devices. The determination unit 1820 is used to determine a clock network in at least one network according to the network identification of at least one network, and the clock network is used to output at least one clock signal. The determination unit 1830 is also used to acquire the identification information of at least one device in the clock network and the connection relationship between at least one device and other devices in the circuit system. The determination unit 1820 is also used to determine the type of at least one device according to the identification information of at least one device; and, according to the connection relationship of at least one device, determine the flow direction of at least one clock signal in the circuit system. The generation unit 1830 is used to generate a clock tree corresponding to the clock network according to the type of at least one device and the flow direction of at least one clock signal.

[0298] In some embodiments, the determination unit 1820 is further configured to determine a clock source device in at least one device of the clock network according to identification information of at least one device, where the clock source device is configured to generate a clock signal.

[0299] In some other embodiments, the acquisition unit 1810 is further configured to acquire identification information of a device connected to the clock network based on identification information of a device in at least one network in the circuit system and a connection status between the devices. The determination unit 1820 is further configured to determine a clock demanding device based on identification information of the device connected to the clock network, where the clock demanding device is a device that consumes a clock signal.

[0300] In some other embodiments, the determination unit 1820 is further configured to determine a clock conversion device in at least one device of the clock network according to identification information of at least one device, where the clock conversion device is configured to change a parameter value of a clock signal.

[0301] In other embodiments, the generation unit 1830 is also used to generate a clock tree corresponding to the circuit system based on the clock source device, the clock conversion device, the clock demand device and the flow direction of at least one clock signal, and the clock tree includes a parameter value of at least one clock signal at the pins of the clock source device, the clock conversion device and the clock demand device.

[0302] In other embodiments, the acquisition unit 1810 is further used to acquire device identification configuration data, which includes the correspondence between identification information and type of at least one device; the determination unit 1820 is further used to determine the type of at least one device based on the device identification configuration data and the identification information of at least one device.

[0303] In other embodiments, the device identification configuration data comes from a device identification database connected to the electronic device.

[0304] In other embodiments, the acquisition unit 1810 is also used to acquire network identification configuration data, the network identification configuration data including a correspondence between at least one network identification and a network type; the determination unit 1820 is also used to determine a clock network in at least one network based on the network identification configuration data and the network identification of at least one network.

[0305] In other embodiments, the network identification configuration data comes from a network identification database connected to the electronic device.

[0306] In other embodiments, the determination unit 1820 is also used to determine a netlist file corresponding to the circuit system; the acquisition unit 1810 is also used to parse the netlist file, obtain the network identification of at least one network in the circuit system and the identification information of the devices in at least one network and the connection status between the devices.

[0307] In other embodiments, the identification information of at least one device includes one or more of a code, a bit number, and a keyword of the at least one device.

[0308] In other embodiments, the circuit system also includes one or more of a power supply network and a bus network; the clock source device includes one or more of a crystal oscillator, a clock oscillator, a resonant tank circuit, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; the clock conversion device includes one or more of a frequency synthesizer, a divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; and the parameter value of the clock signal includes one or more of frequency, signal strength, and phase.

[0309] In summary, the clock tree generation device 1800 provided by the present application can identify the types of various devices and the flow of clock signals according to the netlist file, and then automatically draw the clock tree. Developers can view or adjust the clock architecture of the circuit system according to the clock tree. And developers do not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0310] The method of the embodiment of the present application is described in detail above. In order to facilitate better implementation of the above scheme of the embodiment of the present application, correspondingly, related equipment for cooperating in implementing the above scheme is also provided below.

[0311] Fig.19 1 is a schematic diagram of a computing device 1900 provided in the present application. The computing device 1900 may be the clock tree generating device 1800 in the aforementioned content. Fig.19 As shown, the computing device 1900 includes: a processor 1910, a communication interface 1920 and a memory 1930. Among them, the processor 1910, the communication interface 1920 and the memory 1930 can be connected to each other through an internal bus 1940, or can communicate through other means such as wireless transmission. The embodiment of the present application takes the connection through bus 1940 as an example. Bus 1940 can be a peripheral component interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. Bus 1940 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, bus 1940 can also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as bus 1940 in the figure.

[0312] The processor 1910 may be composed of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 1910 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 1930, which enables the computing device 1900 to provide a variety of services.

[0313] The memory 1930 is used to store program codes, and is controlled by the processor 1910 to execute the processing steps of the clock tree generation method in the above embodiment. The program code may include one or more software modules, which may be Fig.18 The software modules provided in the embodiments, such as an acquisition unit, a generation unit, and a determination unit: the acquisition unit is used to acquire the network identification of at least one network in the circuit system and the identification information of the devices in at least one network and the connection status between the devices. The determination unit is used to determine a clock network in at least one network according to the network identification of at least one network, and the clock network is used to output at least one clock signal. The acquisition unit is also used to acquire the identification information of at least one device in the clock network and the connection relationship between at least one device and other devices in the circuit system. The determination unit is also used to determine the type of at least one device according to the identification information of at least one device; and, according to the connection relationship of at least one device, determine the flow direction of at least one clock signal in the circuit system. The generation unit is used to generate a clock tree corresponding to the clock network according to the type of at least one device and the flow direction of at least one clock signal.

[0314] It should be noted that this embodiment can be implemented by a general physical server, for example, an ARM server or an X86 server, or it can be implemented by a virtual machine based on a general physical server combined with NFV technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment. This application does not make any specific limitations.

[0315] The memory 1930 may include a volatile memory, such as a random access memory (RAM); the memory 1930 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 1930 may also include a combination of the above. The memory 1930 may store program code, execute Figure 2 Steps S210 to S250 and their optional steps in the embodiment, or specific implementation Figure 4 Steps S401 to S419 and their optional steps in the embodiment, or executing Fig.15 S1501 to S1518 in the embodiment and the optional steps thereof, or executing Fig.16 S1601 to S1618 in the embodiment and the optional steps thereof, or executing Fig.17 Steps S1701 to S1717 and their optional steps in the embodiment will not be described in detail here.

[0316] The communication interface 1920 can be a wired interface (such as an Ethernet interface), an internal interface (such as a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe) bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless local area network interface) for communicating with other devices or modules.

[0317] Need to explain, Fig.19 This is only one possible implementation of the embodiment of the present application. In practical applications, the computing device 1900 may also include more or fewer components, which is not limited here. For the contents not shown or described in the embodiment of the present application, please refer to the aforementioned Figure 2 , Figure 4 , Fig.15 , Fig.16 as well as Fig.17 The relevant explanations in the embodiments will not be repeated here.

[0318] It should be understood that Fig.19 The computing device shown may also be a computer cluster consisting of at least one server, which is not specifically limited in this application.

[0319] The present application also provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a processor, Figure 2 , Figure 4 , Fig.15 , Fig.16 or Fig.17 The method flow shown is realized.

[0320] The present application also provides a computer program product. When the computer program product is run on a processor, Figure 2 , Figure 4 , Fig.15 , Fig.16 or Fig.17 The method flow shown is realized.

[0321] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0322] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0323] The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media sets. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (DVD), or a semiconductor medium. The semiconductor medium may be an SSD.

[0324] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.< / lewis>

Claims

1. A clock tree generation method, characterized in that: Applied to electronic equipment, the method comprises: Acquire a network identifier of at least one network in a circuit system, identifier information of devices in the at least one network, and connection status between devices; Determine a clock network in the at least one network according to the network identifier of the at least one network, the clock network being used to output at least one clock signal; Determining identification information of at least one device in the clock network and a connection relationship between the at least one device and other devices in the circuit system; Determining the type of the at least one device according to the identification information of the at least one device; and, determining the flow direction of at least one clock signal in the circuit system according to the connection relationship of the at least one device; and A clock tree corresponding to the circuit system is generated according to the type of the at least one device and the flow direction of the at least one clock signal.

2. The method according to claim 1, characterized in that The determining the type of the at least one device according to the identification information of the at least one device includes: A clock source device is determined in at least one device of the clock network according to the identification information of the at least one device, and the clock source device is used to generate a clock signal.

3. The method according to claim 2, characterized in that The determining the type of the at least one device according to the identification information of the at least one device includes: Acquire identification information of a device connected to the clock network according to identification information of a device in at least one network in the circuit system and a connection status between the devices; A clock demanding device is determined according to identification information of a device connected to the clock network, where the clock demanding device is a device that consumes a clock signal.

4. The method according to claim 3, characterized in that: The determining the type of the at least one device according to the identification information of the at least one device includes: A clock conversion device is determined in at least one device of the clock network according to the identification information of the at least one device, wherein the clock conversion device is used to change a parameter value of a clock signal.

5. The method according to claim 4, characterized in that Generating a clock tree corresponding to the circuit system according to the type of the at least one device and the flow direction of the at least one clock signal includes: A clock tree corresponding to the circuit system is generated according to the clock source device, the clock conversion device, the clock demand device and the flow direction of the at least one clock signal, and the clock tree includes parameter values ​​of the at least one clock signal at the pins of the clock source device, the clock conversion device and the clock demand device.

6. The method according to claim 1, characterized in that The method further comprises: Acquire device identification configuration data, wherein the device identification configuration data includes a correspondence between identification information and a type of at least one device; The determining the type of the at least one device according to the identification information of the at least one device includes: The type of the at least one device is determined according to the device identification configuration data and the identification information of the at least one device.

7. The method according to claim 6, characterized in that The device identification configuration data comes from a device identification database connected to the electronic device.

8. The method according to claim 1, characterized in that The method further comprises: Acquire network identification configuration data, wherein the network identification configuration data includes a correspondence between at least one network identification and a network type; The step of determining the clock network in the at least one network according to the network identifier of the at least one network includes: The clock network is determined in the at least one network according to the network identification configuration data and the network identification of the at least one network.

9. The method according to claim 8, characterized in that The network identification configuration data comes from a network identification database connected to the electronic device.

10. The method according to claim 1, characterized in that The obtaining of the network identification of at least one network in the circuit system and the identification information of the devices in the at least one network and the connection status between the devices includes: Determine a netlist file corresponding to the circuit system; The netlist file is parsed to obtain a network identifier of at least one network in the circuit system, identification information of devices in the at least one network, and connection status between devices.

11. The method according to claim 1, characterized in that: The identification information of the at least one device includes one or more of a code, a bit number, and a keyword of the at least one device.

12. The method according to claim 5, characterized in that The circuit system further includes one or more of a power supply network and a bus network; The clock source device includes one or more of a crystal oscillator, a clock oscillator, a resonant tank circuit, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; The clock conversion device includes one or more of a frequency synthesizer, a frequency divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; The parameter value of the clock signal includes one or more of frequency, signal strength, and phase.

13. A readable medium, characterized in that: The readable medium contains instructions, which, when executed by a processor of an electronic device, enable the electronic device to implement the method of any one of claims 1 to 12.

14. An electronic device, characterized in that: include: a memory for storing instructions to be executed by one or more processors of the electronic device; and a processor, which is one of the processors of the electronic device, configured to execute the instructions so that the electronic device implements the method according to any one of claims 1 to 12.

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