Neural network accelerator based on eDRAM in-memory calculation and control method thereof

Abstract

The invention discloses a neural network accelerator based on eDRAM in-memory calculation and a control method thereof, the neural network accelerator comprises a top layer controller and an extensible and reconfigurable SR-CIM macro array, and the extensible and reconfigurable SR-CIM macro array is operated in a global system mode. The method comprises the following steps: acquiring weight data and input activation data; setting a working mode of the extensible and reconfigurable SR-CIM macro array; and according to the working mode of the extensible and reconfigurable SR-CIM macro array, performing operation on the weight data and the input activation data, and transmitting an operation result to the off-chip neural network. According to the embodiment of the invention, the computing efficiency of the neural network can be improved by improving the reuse rate of the data and reducing the access times of the off-chip data in different data flow modes. The method can be widely applied to the technical field of neural network accelerators.

Description

Technical Field

[0001] The present application relates to the technical field of neural network accelerators, and in particular to a neural network accelerator based on eDRAM in-memory computing and a control method thereof. Background Art

[0002] With the rapid development of artificial intelligence technology, deep neural networks (DNNs) have achieved remarkable results in image recognition, natural language processing and other fields. However, the computational complexity and data movement of DNNs have brought great challenges to traditional computing architectures. Computing-in-memory (CIM) is an emerging technology that can significantly reduce data movement and improve computing efficiency by integrating computing units with storage units. However, CIM accelerators in related technologies have certain limitations in data flow support, storage density, and power consumption. For example, most CIM accelerators only support a single weighted fixed (WS) data flow and cannot give full play to the advantages of different data flows; the density of storage units is low, which limits the integration and performance improvement of the accelerator, and it has a high power consumption problem.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a neural network accelerator based on eDRAM in-memory computing and a control method thereof, which can improve the computing efficiency of the neural network by increasing the data reuse rate and reducing the number of data accesses under different data flow modes.

[0005] To achieve the above-mentioned object, an embodiment of the present application proposes a neural network accelerator based on eDRAM in-memory computing, wherein the neural network accelerator includes a top-level controller and an extensible and reconfigurable SR-CIM macroarray, wherein the top-level controller and the extensible and reconfigurable SR-CIM macroarray are electrically connected, and the extensible and reconfigurable SR-CIM macroarray is operated in a global systolic manner, wherein:

[0006] The top-level controller is used to control the operation of the scalable and reconfigurable SR-CIM macro array;

[0007] The scalable and reconstructible SR-CIM macro array is used to obtain weight data and input activation data, perform calculations according to a preset working mode, and transmit the calculation results to an off-chip neural network.

[0008] In some embodiments, the scalable and reconfigurable SR-CIM macro array includes a plurality of SR-CIM macro units, and the plurality of SR-CIM macro units are arranged in an n×n manner.

[0009] In some embodiments, the SR-CIM macro unit includes a local controller, a local input buffer, a 3TeDRAM-CIM array, an in-memory accumulator and an addition tree, the local controller is electrically connected to the local input buffer, the 3TeDRAM-CIM array, the in-memory accumulator and the addition tree, the output end of the local input buffer is connected to the input end of the 3TeDRAM-CIM array, the 3TeDRAM-CIM array is interconnected with the in-memory accumulator and the addition tree, wherein:

[0010] The local controller is used to control the operation of the local input buffer, the 3T eDRAM-CIM array, the in-memory accumulator and the addition tree;

[0011] The local input buffer is used to receive the input activation data transmitted by the off-chip neural network;

[0012] The 3T eDRAM-CIM array is used to receive the weight data transmitted by the off-chip neural network and perform in-memory multiplication calculation on the weight data and the input activation data according to the preset working mode to obtain a calculation result;

[0013] The in-memory accumulator and the addition tree are used to perform accumulation calculations on multi-bit data and multi-channel data according to the calculation results to obtain operation results.

[0014] In some embodiments, the 3T eDRAM-CIM array includes a read word line driver, a write bit line driver, a write word line driver, a read bit line driver, and a plurality of 3T eDRAM-CIM units, and the 3T eDRAM-CIM units are all electrically connected to the read word line driver, the write bit line driver, the write word line driver, and the read bit line driver, wherein:

[0015] The read word line driver, the write bit line driver, the write word line driver and the read bit line driver are used to perform data writing and reading processing;

[0016] The 3T eDRAM-CIM unit is used to perform in-memory multiplication calculations.

[0017] In some embodiments, the 3T eDRAM-CIM unit includes a write access transistor, a first read access transistor, a second read access transistor and a parasitic capacitor, the drain of the write access transistor is connected to the write bit line driver, the gate of the write access transistor is connected to the write word line driver, the gate of the first read access transistor, the source of the write access transistor and the first end of the parasitic capacitor are connected to a storage node, the second end of the parasitic capacitor is grounded, the source of the first read access transistor and the gate of the second read access transistor are both connected to the read word line driver, the drain of the first read access transistor is connected to the drain of the second read access transistor, and the source of the second read access transistor is connected to the read bit line driver.

[0018] To achieve the above object, another aspect of the embodiment of the present application provides a control method for a neural network accelerator based on eDRAM in-memory computing, the control method comprising the following steps:

[0019] Get weight data and input activation data;

[0020] Setting the working mode of the scalable and reconfigurable SR-CIM macro array;

[0021] According to the working mode of the scalable and reconfigurable SR-CIM macroarray, matrix×vector operations and matrix×matrix operations are performed on the weight data and the input activation data, and the operation results are transmitted to the off-chip neural network.

[0022] In some embodiments, the operating modes of the scalable and reconfigurable SR-CIM macro array include a WS operating mode, an OS operating mode, and an RS operating mode, wherein:

[0023] The WS working mode is that the first side of the scalable reconfigurable SR-CIM macro array obtains the weight data and performs data transmission according to the first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array obtains the input activation data and performs data transmission according to the second transmission direction, and the operation result or calculation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to the third transmission direction;

[0024] The OS working mode is that the first side of the scalable reconfigurable SR-CIM macro array obtains the weight data and performs data transmission according to a first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array obtains the input activation data and performs data transmission according to a second transmission direction, and the operation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to a third transmission direction;

[0025] The RS working mode is that the first side of the scalable reconstructed SR-CIM macro array obtains the weight data and performs data transmission according to the first transmission direction, the first side of the scalable reconstructed SR-CIM macro array obtains the input activation data and performs data transmission according to the fourth transmission direction, and the operation result or calculation result is output from the fourth side of the scalable reconstructed SR-CIM macro array to the off-chip neural network according to the second transmission direction.

[0026] In some embodiments, it also includes:

[0027] When the working mode of the scalable and reconfigurable SR-CIM macro array is the WS working mode, the scalable and reconfigurable SR-CIM macro array is used to maximize the storage of the weight data;

[0028] When the operating mode of the scalable and reconfigurable SR-CIM macro array is the OS operating mode, the scalable and reconfigurable SR-CIM macro array is used to maximize the storage of the operation results and the calculation results;

[0029] When the operating mode of the scalable and reconfigurable SR-CIM macroarray is the RS operating mode, the scalable and reconfigurable SR-CIM macroarray is used to equally store the weight data and the input activation data, and maximize the storage of the operation results and the calculation results.

[0030] In some embodiments, the operation steps of the scalable and reconfigurable SR-CIM macro array include:

[0031] Acquire the weight data and the input activation data and transmit them to the 3T eDRAM-CIM array in a bit serial manner;

[0032] Based on the read word line driver of the 3T eDRAM-CIM array, the weight data and the input activation data are transmitted row by row to the 3T eDRAM-CIM unit to perform in-memory multiplication calculation to obtain a calculation result;

[0033] The calculation result is transmitted to the in-memory accumulator and the addition tree to perform multi-bit data accumulation calculation to obtain the operation result;

[0034] The calculation result is output to the off-chip neural network in the WS working mode, and the calculation result is written back to the scalable and reconfigurable SR-CIM macro array in the OS working mode and the RS working mode.

[0035] In some embodiments, the calculation step of the 3T eDRAM-CIM unit includes a write operation and a read operation, wherein:

[0036] For the write operation, the write word line driver is set to a low level, the write access transistor is turned on, and the data on the write bit line driver is transferred to the storage node. If the write bit line driver is at a high level, the data "0" is transferred to the storage node. If the write bit line driver is at a low level, the data "1" is transferred to the storage node, the write word line driver is set to a high level, and the write access transistor is turned off;

[0037] For the read operation, the read word line driver is set to a high level, the second read access transistor is turned on, the read bit line driver is precharged to a high level, and the data of the storage node is read and transmitted to the read bit line driver.

[0038] The embodiments of the present application include at least the following beneficial effects: The present application provides a neural network accelerator based on eDRAM in-memory computing and a control method thereof. The scheme constructs an extensible and reconstructible SR-CIM macro array and operates in a global systolic manner, and can perform calculations according to a preset working mode to adapt to the computing requirements of different neural network models, thereby improving the versatility and adaptability of the accelerator, so that under different data flow modes, the data reuse rate can be maximized, the number of data accesses and redundant MVM operations can be reduced, thereby significantly improving computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the structure of a neural network accelerator based on eDRAM in-memory computing provided in an embodiment of the present application;

[0040] Figure 2 It is a schematic diagram of the steps of a control method of a neural network accelerator based on eDRAM in-memory computing provided in an embodiment of the present application;

[0041] Figure 3 is a schematic diagram of a WS working mode of an extensible and reconfigurable SR-CIM macro array provided in an embodiment of the present application;

[0042] Figure 4 is a schematic diagram of an OS working mode of an extensible and reconfigurable SR-CIM macro array provided in an embodiment of the present application;

[0043] Figure 5 is a schematic diagram of the RS working mode of the scalable and reconfigurable SR-CIM macro array provided in an embodiment of the present application;

[0044] Figure 6 is a schematic diagram of the circuit principle of the SR-CIM macro array provided in an embodiment of the present application;

[0045] Figure 7 is a schematic diagram of the structure of a 3T eDRAM-CIM unit provided in an embodiment of the present application;

[0046] Figure 8 It is a schematic diagram of data comparison between the 3T eDRAM-CIM unit provided in an embodiment of the present application and the existing in-memory computing unit. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0048] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0049] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0051] Reference Figure 1 , Figure 1 A schematic diagram of a neural network accelerator based on eDRAM in-memory computing provided by an embodiment of the present invention, referring to Figure 1 The neural network accelerator includes a top-level controller and an expandable and reconfigurable SR-CIM macro array, the top-level controller and the expandable and reconfigurable SR-CIM macro array are electrically connected, and the expandable and reconfigurable SR-CIM macro array is operated in a global systolic manner, wherein:

[0052] The top-level controller is used to control the operation of the scalable and reconfigurable SR-CIM macroarray;

[0053] The scalable and reconfigurable SR-CIM macroarray is used to obtain weight data and input activation data, perform calculations according to the preset working mode, and transmit the calculation results to the off-chip neural network.

[0054] The scalable and reconfigurable SR-CIM macro array includes a plurality of SR-CIM macro units, and the plurality of SR-CIM macro units are arranged in an n×n manner.

[0055] Furthermore, it should be noted that the SR-CIM macro unit includes a local controller, a local input buffer, a 3T eDRAM-CIM array, an in-memory accumulator and an addition tree. The local controller is electrically connected to the local input buffer, the 3T eDRAM-CIM array, the in-memory accumulator and the addition tree. The output end of the local input buffer is connected to the input end of the 3T eDRAM-CIM array. The 3T eDRAM-CIM array is interconnected with the in-memory accumulator and the addition tree. The local controller is used to control the operation of the local input buffer, the 3T eDRAM-CIM array, the in-memory accumulator and the addition tree; the local input buffer is used to receive input activation data transmitted by an off-chip neural network; the 3T eDRAM-CIM array is used to receive weight data transmitted by an off-chip neural network and perform in-memory multiplication calculations on the weight data and the input activation data according to a preset working mode to obtain a calculation result; the in-memory accumulator and the addition tree are used to perform accumulation calculations on multi-bit data and multi-channel data according to the calculation result to obtain an operation result.

[0056] In summary, an embodiment of the present invention provides a neural network accelerator based on scalable and reconfigurable eDRAM in-memory computing, adopts a global systolic local parallel (GSLP) architecture, including a top-level controller, a weight buffer, an input / output buffer, and a scalable and reconfigurable SR-CIM macroarray (for example, a 2×2 SR-CIM array). The top-level controller is responsible for overall control and scheduling. The weight / input buffer serially receives the weights / inputs transmitted from outside the chip and then transmits the data to the SR-CIM macroarray in parallel. Under the configuration of the top-level controller, the SR-CIM macroarray is intelligently configured to the WS / OS / RS working mode and is responsible for performing matrix × vector / matrix × matrix operations between weights and inputs. The output buffer receives the partial sum or output data calculated by the SR-CIM macroarray in parallel and then transmits the data to the outside of the chip in serial.

[0057] Among them, the entire 2×2 SR-CIM macro array of the embodiment of the present invention operates in a global systolic manner. Since only the edge SR-CIM macros of the array communicate with the outside of the chip, this global systolic operation reduces the input and output bandwidth requirements of the entire chip, while ensuring the orderly flow and efficient processing of data in the entire accelerator. Through carefully designed data transmission paths and control signals, different CIM macros can work together to achieve parallel processing and fast computing of large-scale data.

[0058] In addition, the GSLP architecture has good scalability and can be easily expanded to larger CIM macro arrays to meet application scenarios with different performance requirements. By increasing the number of CIM macros and the corresponding communication network, the computing power and processing throughput of the accelerator can be improved. At the same time, this scalability enables the accelerator to adapt to the growing scale and complexity of future neural network models.

[0059] Specifically, Figure 6 As shown, the 3T eDRAM-CIM array includes a read word line driver, a write bit line driver, a write word line driver, a read bit line driver and a plurality of 3T eDRAM-CIM units, and the 3T eDRAM-CIM units are all electrically connected to the read word line driver, the write bit line driver, the write word line driver and the read bit line driver, wherein the read word line driver, the write bit line driver, the write word line driver and the read bit line driver are used to perform data writing and reading processing; the 3T eDRAM-CIM unit is used to perform in-memory multiplication calculations.

[0060] More specifically, if Figure 7 As shown, the 3T eDRAM-CIM cell includes a write access transistor M 1 , the first read access transistor M 2 , the second read access transistor M 3 and parasitic capacitance C S , the drain of the write access transistor is connected to the write bit line driver, the gate of the write access transistor is connected to the write word line driver, the gate of the first read access transistor, the source of the write access transistor and the first end of the parasitic capacitor are connected to the storage node, the second end of the parasitic capacitor is grounded, the source of the first read access transistor and the gate of the second read access transistor are both connected to the read word line driver, the drain of the first read access transistor is connected to the drain of the second read access transistor, and the source of the second read access transistor is connected to the read bit line driver.

[0061] Further, it should be noted that the 3T eDRAM-CIM unit consists of a write access transistor (M 1 ), read access transistor (M 2 With M 3) and the parasitic capacitance of the storage node (C S ) 1 Controlled by the write word line (WWL), used to write data from the write bit line (WBL) to the storage node; M 3 Controlled by the read word line (RWL) to read data from the storage node to the read bit line (RBL).

[0062] See also Figure 2 The embodiment of the present application also provides a control method for a neural network accelerator based on eDRAM in-memory computing, which can implement the above-mentioned neural network accelerator based on eDRAM in-memory computing. The control method includes the following steps:

[0063] S100, obtaining weight data and input activation data;

[0064] S200, setting a working mode of an expandable and reconfigurable SR-CIM macro array;

[0065] It should be noted that, in some embodiments, the operating modes of the scalable and reconfigurable SR-CIM macro array include a WS operating mode, an OS operating mode, and an RS operating mode.

[0066] First of all, it should be explained that in the embodiment of the present invention, the first side of the scalable reconstructed SR-CIM macro array is defined as the west side of the scalable reconstructed SR-CIM macro array, the second side of the scalable reconstructed SR-CIM macro array is the south side of the scalable reconstructed SR-CIM macro array, the third side of the scalable reconstructed SR-CIM macro array is the east side of the scalable reconstructed SR-CIM macro array, the fourth side of the scalable reconstructed SR-CIM macro array is the north side of the scalable reconstructed SR-CIM macro array, and the first transmission direction is from west to east. The second transmission direction is from south to north, the third transmission direction is from west to east, and the fourth transmission direction is from southwest to northeast.

[0067] In some specific embodiments, the WS working mode is that the first side of the scalable reconfigurable SR-CIM macro array obtains weight data and performs data transmission according to a first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array obtains input activation data and performs data transmission according to a second transmission direction, and the operation result or calculation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to a third transmission direction;

[0068] Specifically, Figure 3As shown in the figure, in the WS data flow mode, the weight is transmitted from west to east after being transmitted to the west SR-CIM macro, and the input is transmitted from south to north after being transmitted to the south SR-CIM macro. The partial sum or final output result calculated by each SR-CIM macro is also transmitted from west to east in turn, and is finally output to the outside of the chip by the east SR-CIM macro.

[0069] More specifically, at the global level, weights are vertically mapped to the SR-CIM macro array according to the core dimension and transmitted horizontally from west to east; input activations are vertically transmitted from south to north; output activations or partial sums are horizontally accumulated from west to east. At the local level, most of the memory in each SR-CIM macro is used to store weights, and input activations are mapped to each row of IALB in channel order and transmitted to the eDRAM-CIM channel through MUX for bit-serial computation.

[0070] The OS working mode is that the first side of the scalable reconfigurable SR-CIM macro array acquires weight data and performs data transmission according to a first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array acquires input activation data and performs data transmission according to a second transmission direction, and the operation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to a third transmission direction;

[0071] Specifically, Figure 4 As shown in the figure, in the OS data flow mode, the weights are transmitted from west to east after being transmitted to the west SR-CIM macro, and the inputs are transmitted from south to north after being transmitted to the south SR-CIM macro. The partial sums calculated by each SR-CIM macro are fully accumulated in each SR-CIM macro, and then the final output result is transmitted from west to east, and finally output to the outside of the chip by the east SR-CIM macro.

[0072] More specifically, the global data transfer direction is the same as the WS data flow, but in order to maximize the multiplexing of output activations or partial sums, in each SR-CIM macro, the output activations or partial sums are accumulated locally and stored in 16 eDRAM-CIM channels in channel order. During MVM operation, since only one row of eDRAM is used to store weights, the 1-to-18 MUX is bypassed.

[0073] The RS working mode is that the first side of the scalable reconstructed SR-CIM macro array obtains weight data and performs data transmission according to the first transmission direction, the first side of the scalable reconstructed SR-CIM macro array obtains input activation data and performs data transmission according to the fourth transmission direction, and the operation result or calculation result is output from the fourth side of the scalable reconstructed SR-CIM macro array to the off-chip neural network according to the second transmission direction.

[0074] Specifically, Figure 5As shown in the figure, in the RS data flow mode, the weight is transmitted from west to east after being transmitted to the west SR-CIM macro, the input is first transmitted to the west SR-CIM macro, and finally transmitted from southwest to northeast, and the partial sum or final output result calculated by each SR-CIM macro is transmitted from south to north in turn, and finally output to the outside of the chip by the north SR-CIM macro.

[0075] More specifically, at the global level, weights are vertically mapped to the SR-CIM macroarray along the row dimension and broadcast horizontally from west to east; input activations are transmitted diagonally; and output activations or partial sums are vertically accumulated from south to north. At the local level, in each eDRAM-CIM channel, the first 3 rows are used to store weights, the next 3 rows are used to store input activations, and the remaining 12 rows are used to store output activations or partial sums. During MVM operation, the 1-to-18 MUX is reconfigured to a 1-to-3 MUX to match the 3-row storage of weights.

[0076] It should be noted that each SRCIM macro includes an 18-kb main eDRAM-CIM array, which is organized into 16 channels, each channel contains 18 rows and 64 columns. This storage structure design is conducive to efficient data storage and access, while supporting reconfigurable memory allocation.

[0077] In addition, in this embodiment, it should be noted that when the working mode of the scalable reconstructed SR-CIM macro array is the WS working mode, the scalable reconstructed SR-CIM macro array is used to maximize the storage of weight data; when the working mode of the scalable reconstructed SR-CIM macro array is the OS working mode, the scalable reconstructed SR-CIM macro array is used to maximize the storage of operation results and calculation results; when the working mode of the scalable reconstructed SR-CIM macro array is the RS working mode, the scalable reconstructed SR-CIM macro array is used to equally store weight data and input activation data, maximizing the storage of operation results and calculation results.

[0078] That is, within each CIM macro, according to different data flow modes, the weights, input activations, and output activations are reasonably stored and processed for optimization. For example, in the WS data flow mode, most of the memory is used to store weights to increase the reuse rate of weights; in the OS data flow mode, more memory is allocated to output activations or partial sums to reduce data movement. Through this global and local collaborative working method, the GSLP architecture can give full play to the advantages of each part and achieve efficient neural network computing.

[0079] Exemplarily, the SRCIM macro has a reconfigurable weight / input / output memory ratio feature. By adjusting the memory allocation ratio, the reuse of related data can be maximized according to different data flow modes. For example, in the WS data flow mode, more memory is used to store weights to improve the reuse rate of weights; in the OS data flow mode, more memory is allocated to output activations or partial sums to reduce data movement.

[0080] Therefore, since the GSLP architecture supports multiple data flow modes and can be flexibly configured according to the characteristics of the model, it has strong adaptability to different types of neural network models. Both convolutional neural networks (CNN) and Transformer-based models can run efficiently on the GSLP-CIM accelerator. This adaptability makes the accelerator have broad application prospects in various artificial intelligence applications.

[0081] S300, according to the working mode of the scalable and reconfigurable SR-CIM macro array, performing matrix × vector operations and matrix × matrix operations on the weight data and the input activation data, and transmitting the operation results to the off-chip neural network;

[0082] It should be noted that, in some embodiments, the operation steps of the scalable and reconstructible SR-CIM macro array include:

[0083] S310, obtaining weight data and input activation data and transmitting them to the 3TeDRAM-CIM array in a bit serial manner;

[0084] S320, based on the read word line driver of the 3T eDRAM-CIM array, transmit the weight data and the input activation data to the 3T eDRAM-CIM unit row by row to perform in-memory multiplication calculation to obtain a calculation result;

[0085] S330, transmitting the calculation result to the in-memory accumulator and the addition tree to perform multi-bit data accumulation calculation to obtain the calculation result;

[0086] S340, the calculation result is output to the off-chip neural network in the WS working mode, and the calculation result is written back to the scalable and reconfigurable SR-CIM macro array in the OS working mode and the RS working mode.

[0087] Specifically, the local input buffer reads out the input data; the input data is selected by the 64-to-16 data selector and transmitted to the RWL drivers of the 16-channel eDRAM-CIM array in a bit-serial manner, thereby realizing multi-bit input calculation; within each channel, the RWL driver of the eDRAM-CIM array selects to transmit the input data row by row to different eDRAM-CIM rows to perform in-memory multiplication calculation (input multiplied by weight); within each channel, the eDRAM-CIM array transmits the multiplication calculation result to the in-memory accumulator to perform accumulation of multi-bit input data; the accumulation result of the in-memory accumulator is output to the addition tree to perform accumulation of multiplication results between multiple channels; the accumulation result of the addition tree is output in the WS and RS data flow working modes, and is written back to the eDRAM-CIM array in the OS data flow working mode.

[0088] In some specific embodiments, the calculation steps of the 3T eDRAM-CIM unit include a write operation and a read operation, wherein, for a write operation, the write word line driver is set to a low level, the write access transistor is turned on, and the data on the write bit line driver is transmitted to the storage node. If the write bit line driver is at a high level, the data "0" is transmitted to the storage node. If the write bit line driver is at a low level, the data "1" is transmitted to the storage node, the write word line driver is set to a high level, and the write access transistor is turned off; for a read operation, the read word line driver is set to a high level, the second read access transistor is turned on, the read bit line driver is precharged to a high level, the data of the storage node is read and transmitted to the read bit line driver.

[0089] Specifically, efficient data reading and writing operations are achieved by cleverly utilizing the capacitance characteristics of the storage node and the switching control of the transistor.

[0090] During a write operation:

[0091] 1) Set WWL to a low level, so that transistor M1 is turned on;

[0092] 2) The data on WBL is transmitted to the storage node. When WBL is high, data 0 is written, and when WBL is low, data 1 is written;

[0093] 3) Set WWL to high level to turn off transistor M1.

[0094] During a read operation:

[0095] 1) Set RWL to low level to turn on transistor M3;

[0096] 2) Precharge RBL to a high level;

[0097] 3) The voltage in the storage node is read out to RBL. Only when the storage node is at a low level will RBL be discharged to a low level. At the same time, by storing the weight in the eDRAM cell and activating it with the RWL transfer input, a 1bAND operation can be implemented within the cell, providing a basis for MVM calculation.

[0098] Therefore, the 3T eDRAM-CIM unit proposed in the embodiment of the present invention has a significant high density advantage. Figure 8 As shown in Table 1, compared with the existing 1T1CeDRAM-CIM cell, the cell density of the 3TeDRAM-CIM cell based on logic rules is increased by 1.49 times; even compared with the 8T SRAM-CIM cell based on compact rules, the cell density is still increased by 1.3 times. This high-density design helps to reduce the chip area and improve the integration and performance of the accelerator.

[0099] Table 1 3T eDRAM-CIM operation data table

[0100] enter Weight Input × Weight RWH <![CDATA[V W ]]> RBL <![CDATA[0(V DD )]]> <![CDATA[0 / 1(V DD / V SS )]]> <![CDATA[0(V DD )]]> <![CDATA[1(V SS )]]> <![CDATA[0(V DD )]]> <![CDATA[0(V DD )]]> <![CDATA[1(V SS )]]> <![CDATA[1(V SS )]]> <![CDATA[1(V SS )]]>

[0101] In summary, the embodiments of the present invention have the following advantages compared with the related art:

[0102] 1) Support for multiple data flow modes: Through the GSLP architecture and the reconfigurable SRCIM macro, the accelerator of the present invention can flexibly support multiple data flow modes such as WS, OS and RS, adapt to the computing requirements of different neural network models, and improve the versatility and adaptability of the accelerator.

[0103] 2) Improve data reuse rate and computing efficiency: The reconfigurable memory ratio design and optimized workload mapping strategy of the SRCIM macro can maximize the data reuse rate under different data flow modes, reduce the number of data accesses and redundant MVM operations, and thus significantly improve computing efficiency.

[0104] 3) High-density storage and small area advantages: The use of high-density 3T eDRAM-CIM units has significantly improved unit density compared to existing technologies, reduced chip area, and is conducive to the realization of more highly integrated neural network accelerators.

[0105] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0106] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A neural network accelerator based on eDRAM in-memory computing, characterized in that: The neural network accelerator includes a top-level controller and an extensible and reconfigurable SR-CIM macroarray, wherein the top-level controller and the extensible and reconfigurable SR-CIM macroarray are electrically connected, and the extensible and reconfigurable SR-CIM macroarray is operated in a global systolic manner, wherein: The top-level controller is used to control the operation of the scalable and reconfigurable SR-CIM macro array; The scalable and reconstructible SR-CIM macro array is used to obtain weight data and input activation data, perform calculations according to a preset working mode, and transmit the calculation results to an off-chip neural network.

2. The neural network accelerator according to claim 1, characterized in that: The scalable and reconfigurable SR-CIM macro array includes a plurality of SR-CIM macro units, and the plurality of SR-CIM macro units are arranged in an n×n manner.

3. The neural network accelerator according to claim 2, characterized in that: The SR-CIM macro unit includes a local controller, a local input buffer, a 3T eDRAM-CIM array, an in-memory accumulator and an addition tree. The local controller is electrically connected to the local input buffer, the 3T eDRAM-CIM array, the in-memory accumulator and the addition tree. The output end of the local input buffer is connected to the input end of the 3TeDRAM-CIM array. The 3T eDRAM-CIM array is connected to the in-memory accumulator and the addition tree. The local controller is used to control the operation of the local input buffer, the 3T eDRAM-CIM array, the in-memory accumulator and the addition tree; The local input buffer is used to receive the input activation data transmitted by the off-chip neural network; The 3T eDRAM-CIM array is used to receive the weight data transmitted by the off-chip neural network and perform in-memory multiplication calculation on the weight data and the input activation data according to the preset working mode to obtain a calculation result; The in-memory accumulator and the addition tree are used to perform accumulation calculations on multi-bit data and multi-channel data according to the calculation results to obtain operation results.

4. The neural network accelerator according to claim 3, characterized in that: The 3T eDRAM-CIM array includes a read word line driver, a write bit line driver, a write word line driver, a read bit line driver and a plurality of 3T eDRAM-CIM units, and the 3T eDRAM-CIM units are all electrically connected to the read word line driver, the write bit line driver, the write word line driver and the read bit line driver, wherein: The read word line driver, the write bit line driver, the write word line driver and the read bit line driver are used to perform data writing and reading processing; The 3T eDRAM-CIM unit is used to perform in-memory multiplication calculations.

5. The neural network accelerator according to claim 4, characterized in that: The 3T eDRAM-CIM unit includes a write access transistor, a first read access transistor, a second read access transistor and a parasitic capacitor, the drain of the write access transistor is connected to the write bit line driver, the gate of the write access transistor is connected to the write word line driver, the gate of the first read access transistor, the source of the write access transistor and the first end of the parasitic capacitor are connected to a storage node, the second end of the parasitic capacitor is grounded, the source of the first read access transistor and the gate of the second read access transistor are both connected to the read word line driver, the drain of the first read access transistor is connected to the drain of the second read access transistor, and the source of the second read access transistor is connected to the read bit line driver.

6. A control method for a neural network accelerator based on eDRAM in-memory computing, characterized in that: The control method comprises the following steps: Get weight data and input activation data; Setting the working mode of the scalable and reconfigurable SR-CIM macro array; According to the working mode of the scalable and reconfigurable SR-CIM macroarray, matrix×vector operations and matrix×matrix operations are performed on the weight data and the input activation data, and the operation results are transmitted to the off-chip neural network.

7. The method according to claim 6, characterized in that The operating modes of the scalable and reconfigurable SR-CIM macro array include a WS operating mode, an OS operating mode and an RS operating mode, wherein: The WS working mode is that the first side of the scalable reconfigurable SR-CIM macro array obtains the weight data and performs data transmission according to the first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array obtains the input activation data and performs data transmission according to the second transmission direction, and the operation result or calculation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to the third transmission direction; The OS working mode is that the first side of the scalable reconfigurable SR-CIM macro array obtains the weight data and performs data transmission according to a first transmission direction, the second side of the scalable reconfigurable SR-CIM macro array obtains the input activation data and performs data transmission according to a second transmission direction, and the operation result is output from the third side of the scalable reconfigurable SR-CIM macro array to the off-chip neural network according to a third transmission direction; The RS working mode is that the first side of the scalable reconstructed SR-CIM macro array obtains the weight data and performs data transmission according to the first transmission direction, the first side of the scalable reconstructed SR-CIM macro array obtains the input activation data and performs data transmission according to the fourth transmission direction, and the operation result or calculation result is output from the fourth side of the scalable reconstructed SR-CIM macro array to the off-chip neural network according to the second transmission direction.

8. The method according to claim 7, characterized in that Also includes: When the working mode of the scalable and reconfigurable SR-CIM macro array is the WS working mode, the scalable and reconfigurable SR-CIM macro array is used to maximize the storage of the weight data; When the operating mode of the scalable and reconfigurable SR-CIM macro array is the OS operating mode, the scalable and reconfigurable SR-CIM macro array is used to maximize the storage of the operation results and the calculation results; When the operating mode of the scalable and reconfigurable SR-CIM macroarray is the RS operating mode, the scalable and reconfigurable SR-CIM macroarray is used to equally store the weight data and the input activation data, and maximize the storage of the operation results and the calculation results.

9. The method according to claim 7, characterized in that: The operation steps of the scalable and reconfigurable SR-CIM macro array include: Obtaining the weight data and the input activation data and transmitting them to the 3TeDRAM-CIM array in a bit-serial manner; Based on the read word line driver of the 3T eDRAM-CIM array, the weight data and the input activation data are transmitted row by row to the 3T eDRAM-CIM unit to perform in-memory multiplication calculation to obtain a calculation result; The calculation result is transmitted to the in-memory accumulator and the addition tree to perform multi-bit data accumulation calculation to obtain the operation result; The calculation result is output to the off-chip neural network in the WS working mode, and the calculation result is written back to the scalable and reconfigurable SR-C IM macro array in the OS working mode and the RS working mode.

10. The method according to claim 7, characterized in that The calculation steps of the 3T eDRAM-C IM unit include a write operation and a read operation, wherein: For the write operation, the write word line driver is set to a low level, the write access transistor is turned on, and the data on the write bit line driver is transmitted to the storage node. If the write bit line driver is at a high level, the data "0" is transmitted to the storage node. If the write bit line driver is at a low level, the data "1" is transmitted to the storage node, the write word line driver is set to a high level, and the write access transistor is turned off; For the read operation, the read word line driver is set to a high level, the second read access transistor is turned on, the read bit line driver is precharged to a high level, and the data of the storage node is read and transmitted to the read bit line driver.

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