Pattern load line width adjusting method in SADP mandrel etching
By pretreatment and multi-layer etching technology on photoresist, the problem of load effect after sparse and dense pattern development in SADP mandrel etching is solved, the matching of the trench line width and the defined line width is achieved, and the metal is improved The density and pitch control effect of wiring.
Patent Information
- Application Number
- CN202310847828.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-11
- Publication Date
- 2025-01-14
AI Technical Summary
During the SADP mandrel etching process, sparse and dense patterns produce a load effect after development, resulting in a difference between the trench linewidth of the photoresist pattern and the defined linewidth, affecting the density and pitch control of metal wiring.
By pretreating the photoresist before etching, including removing residues at the bottom of the trench and eliminating sidewall tilt, eliminating load effects, and etching the hard mask, SOC and A-Si layers in sequence until the TEOS layer is exposed, Remove the SOC graphic structure to form a mandrel structure.
The difference between the trench line width and the defined line width after etching is effectively reduced, the matching degree of line widths between the dense and sparse areas of the graphics is improved, and the density and pitch control of metal wiring is improved.
Smart Images
Figure CN119314858A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for adjusting the line width of a pattern load in SADP mandrel etching. Background Art
[0002] With the rapid development of integrated circuits, the continuous improvement of integration and the continuous reduction of feature size, the process of back-end metal lines will also be implemented using self-aligned double patterning (SADP) technology. It is a sidewall spacer transfer patterning technology. Its advantage is that for any given line defined by photolithography, a spacer layer can be deposited on the side of each mandrel. After the spacer layer is etched, the original mandrel template material is removed, which can effectively double the line density. This method has excellent line width and pitch control effects for high-density parallel lines. After the spacer layer is etched, a spacer layer is formed on the side of each mandrel. Finally, the target layer below is etched using the formed sidewall spacer layer as a mask layer to form the final graphic layer.
[0003] The size of the mandrel groove is defined by the photolithography process, and then the mandrel pattern is finally defined through the hard mask dielectric anti-reflective layer, amorphous carbon layer, and mandrel layer dry etching process. As the mask layer of the metal wiring, the mandrel pattern involves the design of different line widths. In the mandrel dry etching, under different graphic designs, it will cause sparse or dense graphic line width load effects. For example, after development, photoresist development residues appear in the dense and sparse areas of the pattern; the morphology of the photoresist pattern after development is different between the dense and sparse areas of the pattern.
[0004] Due to the design limitations of the mask layout and the process window limitations of the photolithography process, the dry etching process is required to have a certain method for adjusting the line width of the graphic load. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for adjusting the line width of pattern load in SADP mandrel etching, so as to solve the problem of load effect of sparse patterns and dense patterns after development in the prior art.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for adjusting the line width of a pattern load in SADP mandrel etching, which at least comprises:
[0007] Step 1, providing a semiconductor structure, the semiconductor structure comprising: a TEOS layer, an A-Si layer, a SOC layer, and a hard mask layer stacked from bottom to top; spin coating a layer of photoresist on the hard mask layer, and then using a photolithography process to define the groove line width, forming a photoresist pattern in a pattern-dense area and a photoresist pattern in a pattern-sparse area, and the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area have a loading effect;
[0008] Step 2, pre-processing the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area to eliminate the loading effect;
[0009] Step 3, etching the hard mask layer according to the photoresist pattern after eliminating the loading effect until the surface of the SOC layer is exposed, so as to form a hard mask pattern structure;
[0010] Step 4, etching the SOC layer according to the hard mask pattern until the A-Si surface is exposed to form a SOC pattern structure;
[0011] Step 5, etching the A-Si layer according to the SOC pattern until the surface of the TEOS layer is exposed to form a mandrel structure;
[0012] Step six: removing the SOC graphic structure.
[0013] Preferably, the loading effect of the photoresist pattern in the pattern-dense area in step one includes photoresist residue at the bottom of the photoresist pattern groove formed after the photolithography process is developed and the sidewall of the photoresist pattern formed after the photolithography process is developed is tilted, thereby causing the groove line width of the photoresist pattern to be different from the groove line width defined by it.
[0014] Preferably, the loading effect of the photoresist pattern in the sparsely-patterned area in step one includes photoresist residue at the bottom of the photoresist pattern groove formed after the photolithography process is developed and the sidewall of the photoresist pattern formed after the photolithography process is developed is tilted, thereby causing a difference between the groove line width of the photoresist pattern and the groove line width defined by it.
[0015] Preferably, the difference between the groove line width of the photoresist pattern in the sparse pattern area and the groove line width defined by it is greater than the difference between the groove line width of the photoresist pattern in the dense pattern area and the groove line width defined by it.
[0016] Preferably, the hard mask layer in step one is a dielectric anti-reflection layer.
[0017] Preferably, in step 4, the SOC layer is etched by dry etching to form a SOC graphic structure.
[0018] Preferably, in step five, the A-Si layer is etched by dry etching to form the mandrel structure.
[0019] Preferably, in step six, ashing dry etching is used to remove the SOC graphic structure.
[0020] Preferably, the method for pre-processing the photoresist pattern in the pattern-dense area in step 2 includes: removing the residual photoresist at the bottom of the photoresist pattern groove in the pattern-dense area and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the groove line width defined by it.
[0021] Preferably, the method for preprocessing the photoresist pattern in the sparsely patterned area in step 2 includes: removing the residual photoresist at the bottom of the photoresist pattern groove in the densely patterned area and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the defined groove line width.
[0022] As described above, the method for adjusting the graphic load line width in SADP spindle etching of the present invention has the following beneficial effects: the present invention reduces or even eliminates its load effect by pretreating the photoresist before etching, thereby reducing the difference between the groove line width after etching and the defined line width. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figures 1 to 6 It is a schematic diagram showing the structure formed by each step of the method for adjusting the line width of a pattern load in SADP mandrel etching of the present invention;
[0024] Figure 7 Shown is a flow chart of the pattern load line width adjustment method in SADP mandrel etching of the present invention. DETAILED DESCRIPTION
[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0027] The present invention provides a method for adjusting the line width of a pattern load in SADP mandrel etching, such as Figure 7As shown, including at least:
[0028] Step 1: Provide a semiconductor structure, wherein the semiconductor structure includes: a TEOS layer, an A-Si layer, a SOC layer, and a hard mask layer stacked from bottom to top; spin-coat a layer of photoresist on the hard mask layer, and then use a photolithography process to define the trench line width (i.e. Figure 6 The trench line width after the mandrel structure 10 is formed by etching in the middle) forms a photoresist pattern in a pattern-dense area and a photoresist pattern in a pattern-sparse area, and a load effect occurs in the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area; Figure 1 As shown, the semiconductor structure includes: a TEOS (tetraethylorthosilicate) layer 01, an A-Si (amorphous silicon) layer 02, a SOC (amorphous carbon) layer 03, and a hard mask layer 04 stacked from bottom to top; a layer of photoresist is spin-coated on the hard mask layer, and then the trench line width is defined by a photolithography process to form a photoresist pattern in a pattern-dense area and a photoresist pattern in a pattern-sparse area ( Figure 1 The photoresist pattern 05 is used to uniformly identify the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area), and the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area have a load effect. Figure 1 The photoresist pattern groove 06 is used to uniformly identify the grooves of the photoresist pattern in the pattern-dense area and the grooves of the photoresist pattern in the pattern-sparse area.
[0029] The present invention further provides that the loading effect of the photoresist pattern in the pattern-dense area in step one of this embodiment includes photoresist residue at the bottom of the photoresist pattern groove formed after the photolithography process is developed and the side walls of the photoresist pattern formed after the photolithography process are tilted, thereby causing a difference between the groove line width of the photoresist pattern and the groove line width defined by it.
[0030] The present invention further provides that the loading effect of the photoresist pattern in the sparsely-patterned area in step one of this embodiment includes photoresist residue at the bottom of the groove of the photoresist pattern formed after the photolithography process is developed and the sidewalls of the photoresist pattern formed after the photolithography process are tilted, thereby causing a difference between the groove line width of the photoresist pattern and the groove line width defined by it.
[0031] The present invention further, in step 1 of the present embodiment, the difference between the groove line width of the photoresist pattern in the sparse pattern area and the groove line width defined by it is greater than the difference between the groove line width of the photoresist pattern in the dense pattern area and the groove line width defined by it. The deviation of the critical dimension of the dense pattern of the groove after etching and the deviation of the critical dimension of the sparse pattern are the results of the synergistic changes between isotropic chemical etching, anisotropic physical bombardment etching, and the protection of the polymer deposition on the sidewall of the groove. Since the consumption requirements of the etching plasma groups of the patterns of different densities are different, the amount of the by-product polymers produced is also different, and there is a difference in the concentration of the chemical and polymer groups produced between the dense pattern area and the sparse pattern area. If these groups produced cannot be discharged in time, a load effect is generated.
[0032] Since the proportion of the exposed sidewalls of the material to be etched in the dense pattern area is much higher than that in the sparse pattern area, any changes in the deposition of the isotropic chemical etching groups used for etching reactions and the plasma atmosphere polymer for sidewall protection are weakened. On the contrary, the changes in the etching groups and polymer deposition caused by changes in these etching reaction parameters are amplified in the pattern area of the sparse grooves. This makes the sparse groove pattern more sensitive to changes in etching parameters than the dense groove.
[0033] Furthermore, in the present invention, the hard mask layer in step 1 of this embodiment is a dielectric anti-reflection layer.
[0034] Step 2, pre-processing the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area to eliminate the loading effect;
[0035] The present invention further provides that the method for pre-processing the photoresist pattern in the pattern-dense area in step 2 of this embodiment includes: removing the residual photoresist at the bottom of the groove of the photoresist pattern in the pattern-dense area and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the groove line width defined by it.
[0036] The present invention further comprises the following steps: removing the residual photoresist at the bottom of the photoresist groove in the densely-patterned area of the present invention and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the defined groove line width.
[0037] Figure 2 The photoresist pattern groove 07 after eliminating the load effect is used to uniformly identify the grooves of the photoresist pattern after preprocessing the photoresist pattern in the pattern-dense area and the grooves of the photoresist pattern after preprocessing the photoresist pattern in the pattern-sparse area.
[0038] Step 3, etching the hard mask layer according to the photoresist pattern after eliminating the loading effect until the surface of the SOC layer is exposed to form a hard mask pattern structure; Figure 3 As shown, the hard mask layer is etched according to the photoresist pattern 05 after eliminating the load effect until the surface of the SOC layer 03 is exposed, thereby forming a hard mask pattern structure 08.
[0039] Step 4: etching the SOC layer according to the hard mask pattern until the A-Si surface is exposed to form a SOC pattern structure; Figure 4 As shown, the SOC layer is etched according to the hard mask pattern 08 until the surface of the A-Si layer 02 is exposed, thereby forming a SOC pattern structure 09.
[0040] Furthermore, in the present invention, in step 4 of this embodiment, the SOC layer is etched by dry etching to form a SOC graphic structure.
[0041] Step 5: etching the A-Si layer according to the SOC pattern structure until the surface of the TEOS layer is exposed to form a mandrel structure; Figure 5 As shown, the A-Si layer is etched according to the SOC pattern structure 09 until the surface of the TEOS layer 01 is exposed, thereby forming a mandrel structure 10 .
[0042] The present invention further comprises that in step five of this embodiment, the A-Si layer is etched by dry etching to form the mandrel structure.
[0043] Step 6: Remove the SOC graphic structure to form Figure 6 The structure described.
[0044] The present invention further adopts ashing dry etching to remove the SOC graphic structure in step six of this embodiment.
[0045] In summary, the present invention reduces or even eliminates the loading effect of the photoresist by pre-treating the photoresist before etching, thereby reducing the difference between the groove line width after etching and the defined line width, and also reducing the difference between the groove line width in the pattern-dense area and the pattern line width in the pattern-sparse area. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for adjusting the line width of pattern load in SADP mandrel etching, characterized in that: At least: Step 1, providing a semiconductor structure, the semiconductor structure comprising: a TEOS layer, an A-Si layer, a SOC layer, and a hard mask layer stacked from bottom to top; spin coating a layer of photoresist on the hard mask layer, and then using a photolithography process to define the groove line width, forming a photoresist pattern in a pattern-dense area and a photoresist pattern in a pattern-sparse area, and the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area have a loading effect; Step 2, pre-processing the photoresist pattern in the pattern-dense area and the photoresist pattern in the pattern-sparse area to eliminate the loading effect; Step 3, etching the hard mask layer according to the photoresist pattern after eliminating the loading effect until the surface of the SOC layer is exposed, so as to form a hard mask pattern structure; Step 4, etching the SOC layer according to the hard mask pattern until the A-Si surface is exposed to form a SOC pattern structure; Step 5, etching the A-Si layer according to the SOC pattern structure until the surface of the TEOS layer is exposed to form a mandrel structure; Step six: removing the SOC graphic structure.
2. The method for adjusting pattern load line width in SADP mandrel etching according to claim 1, characterized in that: The loading effect of the photoresist pattern in the pattern-dense area in step one includes photoresist residue at the bottom of the photoresist pattern groove formed after the photolithography process is developed and the sidewall of the photoresist pattern formed after the photolithography process is developed is tilted, resulting in a difference between the line width of the photoresist pattern groove and the groove line width defined by it.
3. The method for adjusting pattern load line width in SADP mandrel etching according to claim 2, characterized in that: The loading effect of the photoresist pattern in the sparse pattern area in step 1 includes photoresist residue at the bottom of the photoresist pattern groove formed after the photolithography process is developed and the sidewall of the photoresist pattern formed after the photolithography process is developed is tilted, resulting in a difference between the groove line width of the photoresist pattern and the groove line width defined by it.
4. The method for adjusting pattern load line width in SADP mandrel etching according to claim 3, characterized in that: In step 1, the difference between the trench line width of the photoresist pattern in the sparse pattern area and the trench line width defined by it is greater than the difference between the trench line width of the photoresist pattern in the dense pattern area and the trench line width defined by it.
5. The method for adjusting pattern load line width in SADP mandrel etching according to claim 1, characterized in that: The hard mask layer in step 1 is a dielectric anti-reflection layer.
6. The method for adjusting pattern load line width in SADP mandrel etching according to claim 1, characterized in that: In step 4, the SOC layer is etched by dry etching to form a SOC graphic structure.
7. The method for adjusting pattern load line width in SADP mandrel etching according to claim 1, characterized in that: In step five, the A-Si layer is etched by dry etching to form the mandrel structure.
8. The method for adjusting pattern load line width in SADP mandrel etching according to claim 1, characterized in that: In step six, ashing dry etching is used to remove the SOC graphic structure.
9. The method for adjusting pattern load line width in SADP mandrel etching according to claim 2, characterized in that: The method for preprocessing the photoresist pattern in the pattern-dense area in step 2 includes: removing the residual photoresist at the bottom of the photoresist pattern groove in the pattern-dense area and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the groove line width defined by it.
10. The method for adjusting pattern load line width in SADP mandrel etching according to claim 2, characterized in that: The method for preprocessing the photoresist pattern in the sparse pattern area in step 2 includes: removing the residual photoresist at the bottom of the photoresist pattern groove in the dense pattern area and using ultraviolet light to eliminate the inclination of the side wall of the photoresist pattern, thereby eliminating the difference between the groove line width of the photoresist pattern and the defined groove line width.