Low-phase-noise four-stage ring oscillator based on novel negative skew delay unit

Abstract

The technical scheme of the invention provides a low-phase-noise four-stage ring oscillator based on a novel negative skew delay unit. The voltage output waveform of the voltage-controlled oscillator of the four-stage negative skew delay unit is more symmetrical, so that the generation of second-order harmonics is reduced. Therefore, the existence of the diode connection type PMOS tube improves the power consumption of the voltage-controlled oscillator, and increases the conversion speed of the output node voltage from high to low, so that the phase noise of the voltage-controlled oscillator of the four-stage negative skew delay unit is reduced by 10dB compared with the phase noise of a voltage-controlled oscillator without an improved structure. According to the invention, the KVCO linearity of the voltage-controlled oscillator of the four-stage negative skew delay unit is improved.

Description

Technical Field

[0001] The invention relates to a voltage-controlled fourth-order ring oscillator circuit with low power consumption, low phase noise, self-bias and small size, and belongs to the field of mixed signal and analog integrated circuits. Background Art

[0002] Voltage controlled oscillator (VCO) is an important circuit structure of digital-analog mixed signal integrated circuits and is widely used in phase-locked loop modules and FPGA modules. Compared with LC oscillators, ring oscillators occupy a smaller chip area and have a simple structure for easy integration. Therefore, ring oscillators are widely used to generate clock signals in digital chips such as SOC chips and data storage chips. In addition, the traditional ring oscillator structure also includes a voltage control circuit and a bias circuit. The voltage control circuit uses voltage changes to change the current flowing into the inverter, thereby controlling the frequency of the ring oscillator. The bias circuit provides the DC operating point of the voltage controlled oscillator.

[0003] Conventional ring oscillators such as Figure 1 As shown, it is usually composed of three or five odd-numbered inverters in cascade, using the phase difference between the inverters to generate a total phase shift of more than 360° and cause oscillation. If an even-numbered oscillator is required, a differential structure is generally required, such as Figure 2 As shown. However, the differential ring oscillator consumes a larger area. In order to further reduce the circuit size, Seog-Jun Lee et al. proposed a four-stage cascaded ring oscillator based on a negative skewed delay structure (Negative skewed delay scheme) [1,2]. The PMOS of the i-th stage (i≥4) of the oscillator is driven by the output of the (i-2) stage, and the NMOS of the i-th stage is driven by the output of the (i-1) stage. The input signal always reaches the PMOS first. The delayed input causes each PMOS and NMOS of the negative skewed delay structure to exist in four states within one oscillation cycle: "switch", "on-on", "off-on" and "off-off". Since the speed of PMOS is slower than that of NMOS, allowing the PMOS transistor to receive the shutdown signal in advance can speed up the conversion speed of the node output voltage from high to low. The schematic diagram of the four-stage ring oscillator based on the negative skewed delay structure is shown in Figure 3As shown, the gate voltage of the tail current source M1 is used to control the oscillation frequency of the voltage-controlled oscillator, and the oscillation frequency increases with the increase of current. Under the working condition of VDD=1.2V, the original structure can achieve a voltage swing of 0.2V to 1.2V and a frequency swing of 4 orders of magnitude. In the figure, M1, M2, M3, M4, and M5 are marked as NMOS tubes, among which M1 is the tail current source of the oscillator. M6, M7, M8, and M9 are PMOS tubes, and vb1, vb2, vb3, and vb4 are the drain voltages of M6, M7, M8, and M9 tubes, that is, the node voltages mentioned below. vdd is the power supply voltage, gnd is the power ground, and Vc is the gate voltage of M1. Summary of the invention

[0004] There are two technical problems in the traditional voltage-controlled oscillator based on the negative-skew delay structure: first, the working state of the tail current source M1 needs to change in a wide range from the subthreshold region to the linear region, which is not conducive to improving the linearity of the voltage-controlled oscillator KVCO; second, within a single oscillation cycle, a single negative-skew delay structure has a phase where NMOS and PMOS are turned on at the same time. As the vibration frequency decreases, the speed difference between PMOS and NMOS becomes more and more obvious, and the time required for PMOS to turn off and NMOS to turn on increases, resulting in a long "step" in the process of the node voltage changing from high to low. The appearance of the "step" causes the rising and falling edges of the output waveform to be asymmetric, increasing the phase noise of the voltage-controlled oscillator.

[0005] In order to solve the above technical problems, the technical solution of the present invention is to provide a low phase noise four-stage ring oscillator based on a novel negative skew delay unit, characterized in that it includes PMOS tubes M6, M7, M8, M9, NMOS tubes M2, M3, M4, M5 and phase noise and linearity optimized PMOS tubes M10, M11, M12, M13, wherein:

[0006] The sources of the PMOS tubes M6, M7, M8, and M9 are connected in parallel and then connected to the power supply voltage, the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M3, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M4, and the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M5; the gate of the PMOS tube M6 is connected to the drain of the NMOS tube M4, the gate of the PMOS tube M7 is connected to the drain of the NMOS tube M5, the gate of the PMOS tube M8 is connected to the drain of the NMOS tube M2, and the gate of the PMOS tube M9 is connected to the drain of the NMOS tube M3;

[0007] The sources of NMOS tubes M2, M3, M4, and M5 are connected in parallel and then connected to the tail current source M1; the gate of NMOS tube M2 is connected to the drain of NMOS tube M5, the gate of NMOS tube M5 is connected to the drain of NMOS tube M4, the gate of NMOS tube M4 is connected to the drain of NMOS tube M2, and the gate of NMOS tube M3 is connected to the drain of NMOS tube M2;

[0008] The sources of the phase noise and linearity optimized PMOS tubes M10, M11, M12, and M13 are connected in parallel and then connected to the power supply voltage; the drain of the phase noise and linearity optimized PMOS tube M10 is short-circuited with the gate, and then connected to the drain of the PMOS tube M6; the drain of the phase noise and linearity optimized PMOS tube M11 is short-circuited with the gate, and then connected to the drain of the PMOS tube M7; the drain of the phase noise and linearity optimized PMOS tube M12 is short-circuited with the gate, and then connected to the drain of the PMOS tube M8; the drain of the phase noise and linearity optimized PMOS tube M13 is short-circuited with the drain, and then connected to the drain of the PMOS tube M9.

[0009] The voltage output waveform of the four-stage negative deflection delay unit voltage-controlled oscillator of the present invention is more symmetrical, thereby reducing the generation of second-order harmonics. This can be explained by the fact that the presence of the diode-connected PMOS tube increases the power consumption of the voltage-controlled oscillator and increases the conversion speed of the output node voltage from high to low, so that the phase noise of the four-stage negative deflection delay unit voltage-controlled oscillator of the present invention is reduced by 10dB compared to the phase noise of the voltage-controlled oscillator without the improved structure. In the present invention, the K VCO The linearity is improved. This can be explained by the fact that the diode-connected PMOS tube reduces the maximum oscillation frequency of the voltage-controlled oscillator, and the impedance at the output node changes more linearly with the voltage, so K VCO The linearity has been improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a traditional ring oscillator;

[0011] Figure 2 It is a schematic diagram of a traditional four-stage differential structure ring oscillator;

[0012] Figure 3 The schematic diagram is a classic structure diagram of a four-stage ring voltage-controlled oscillator based on a negative-skew delay unit;

[0013] Figure 4 Schematic diagram of the structure of a low phase noise four-stage ring oscillator based on a new negative-skew delay unit. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0015] The embodiment of the present invention discloses a non-differential ring oscillator circuit with four output phases, which includes four negative skew delay structures, four phase noise and linearity optimized PMOS tubes and a voltage controlled NMOS tube for controlling the oscillation frequency. The circuit diagram of the scheme is shown in FIG. Figure 4 shown.

[0016] In the i-th (i is equal to 1 to 4) negative skew delay structure, the NMOS tube is sequentially connected to the i-1th port, and the PMOS tube is sequentially connected to the i-2th port, thereby generating an oscillation of an inverter delay cycle on the node voltage vbi of port i. The skew inverter unit circuit does not require any external bias circuit and realizes staggered opening and closing according to the current change inside the loop.

[0017] In each negative skew delay structure, a diode-connected PMOS tube is connected in parallel to the drain end of the PMOS tube as a phase noise and linearity optimization tube, which improves the gain, bandwidth, and K of the oscillator by increasing the circuit size and circuit complexity. VCO Linearity and phase noise.

[0018] The source terminals of the NMOS tubes in the four negative skew delay structures are connected in series with the same NMOS tube tail current source to the ground. The NMOS tube tail current source serves as a voltage control tube for controlling the oscillation frequency.

[0019] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0020] Figure 4 The transistor types numbered M1 to M9 are Figure 3 The PMOS tubes numbered M10, M11, M12, and M13 are four phase noise and linearity optimization tubes.

[0021] In the four-stage negative-skew delay unit voltage-controlled oscillator, the NMOS sources numbered M2, M3, M4, and M5 are connected in parallel and then connected to the tail current source M1. The gate of M2 is connected to the drain of M5, the gate of M5 is connected to the drain of M4, the gate of M4 is connected to the drain of M2, and the gate of M3 is connected to the drain of M2.

[0022] In the four-stage negative-skew delay unit voltage-controlled oscillator, the sources of the four PMOS tubes numbered M6, M7, M8, and M9 are connected in parallel and then connected to the power supply voltage. The drain of M6 is connected to the drain of M2, the drain of M7 is connected to the drain of M3, the drain of M8 is connected to the drain of M4, and the drain of M9 is connected to the drain of M5. The gate of M6 is connected to the drain of M4, the gate of M7 is connected to the drain of M5, the gate of M8 is connected to the drain of M2, and the gate of M9 is connected to the drain of M3.

[0023] The sources of the four phase noise and linearity optimized PMOS tubes, numbered M10, M11, M12, and M13, are connected in parallel and connected to the power supply voltage. The drain of M10 is short-circuited with the gate, and then connected to the drain of M6; the drain of M11 is short-circuited with the gate, and then connected to the drain of M7; the drain of M12 is short-circuited with the gate, and then connected to the drain of M8; the drain of M13 is short-circuited with the drain, and then connected to the drain of M9.

[0024] In the four-stage negative-skew delay unit voltage-controlled oscillator of the present invention, the output gain of each stage of the negative-skew delay unit can be obtained using the following formula (1):

[0025]

[0026] Among them, g mn is the NMOS transconductance, g mp is the PMOS transconductance. Due to the positive feedback characteristics of the node, the small signal impedance of the PMOS is negative. Since the overdrive voltage of the oscillator is constantly changing, g m Select the following formula (2) and substitute it into the calculation:

[0027]

[0028] Where μ is the carrier mobility, W is the MOS tube width, L is the MOS tube length, C is the gate oxide parasitic capacitance, and I is the current flowing through the NMOS transistor and the PMOS transistor. Assuming that the MOS tube gate oxide parasitic capacitance C is small, the difference can be ignored. Then the node gain A1 of the original structure and the node gain A2 of the improved structure are shown in formulas (3) and (4):

[0029]

[0030] Wherein, a and b are the proportional coefficients of the current I flowing through the two PMOS transistors. Under the appropriate size, the static small signal gain of the improved single negative skew delay unit is improved to meet the gain requirement of the ring oscillator start-up.

Claims

1. A low phase noise four-stage ring oscillator based on a novel negative skew delay unit, characterized in that: Including PMOS tubes M6, M7, M8, M9, NMOS tubes M2, M3, M4, M5 and phase noise and linearity optimized PMOS tubes M10, M11, M12, M13, among which: The sources of the PMOS tubes M6, M7, M8, and M9 are connected in parallel and then connected to the power supply voltage, the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M3, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M4, and the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M5; the gate of the PMOS tube M6 is connected to the drain of the NMOS tube M4, the gate of the PMOS tube M7 is connected to the drain of the NMOS tube M5, the gate of the PMOS tube M8 is connected to the drain of the NMOS tube M2, and the gate of the PMOS tube M9 is connected to the drain of the NMOS tube M3; The sources of NMOS tubes M2, M3, M4, and M5 are connected in parallel and then connected to the tail current source M1; the gate of NMOS tube M2 is connected to the drain of NMOS tube M5, the gate of NMOS tube M5 is connected to the drain of NMOS tube M4, the gate of NMOS tube M4 is connected to the drain of NMOS tube M2, and the gate of NMOS tube M3 is connected to the drain of NMOS tube M2; The sources of the phase noise and linearity optimized PMOS tubes M10, M11, M12, and M13 are connected in parallel and then connected to the power supply voltage; the drain of the phase noise and linearity optimized PMOS tube M10 is short-circuited with the gate, and then connected to the drain of the PMOS tube M6; the drain of the phase noise and linearity optimized PMOS tube M11 is short-circuited with the gate, and then connected to the drain of the PMOS tube M7; the drain of the phase noise and linearity optimized PMOS tube M12 is short-circuited with the gate, and then connected to the drain of the PMOS tube M8; the drain of the phase noise and linearity optimized PMOS tube M13 is short-circuited with the drain, and then connected to the drain of the PMOS tube M9.

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